From: Yakir Yang <ykk@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>,
Thierry Reding <treding@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
Inki Dae <inki.dae@samsung.com>,
joe@perches.com, Kukjin Kim <kgene@kernel.org>,
Krzysztof Kozlowski <k.kozlowski@samsung.com>,
Mark Yao <mark.yao@rock-chips.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>,
djkurtz@chromium.com, dianders@chromium.com,
seanpaul@chromium.com, ajaynumb@gmail.com,
Andrzej Hajda <a.hajda@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
David Airlie <airlied@linux.ie>,
Gustavo Padovan <gustavo.padovan@collabora.co.uk>,
Andy Yan <andy.yan@rock-chips.com>,
Kumar Gala <galak@codeaurora.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
architt@codeaurora.org, robherring2@gmail.com,
Yakir Yang <ykk@rock-chips.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
Date: Tue, 1 Sep 2015 14:01:28 +0800 [thread overview]
Message-ID: <1441087288-25404-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1441086371-24838-1-git-send-email-ykk@rock-chips.com>
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.
Changes in v2:
- Take Heiko suggest, get panel node with remote-endpoint method,
and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
.../bindings/video/analogix_dp-rockchip.txt | 74 ++++
drivers/gpu/drm/rockchip/Kconfig | 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 389 +++++++++++++++++++++
4 files changed, 473 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..502483e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+ dp-controller: dp@ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff970000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ status = "disabled";
+
+ ports {
+ edp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_ANALOGIX_DP
+ tristate "Rockchip specific extensions for Analogix DP driver"
+ depends on DRM_ROCKCHIP
+ select DRM_ANALOGIX_DP
+ help
+ This selects support for Rockchip SoC specific extensions
+ for the Analogix Core DP driver. If you want to enable DP
+ on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..cebff9e
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,389 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * Yakir Yang <ykk@rock-chips.com>
+ * Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define encoder_to_dp(c) \
+ container_of(c, struct rockchip_dp_device, encoder)
+
+#define plat_data_to_dp(pd) \
+ container_of(pd, struct rockchip_dp_device, plat_data)
+
+/* dp grf register offset */
+#define GRF_GPIO7B_IOMUX 0x0070
+#define GPIO7B3_SEL_MASK (0x03 << 6)
+#define GPIO7B3_SEL_EDP_HOTPLUG BIT(7)
+
+#define GRF_SOC_CON6 0x025c
+#define GRF_EDP_LCD_SEL_MASK BIT(5)
+#define GRF_EDP_SEL_VOP_LIT BIT(5)
+#define GRF_EDP_SEL_VOP_BIG 0
+
+struct rockchip_dp_device {
+ struct drm_device *drm_dev;
+ struct device *dev;
+ struct drm_encoder encoder;
+ struct drm_display_mode mode;
+
+ struct clk *pclk;
+ struct regmap *grf;
+ struct reset_control *rst;
+
+ struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+ u32 val;
+ int ret;
+
+ val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
+ ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
+ return ret;
+ }
+
+ reset_control_assert(dp->rst);
+ usleep_range(10, 20);
+ reset_control_deassert(dp->rst);
+
+ return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+ struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+ int ret;
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+ return ret;
+ }
+
+ ret = rockchip_dp_pre_init(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+ struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+
+ clk_disable_unprepare(dp->pclk);
+
+ return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ /* do nothing */
+ return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted)
+{
+ /* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+ struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+ u32 val;
+ int ret;
+
+ ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+ DRM_MODE_CONNECTOR_eDP,
+ ROCKCHIP_OUT_MODE_AAAA);
+ if (ret < 0) {
+ dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+ return;
+ }
+
+ ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+ if (ret < 0)
+ return;
+
+ if (ret)
+ val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+ else
+ val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+ dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+ return;
+ }
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+ /* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+ .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+ .mode_set = rockchip_dp_drm_encoder_mode_set,
+ .prepare = rockchip_dp_drm_encoder_prepare,
+ .commit = rockchip_dp_drm_encoder_nop,
+ .disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+ .destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "failed to get rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ dp->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dp->pclk)) {
+ dev_err(dev, "failed to get pclk property\n");
+ return PTR_ERR(dp->pclk);
+ }
+
+ dp->rst = devm_reset_control_get(dev, "dp");
+ if (IS_ERR(dp->rst)) {
+ dev_err(dev, "failed to get dp reset control\n");
+ return PTR_ERR(dp->rst);
+ }
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+ return ret;
+ }
+
+ ret = rockchip_dp_pre_init(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to pre init %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+ struct drm_encoder *encoder = &dp->encoder;
+ struct drm_device *drm_dev = dp->drm_dev;
+ struct device *dev = dp->dev;
+ int ret;
+
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+ dev->of_node);
+ DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+ ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS);
+ if (ret) {
+ DRM_ERROR("failed to initialize encoder with drm\n");
+ return ret;
+ }
+
+ drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+ return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int ret;
+
+ /*
+ * Just like the probe function said, we don't need the
+ * device drvrate anymore, we should leave the charge to
+ * analogix dp driver, set the device drvdata to NULL.
+ */
+ dev_set_drvdata(dev, NULL);
+
+ ret = rockchip_dp_init(dp);
+ if (ret < 0)
+ return ret;
+
+ dp->drm_dev = drm_dev;
+
+ ret = rockchip_dp_drm_create_encoder(dp);
+ if (ret) {
+ DRM_ERROR("failed to create drm encoder\n");
+ return ret;
+ }
+
+ dp->plat_data.attach = NULL;
+ dp->plat_data.get_modes = NULL;
+ dp->plat_data.power_on = rockchip_dp_poweron;
+ dp->plat_data.power_off = rockchip_dp_powerdown;
+
+ return analogix_dp_bind(dev, dp->drm_dev, &dp->encoder,
+ &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+ .bind = rockchip_dp_bind,
+ .unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *panel_node, *port, *endpoint;
+ struct rockchip_dp_device *dp;
+ struct drm_panel *panel;
+
+ port = of_graph_get_port_by_id(dev->of_node, 1);
+ if (!port) {
+ dev_err(dev, "can't find output port\n");
+ return -EINVAL;
+ }
+
+ endpoint = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (!endpoint) {
+ dev_err(dev, "no output endpoint found\n");
+ return -EINVAL;
+ }
+
+ panel_node = of_graph_get_remote_port_parent(endpoint);
+ of_node_put(endpoint);
+ if (!panel_node) {
+ dev_err(dev, "no output node found\n");
+ return -EINVAL;
+ }
+
+ panel = of_drm_find_panel(panel_node);
+ if (!panel) {
+ DRM_ERROR("failed to find panel\n");
+ of_node_put(panel_node);
+ return -EPROBE_DEFER;
+ }
+
+ of_node_put(panel_node);
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (!dp)
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->plat_data.panel = panel;
+
+ /*
+ * We just use the drvdata until driver run into component
+ * add function, and then we would set drvdata to null, so
+ * that analogix dp driver could take charge of the drvdata.
+ */
+ platform_set_drvdata(pdev, dp);
+
+ return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+ return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+ return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+ {.compatible = "rockchip,rk3288-dp",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+ .probe = rockchip_dp_probe,
+ .remove = rockchip_dp_remove,
+ .driver = {
+ .name = "rockchip-dp",
+ .owner = THIS_MODULE,
+ .pm = &rockchip_dp_pm_ops,
+ .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+ },
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
--
2.1.2
next prev parent reply other threads:[~2015-09-01 6:01 UTC|newest]
Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-01 5:46 [PATCH v4 0/16] Add Analogix Core Display Port Driver Yakir Yang
2015-09-01 5:46 ` [PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang
2015-09-03 0:21 ` Krzysztof Kozlowski
2015-09-03 5:04 ` Yakir Yang
2015-09-03 5:08 ` Krzysztof Kozlowski
2015-09-03 5:33 ` Yakir Yang
2015-09-03 5:57 ` Joe Perches
2015-09-06 1:33 ` Yakir Yang
2015-09-01 5:49 ` [PATCH v4 02/16] drm: exynos/dp: convert to drm bridge mode Yakir Yang
2015-09-01 5:49 ` [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang
2015-09-01 20:46 ` Heiko Stuebner
2015-09-02 1:45 ` Yakir Yang
2015-09-04 21:06 ` Rob Herring
2015-09-04 21:29 ` Heiko Stuebner
2015-09-07 8:11 ` Thierry Reding
2015-09-02 14:50 ` Emil Velikov
2015-09-03 3:55 ` Yakir Yang
2015-09-03 0:58 ` Krzysztof Kozlowski
2015-09-03 5:30 ` Yakir Yang
2015-09-04 0:41 ` Krzysztof Kozlowski
2015-09-06 7:49 ` Yakir Yang
2015-09-07 0:22 ` Krzysztof Kozlowski
2015-09-07 2:27 ` Yakir Yang
2015-09-01 5:52 ` [PATCH v4 04/16] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-09-01 5:55 ` [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang
2015-09-03 8:04 ` Krzysztof Kozlowski
2015-09-06 2:00 ` Yakir Yang
2015-09-01 5:58 ` [PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-01 6:01 ` [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-09-03 0:01 ` Krzysztof Kozlowski
2015-09-01 6:01 ` Yakir Yang [this message]
2015-09-01 14:24 ` [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Heiko Stuebner
2015-09-01 14:48 ` Yakir Yang
2015-09-01 21:00 ` Heiko Stuebner
2015-09-02 1:52 ` Yakir Yang
2015-09-01 6:01 ` [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang
2015-09-01 21:00 ` Heiko Stuebner
2015-09-02 2:06 ` Yakir Yang
2015-09-02 8:34 ` Thierry Reding
2015-09-02 10:02 ` Yakir Yang
2015-09-03 8:38 ` Thierry Reding
2015-09-06 2:06 ` Yakir Yang
2015-09-01 6:04 ` [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-09-01 16:51 ` Heiko Stuebner
2015-09-01 20:58 ` Heiko Stuebner
2015-09-02 1:46 ` Yakir Yang
2015-09-02 1:02 ` Yakir Yang
2015-09-02 13:27 ` Rob Herring
2015-09-03 3:25 ` Yakir Yang
2015-09-03 13:52 ` Heiko Stuebner
2015-09-01 6:07 ` [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Yakir Yang
2015-09-04 0:36 ` Krzysztof Kozlowski
2015-09-06 4:07 ` Yakir Yang
2015-09-06 23:55 ` Krzysztof Kozlowski
2015-09-07 1:47 ` Yakir Yang
2015-09-01 6:09 ` [PATCH v4 12/16] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-09-01 6:11 ` [PATCH v4 13/16] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-09-01 6:14 ` [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-09-02 20:17 ` Rob Herring
2015-09-03 4:27 ` Yakir Yang
2015-09-03 9:04 ` Thierry Reding
2015-09-04 10:20 ` Russell King - ARM Linux
2015-09-07 9:01 ` Thierry Reding
[not found] ` <55EBBA0C.1030100@rock-chips.com>
2015-09-07 8:20 ` Thierry Reding
2015-09-04 21:46 ` Rob Herring
2015-09-06 8:20 ` Yakir Yang
2015-09-07 8:39 ` Thierry Reding
2015-09-03 8:47 ` Thierry Reding
2015-09-03 21:55 ` Rob Herring
2015-09-04 10:01 ` Thierry Reding
2015-09-01 6:17 ` [PATCH v4 15/16] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-09-01 6:20 ` [PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-09-01 21:47 ` [PATCH v4 0/16] Add Analogix Core Display Port Driver Heiko Stuebner
2015-09-02 2:15 ` Yakir Yang
[not found] ` <55FFC3B8.9030108@rock-chips.com>
2015-09-21 9:15 ` Thierry Reding
2015-09-21 10:27 ` Yakir Yang
2015-09-21 11:22 ` Thierry Reding
2015-09-22 7:20 ` [PATCH v5 0/17] " Yakir Yang
2015-09-22 7:26 ` [PATCH v5 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2015-09-22 7:29 ` [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-09-30 5:17 ` Krzysztof Kozlowski
2015-09-30 6:48 ` Yakir Yang
2015-09-22 7:34 ` [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-09-30 5:22 ` Krzysztof Kozlowski
2015-09-30 6:52 ` Yakir Yang
2015-09-22 7:35 ` [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-09-22 7:37 ` [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-09-30 5:32 ` Krzysztof Kozlowski
[not found] ` <560B8CF1.7050102@rock-chips.com>
2015-09-30 7:34 ` Krzysztof Kozlowski
[not found] ` <560B9B33.2060409@rock-chips.com>
2015-09-30 8:26 ` Krzysztof Kozlowski
2015-09-30 9:39 ` Yakir Yang
2015-09-22 7:40 ` [PATCH v5 06/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-22 7:43 ` [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-09-30 5:39 ` Krzysztof Kozlowski
2015-09-30 7:20 ` Yakir Yang
2015-09-22 7:45 ` [PATCH v5 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-09-22 7:48 ` [PATCH v5 09/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-22 7:48 ` [PATCH v5 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-09-22 7:51 ` [PATCH v5 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang
2015-09-22 7:55 ` [PATCH v5 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-09-22 7:57 ` [PATCH v5 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-09-22 8:00 ` [PATCH v5 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-09-22 8:02 ` [PATCH v5 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-09-22 8:05 ` [PATCH v5 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-09-22 8:07 ` [PATCH v5 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-10-07 6:25 ` [PATCH v5 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-07 8:46 ` Javier Martinez Canillas
2015-10-07 9:02 ` Yakir Yang
2015-10-07 9:26 ` Javier Martinez Canillas
[not found] ` <5614FC6B.4080702@rock-chips.com>
2015-10-07 11:25 ` Javier Martinez Canillas
2015-10-08 0:40 ` Yakir Yang
2015-10-10 14:31 ` Yakir Yang
2015-10-13 9:21 ` Javier Martinez Canillas
2015-10-13 13:50 ` Yakir Yang
2015-10-14 8:18 ` Javier Martinez Canillas
2015-10-10 15:35 ` [PATCH v6 " Yakir Yang
2015-10-10 15:38 ` [PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2015-10-10 15:39 ` [PATCH v6 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-10-10 15:41 ` [PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-10-10 15:43 ` [PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-10-10 15:46 ` [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-12 0:37 ` Yakir Yang
2015-10-12 0:49 ` Krzysztof Kozlowski
2015-10-12 2:43 ` Yakir Yang
2015-10-12 3:51 ` Krzysztof Kozlowski
2015-10-12 4:09 ` Yakir Yang
2015-10-12 4:16 ` Krzysztof Kozlowski
2015-10-10 15:49 ` [PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-10-10 15:49 ` [PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-10-10 15:51 ` [PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-10-10 15:53 ` [PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-10-10 15:55 ` [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-10-12 15:02 ` Kishon Vijay Abraham I
2015-10-12 16:18 ` Heiko Stübner
2015-10-13 1:20 ` Yakir Yang
2015-10-10 15:58 ` [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang
2015-10-12 22:28 ` Kishon Vijay Abraham I
2015-10-13 1:21 ` Yakir Yang
2015-10-10 16:00 ` [PATCH v6 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-10-10 16:05 ` [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-10-10 16:05 ` [PATCH v6 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-10-10 16:05 ` [PATCH v6 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-10-10 16:05 ` [PATCH v6 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-10-10 16:06 ` [PATCH v6 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-10-12 4:29 ` [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-12 6:54 ` Krzysztof Kozlowski
2015-10-12 7:20 ` Yakir Yang
2015-10-19 10:40 ` [PATCH v6 0/17] Add Analogix Core Display Port Driver Javier Martinez Canillas
2015-10-20 2:10 ` Yakir Yang
2015-10-20 9:48 ` Javier Martinez Canillas
2015-10-20 11:40 ` Yakir Yang
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