* [PATCH v2] clk: si5351: Add PLL soft reset [not found] <CAEnXRPvCLRDFotc8FkS35df1PoLUW=X=1bTTUHR=UhRU_9zrCw@mail.gmail.com> @ 2015-11-20 17:22 ` Jacob Siverskog 2015-11-20 17:22 ` Jacob Siverskog 0 siblings, 1 reply; 6+ messages in thread From: Jacob Siverskog @ 2015-11-20 17:22 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Sebastian Hesselbarth, linux-kernel, linux-clk Cc: Belisko Marek, Jacob Siverskog Hi! A representative from SiLabs writes: "All the currently published versions of the Si5351 (v1.0) and AN619 (v0.6) do not include the “Si5351A/C only” disclaimer. Based on this and our current understanding, I see no issue performing a PLLB reset for ‘B’ type devices.". Hence, it should not be any issues always performing the PLL reset. Changes in v2: - Output disabling and power down removed in order to prevent breaking systems requiring always-enabled clocks - Cosmetic changes Jacob Jacob Siverskog (1): clk: si5351: Add PLL soft reset drivers/clk/clk-si5351.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.6.3 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] clk: si5351: Add PLL soft reset 2015-11-20 17:22 ` [PATCH v2] clk: si5351: Add PLL soft reset Jacob Siverskog @ 2015-11-20 17:22 ` Jacob Siverskog 2015-11-20 17:55 ` Sebastian Hesselbarth 0 siblings, 1 reply; 6+ messages in thread From: Jacob Siverskog @ 2015-11-20 17:22 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Sebastian Hesselbarth, linux-kernel, linux-clk Cc: Belisko Marek, Jacob Siverskog, Jens Rudberg This is according to figure 12 ("I2C Programming Procedure") in "Si5351A/B/C Data Sheet" (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). Without the PLL soft reset, we were unable to get three outputs working at the same time. According to Silicon Labs support, performing PLL soft reset will only be noticeable if the PLL parameters have been changed. Signed-off-by: Jacob Siverskog <jacob@teenage.engineering> Signed-off-by: Jens Rudberg <jens@teenage.engineering> --- drivers/clk/clk-si5351.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index e346b22..984c058 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1091,6 +1091,12 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, SI5351_CLK_POWERDOWN, 0); + /* do a pll soft reset on both plls, needed in some cases to get all + * outputs running + */ + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); + dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", __func__, clk_hw_get_name(hw), (1 << rdiv), -- 2.6.3 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] clk: si5351: Add PLL soft reset 2015-11-20 17:22 ` Jacob Siverskog @ 2015-11-20 17:55 ` Sebastian Hesselbarth 2015-11-20 18:03 ` [PATCH v3 0/1] " Jacob Siverskog 0 siblings, 1 reply; 6+ messages in thread From: Sebastian Hesselbarth @ 2015-11-20 17:55 UTC (permalink / raw) To: Jacob Siverskog, Michael Turquette, Stephen Boyd, linux-kernel, linux-clk Cc: Belisko Marek, Jens Rudberg On 20.11.2015 18:22, Jacob Siverskog wrote: > This is according to figure 12 ("I2C Programming Procedure") in > "Si5351A/B/C Data Sheet" > (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). > > Without the PLL soft reset, we were unable to get three outputs > working at the same time. > > According to Silicon Labs support, performing PLL soft reset will only > be noticeable if the PLL parameters have been changed. > > Signed-off-by: Jacob Siverskog <jacob@teenage.engineering> > Signed-off-by: Jens Rudberg <jens@teenage.engineering> > --- > drivers/clk/clk-si5351.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c > index e346b22..984c058 100644 > --- a/drivers/clk/clk-si5351.c > +++ b/drivers/clk/clk-si5351.c > @@ -1091,6 +1091,12 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, > si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, > SI5351_CLK_POWERDOWN, 0); > > + /* do a pll soft reset on both plls, needed in some cases to get all > + * outputs running > + */ Common convention for multi-line comments usually is: /* * Do a PLL soft reset on both PLLs required to get * all outputs running. */ After you fixed the style issue, you can add my Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Thanks! > + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, > + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); > + > dev_dbg(&hwdata->drvdata->client->dev, > "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", > __func__, clk_hw_get_name(hw), (1 << rdiv), > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 0/1] clk: si5351: Add PLL soft reset 2015-11-20 17:55 ` Sebastian Hesselbarth @ 2015-11-20 18:03 ` Jacob Siverskog 2015-11-20 18:03 ` [PATCH v3 1/1] " Jacob Siverskog 0 siblings, 1 reply; 6+ messages in thread From: Jacob Siverskog @ 2015-11-20 18:03 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Sebastian Hesselbarth, linux-kernel, linux-clk Cc: Belisko Marek, Jacob Siverskog Hi! Changes in v3: - Fix multiline comment style Changes in v2: - Output disabling and power down removed in order to prevent breaking systems requiring always-enabled clocks - Cosmetic changes Jacob Jacob Siverskog (1): clk: si5351: Add PLL soft reset drivers/clk/clk-si5351.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.6.3 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/1] clk: si5351: Add PLL soft reset 2015-11-20 18:03 ` [PATCH v3 0/1] " Jacob Siverskog @ 2015-11-20 18:03 ` Jacob Siverskog 2015-11-20 18:41 ` Stephen Boyd 0 siblings, 1 reply; 6+ messages in thread From: Jacob Siverskog @ 2015-11-20 18:03 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Sebastian Hesselbarth, linux-kernel, linux-clk Cc: Belisko Marek, Jacob Siverskog, Jens Rudberg This is according to figure 12 ("I2C Programming Procedure") in "Si5351A/B/C Data Sheet" (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). Without the PLL soft reset, we were unable to get three outputs working at the same time. According to Silicon Labs support, performing PLL soft reset will only be noticeable if the PLL parameters have been changed. Signed-off-by: Jacob Siverskog <jacob@teenage.engineering> Signed-off-by: Jens Rudberg <jens@teenage.engineering> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- drivers/clk/clk-si5351.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index e346b22..850316a 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1091,6 +1091,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, SI5351_CLK_POWERDOWN, 0); + /* + * Do a pll soft reset on both plls, needed in some cases to get + * all outputs running. + */ + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); + dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", __func__, clk_hw_get_name(hw), (1 << rdiv), -- 2.6.3 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/1] clk: si5351: Add PLL soft reset 2015-11-20 18:03 ` [PATCH v3 1/1] " Jacob Siverskog @ 2015-11-20 18:41 ` Stephen Boyd 0 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2015-11-20 18:41 UTC (permalink / raw) To: Jacob Siverskog Cc: Michael Turquette, Sebastian Hesselbarth, linux-kernel, linux-clk, Belisko Marek, Jens Rudberg On 11/20, Jacob Siverskog wrote: > This is according to figure 12 ("I2C Programming Procedure") in > "Si5351A/B/C Data Sheet" > (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). > > Without the PLL soft reset, we were unable to get three outputs > working at the same time. > > According to Silicon Labs support, performing PLL soft reset will only > be noticeable if the PLL parameters have been changed. > > Signed-off-by: Jacob Siverskog <jacob@teenage.engineering> > Signed-off-by: Jens Rudberg <jens@teenage.engineering> > Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <CAEnXRPvCLRDFotc8FkS35df1PoLUW=X=1bTTUHR=UhRU_9zrCw@mail.gmail.com>
2015-11-20 17:22 ` [PATCH v2] clk: si5351: Add PLL soft reset Jacob Siverskog
2015-11-20 17:22 ` Jacob Siverskog
2015-11-20 17:55 ` Sebastian Hesselbarth
2015-11-20 18:03 ` [PATCH v3 0/1] " Jacob Siverskog
2015-11-20 18:03 ` [PATCH v3 1/1] " Jacob Siverskog
2015-11-20 18:41 ` Stephen Boyd
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