[PATCH v2 0/2] mtd: spi-nor: add new device MT35X

[PATCH v2 0/2] mtd: spi-nor: add new device MT35X

[Karl Zhang]

Micron has announced a new SPI NOR device MT35X (XTRMFlash).
This device's manufacturer ID is using 2Ch which arranged by
JEDEC. The 20h is also Micron's ID due to the history.

This new device support high speed I/O interface. The clock
frequency could up to 200 MHz (MAX) in DDR (400 MB/s) with
DQS. The device bus width could be 1 or 8, and it's default
width is configurable.

Karl Zhang (2):
  mtd: spi-nor: add Manufacturer ID for Micron
  mtd: spi-nor: add new device MT35X

 drivers/mtd/spi-nor/spi-nor.c | 2 ++
 include/linux/mtd/cfi.h       | 1 +
 include/linux/mtd/spi-nor.h   | 2 ++
 3 files changed, 5 insertions(+)

-- 
1.9.1

[PATCH v2 1/2] mtd: spi-nor: add Manufacturer ID for Micron

[Karl Zhang]

Micron Manufacturer ID assigned by JEDEC is 2Ch.
Add this ID, for new Spi NOR from Micron.

ST's ID(20h) is Micron due to the history.

Signed-off-by: Karl Zhang <karlzhang@micron.com>
---
 v2: no change

 include/linux/mtd/cfi.h     | 1 +
 include/linux/mtd/spi-nor.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@ struct cfi_fixup {
 #define CFI_MFR_SHARP		0x00B0
 #define CFI_MFR_SST		0x00BF
 #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON		0x002C /* Micron */
 #define CFI_MFR_TOSHIBA		0x0098
 #define CFI_MFR_WINBOND		0x00DA
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fac3f6f..b858e93 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -22,6 +22,8 @@
  */
 #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
 #define SNOR_MFR_INTEL		CFI_MFR_INTEL
+/* Micron Manufacturer ID assigned by JEDEC */
+#define SNOR_MFR_MICRON_JEDEC	CFI_MFR_MICRON
 #define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
 #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
 #define SNOR_MFR_SPANSION	CFI_MFR_AMD
-- 
1.9.1

[PATCH v2 2/2] mtd: spi-nor: add new device MT35X

[Karl Zhang]

Micron has announced a new SPI NOR device MT35X(XTRMFlash).
The device can support x1 or x8 bus I/O for high speed.

This patch is purpose to add MT35X into the arch, only
extended mode (x1) was enabled. Octal mode I/O will be done
in the futrue.

Signed-off-by: Karl Zhang <karlzhang@micron.com>
---
 v2: remove change line for m25p_ids[]

 drivers/mtd/spi-nor/spi-nor.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b2460e..34686b5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -192,6 +192,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
 
 	switch (JEDEC_MFR(info)) {
 	case SNOR_MFR_MICRON:
+	case SNOR_MFR_MICRON_JEDEC:
 		/* Some Micron need WREN command; all will accept it */
 		need_wren = true;
 	case SNOR_MFR_MACRONIX:
@@ -756,6 +757,7 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{ "mt35x512",    INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR) },
 
 	/* PMC */
 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
-- 
1.9.1