* [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip eMMC PHY
@ 2016-01-05 1:07 Shawn Lin
2016-01-05 1:08 ` [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal " Shawn Lin
0 siblings, 1 reply; 6+ messages in thread
From: Shawn Lin @ 2016-01-05 1:07 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: linux-kernel, linux-rockchip, Shawn Lin
This patch adds a binding that describes the Rockchip eMMC PHYs
found on Rockchip SoCs eMMC interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2: None
.../devicetree/bindings/phy/rockchip-emmc-phy.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
new file mode 100644
index 0000000..61916f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -0,0 +1,19 @@
+Rockchip EMMC PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-emmc-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #phy-cells: must be 0
+ - reg: PHY configure reg address offset in "general
+ register files"
+
+Example:
+
+emmcphy: phy {
+ compatible = "rockchip,rk3399-emmc-phy";
+ rockchip,grf = <&grf>;
+ reg = <0xf780>;
+ #phy-cells = <0>;
+};
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal eMMC PHY
2016-01-05 1:07 [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip eMMC PHY Shawn Lin
@ 2016-01-05 1:08 ` Shawn Lin
2016-01-25 7:49 ` Shawn Lin
2016-02-03 6:39 ` Kishon Vijay Abraham I
0 siblings, 2 replies; 6+ messages in thread
From: Shawn Lin @ 2016-01-05 1:08 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: linux-kernel, linux-rockchip, Shawn Lin
This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- remove phy from rockchip_emmc_phy
- remove state from rockchip_emmc_phy
- remove on/off from init/exit
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-emmc.c | 241 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 249 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-emmc.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 03cb3ea..47d16e3 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -320,6 +320,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_EMMC
+ tristate "Rockchip EMMC PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip EMMC PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..ed8f175 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
new file mode 100644
index 0000000..6a157c2
--- /dev/null
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -0,0 +1,241 @@
+/*
+ * Rockchip emmc PHY driver
+ *
+ * Copyright (C) 2015 Shawn Lin <shawn.lin@rock-chips.com>
+ * Copyright (C) 2015 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+/* Register definition */
+#define GRF_EMMCPHY_CON0 0x0
+#define GRF_EMMCPHY_CON1 0x4
+#define GRF_EMMCPHY_CON2 0x8
+#define GRF_EMMCPHY_CON3 0xc
+#define GRF_EMMCPHY_CON4 0x10
+#define GRF_EMMCPHY_CON5 0x14
+#define GRF_EMMCPHY_CON6 0x18
+#define GRF_EMMCPHY_STATUS 0x20
+
+#define PHYCTRL_PDB_MASK 0x1
+#define PHYCTRL_PDB_SHIFT 0x0
+#define PHYCTRL_PDB_PWR_ON 0x1
+#define PHYCTRL_PDB_PWR_OFF 0x0
+#define PHYCTRL_ENDLL_MASK 0x1
+#define PHYCTRL_ENDLL_SHIFT 0x1
+#define PHYCTRL_ENDLL_ENABLE 0x1
+#define PHYCTRL_ENDLL_DISABLE 0x0
+#define PHYCTRL_CALDONE_MASK 0x1
+#define PHYCTRL_CALDONE_SHIFT 0x6
+#define PHYCTRL_CALDONE_DONE 0x1
+#define PHYCTRL_CALDONE_GOING 0x0
+#define PHYCTRL_DLLRDY_MASK 0x1
+#define PHYCTRL_DLLRDY_SHIFT 0x5
+#define PHYCTRL_DLLRDY_DONE 0x1
+#define PHYCTRL_DLLRDY_GOING 0x0
+
+struct rockchip_emmc_phy {
+ unsigned int reg_offset;
+ struct regmap *reg_base;
+};
+
+static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
+ bool on_off)
+{
+ unsigned int caldone;
+ unsigned int dllrdy;
+
+ /*
+ * Keep phyctrl_pdb and phyctrl_endll low to allow
+ * initialization of CALIO state M/C DFFs
+ */
+ regmap_write(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+ HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
+ PHYCTRL_PDB_MASK,
+ PHYCTRL_PDB_SHIFT));
+ regmap_write(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+ HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
+ PHYCTRL_ENDLL_MASK,
+ PHYCTRL_ENDLL_SHIFT));
+
+ /* Already finish power_off above */
+ if (on_off == PHYCTRL_PDB_PWR_OFF)
+ return 0;
+
+ /*
+ * According to the user manual, calpad calibration
+ * cycle takes more than 2us without the minimal recommended
+ * value, so we may need a little margin here
+ */
+ udelay(3);
+ regmap_write(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+ HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
+ PHYCTRL_PDB_MASK,
+ PHYCTRL_PDB_SHIFT));
+
+ /*
+ * According to the user manual, it asks driver to
+ * wait 5us for calpad busy trimming
+ */
+ udelay(5);
+ regmap_read(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ &caldone);
+ caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
+ if (caldone != PHYCTRL_CALDONE_DONE) {
+ pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
+ return -ETIMEDOUT;
+ }
+
+ /*
+ * Enable analog DLL circuits, and we need extra 10.2us
+ * for dll to be ready for work.
+ */
+ regmap_write(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_CON6,
+ HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
+ PHYCTRL_ENDLL_MASK,
+ PHYCTRL_ENDLL_SHIFT));
+ udelay(11);
+ regmap_read(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ &dllrdy);
+ dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
+ if (dllrdy != PHYCTRL_DLLRDY_DONE) {
+ pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int rockchip_emmc_phy_power_off(struct phy *phy)
+{
+ struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
+ int ret = 0;
+
+ /* Power down emmc phy analog blocks */
+ ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_emmc_phy_power_on(struct phy *phy)
+{
+ struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
+ int ret = 0;
+
+ /* Power up emmc phy analog blocks */
+ ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_emmc_phy_init(struct phy *phy)
+{
+ return 0;
+}
+
+static int rockchip_emmc_phy_exit(struct phy *phy)
+{
+ return 0;
+}
+
+static const struct phy_ops ops = {
+ .init = rockchip_emmc_phy_init,
+ .exit = rockchip_emmc_phy_exit,
+ .power_on = rockchip_emmc_phy_power_on,
+ .power_off = rockchip_emmc_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_emmc_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rockchip_emmc_phy *rk_phy;
+ struct phy *generic_phy;
+ struct phy_provider *phy_provider;
+ struct regmap *grf;
+ unsigned int reg_offset;
+
+ grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
+ if (IS_ERR(grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return PTR_ERR(grf);
+ }
+
+ rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
+ if (!rk_phy)
+ return -ENOMEM;
+
+ if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
+ dev_err(dev, "missing reg property in node %s\n",
+ dev->of_node->name);
+ return -EINVAL;
+ }
+
+ rk_phy->reg_offset = reg_offset;
+ rk_phy->reg_base = grf;
+
+ generic_phy = devm_phy_create(dev, dev->of_node, &ops);
+ if (IS_ERR(generic_phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(generic_phy);
+ }
+
+ phy_set_drvdata(generic_phy, rk_phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3399-emmc-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
+
+static struct platform_driver rockchip_emmc_driver = {
+ .probe = rockchip_emmc_phy_probe,
+ .driver = {
+ .name = "rockchip-emmc-phy",
+ .of_match_table = rockchip_emmc_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_emmc_driver);
+
+MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.3.7
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal eMMC PHY
2016-01-05 1:08 ` [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal " Shawn Lin
@ 2016-01-25 7:49 ` Shawn Lin
2016-02-01 6:03 ` Kishon Vijay Abraham I
2016-02-03 6:39 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 6+ messages in thread
From: Shawn Lin @ 2016-01-25 7:49 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: shawn.lin, linux-kernel, linux-rockchip
Hello Kishon,
Any changce to apply this patch? :)
On 2016/1/5 9:08, Shawn Lin wrote:
> This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
> Access the PHY via registers provided by GRF (general register
> files) module.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
>
> Changes in v2:
> - remove phy from rockchip_emmc_phy
> - remove state from rockchip_emmc_phy
> - remove on/off from init/exit
>
> drivers/phy/Kconfig | 7 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-emmc.c | 241 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 249 insertions(+)
> create mode 100644 drivers/phy/phy-rockchip-emmc.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 03cb3ea..47d16e3 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -320,6 +320,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_EMMC
> + tristate "Rockchip EMMC PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip EMMC PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 075db1a..ed8f175 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
> new file mode 100644
> index 0000000..6a157c2
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-emmc.c
> @@ -0,0 +1,241 @@
> +/*
> + * Rockchip emmc PHY driver
> + *
> + * Copyright (C) 2015 Shawn Lin <shawn.lin@rock-chips.com>
> + * Copyright (C) 2015 ROCKCHIP, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +/*
> + * The higher 16-bit of this register is used for write protection
> + * only if BIT(x + 16) set to 1 the BIT(x) can be written.
> + */
> +#define HIWORD_UPDATE(val, mask, shift) \
> + ((val) << (shift) | (mask) << ((shift) + 16))
> +
> +/* Register definition */
> +#define GRF_EMMCPHY_CON0 0x0
> +#define GRF_EMMCPHY_CON1 0x4
> +#define GRF_EMMCPHY_CON2 0x8
> +#define GRF_EMMCPHY_CON3 0xc
> +#define GRF_EMMCPHY_CON4 0x10
> +#define GRF_EMMCPHY_CON5 0x14
> +#define GRF_EMMCPHY_CON6 0x18
> +#define GRF_EMMCPHY_STATUS 0x20
> +
> +#define PHYCTRL_PDB_MASK 0x1
> +#define PHYCTRL_PDB_SHIFT 0x0
> +#define PHYCTRL_PDB_PWR_ON 0x1
> +#define PHYCTRL_PDB_PWR_OFF 0x0
> +#define PHYCTRL_ENDLL_MASK 0x1
> +#define PHYCTRL_ENDLL_SHIFT 0x1
> +#define PHYCTRL_ENDLL_ENABLE 0x1
> +#define PHYCTRL_ENDLL_DISABLE 0x0
> +#define PHYCTRL_CALDONE_MASK 0x1
> +#define PHYCTRL_CALDONE_SHIFT 0x6
> +#define PHYCTRL_CALDONE_DONE 0x1
> +#define PHYCTRL_CALDONE_GOING 0x0
> +#define PHYCTRL_DLLRDY_MASK 0x1
> +#define PHYCTRL_DLLRDY_SHIFT 0x5
> +#define PHYCTRL_DLLRDY_DONE 0x1
> +#define PHYCTRL_DLLRDY_GOING 0x0
> +
> +struct rockchip_emmc_phy {
> + unsigned int reg_offset;
> + struct regmap *reg_base;
> +};
> +
> +static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
> + bool on_off)
> +{
> + unsigned int caldone;
> + unsigned int dllrdy;
> +
> + /*
> + * Keep phyctrl_pdb and phyctrl_endll low to allow
> + * initialization of CALIO state M/C DFFs
> + */
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
> + PHYCTRL_PDB_MASK,
> + PHYCTRL_PDB_SHIFT));
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
> + PHYCTRL_ENDLL_MASK,
> + PHYCTRL_ENDLL_SHIFT));
> +
> + /* Already finish power_off above */
> + if (on_off == PHYCTRL_PDB_PWR_OFF)
> + return 0;
> +
> + /*
> + * According to the user manual, calpad calibration
> + * cycle takes more than 2us without the minimal recommended
> + * value, so we may need a little margin here
> + */
> + udelay(3);
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
> + PHYCTRL_PDB_MASK,
> + PHYCTRL_PDB_SHIFT));
> +
> + /*
> + * According to the user manual, it asks driver to
> + * wait 5us for calpad busy trimming
> + */
> + udelay(5);
> + regmap_read(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
> + &caldone);
> + caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
> + if (caldone != PHYCTRL_CALDONE_DONE) {
> + pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
> + return -ETIMEDOUT;
> + }
> +
> + /*
> + * Enable analog DLL circuits, and we need extra 10.2us
> + * for dll to be ready for work.
> + */
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
> + PHYCTRL_ENDLL_MASK,
> + PHYCTRL_ENDLL_SHIFT));
> + udelay(11);
> + regmap_read(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
> + &dllrdy);
> + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
> + if (dllrdy != PHYCTRL_DLLRDY_DONE) {
> + pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_power_off(struct phy *phy)
> +{
> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + /* Power down emmc phy analog blocks */
> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_power_on(struct phy *phy)
> +{
> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + /* Power up emmc phy analog blocks */
> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_init(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_exit(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static const struct phy_ops ops = {
> + .init = rockchip_emmc_phy_init,
> + .exit = rockchip_emmc_phy_exit,
> + .power_on = rockchip_emmc_phy_power_on,
> + .power_off = rockchip_emmc_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int rockchip_emmc_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rockchip_emmc_phy *rk_phy;
> + struct phy *generic_phy;
> + struct phy_provider *phy_provider;
> + struct regmap *grf;
> + unsigned int reg_offset;
> +
> + grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
> + if (IS_ERR(grf)) {
> + dev_err(dev, "Missing rockchip,grf property\n");
> + return PTR_ERR(grf);
> + }
> +
> + rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
> + if (!rk_phy)
> + return -ENOMEM;
> +
> + if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
> + dev_err(dev, "missing reg property in node %s\n",
> + dev->of_node->name);
> + return -EINVAL;
> + }
> +
> + rk_phy->reg_offset = reg_offset;
> + rk_phy->reg_base = grf;
> +
> + generic_phy = devm_phy_create(dev, dev->of_node, &ops);
> + if (IS_ERR(generic_phy)) {
> + dev_err(dev, "failed to create PHY\n");
> + return PTR_ERR(generic_phy);
> + }
> +
> + phy_set_drvdata(generic_phy, rk_phy);
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
> + { .compatible = "rockchip,rk3399-emmc-phy" },
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
> +
> +static struct platform_driver rockchip_emmc_driver = {
> + .probe = rockchip_emmc_phy_probe,
> + .driver = {
> + .name = "rockchip-emmc-phy",
> + .of_match_table = rockchip_emmc_phy_dt_ids,
> + },
> +};
> +
> +module_platform_driver(rockchip_emmc_driver);
> +
> +MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
> +MODULE_LICENSE("GPL v2");
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal eMMC PHY
2016-01-25 7:49 ` Shawn Lin
@ 2016-02-01 6:03 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 6+ messages in thread
From: Kishon Vijay Abraham I @ 2016-02-01 6:03 UTC (permalink / raw)
To: Shawn Lin; +Cc: linux-kernel, linux-rockchip
On Monday 25 January 2016 01:19 PM, Shawn Lin wrote:
> Hello Kishon,
>
> Any changce to apply this patch? :)
back from vacation. Will review it this week. Sorry for the delay.
Thanks
Kishon
>
> On 2016/1/5 9:08, Shawn Lin wrote:
>> This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
>> Access the PHY via registers provided by GRF (general register
>> files) module.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> ---
>>
>> Changes in v2:
>> - remove phy from rockchip_emmc_phy
>> - remove state from rockchip_emmc_phy
>> - remove on/off from init/exit
>>
>> drivers/phy/Kconfig | 7 ++
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-rockchip-emmc.c | 241 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 249 insertions(+)
>> create mode 100644 drivers/phy/phy-rockchip-emmc.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 03cb3ea..47d16e3 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -320,6 +320,13 @@ config PHY_ROCKCHIP_USB
>> help
>> Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_EMMC
>> + tristate "Rockchip EMMC PHY Driver"
>> + depends on ARCH_ROCKCHIP && OF
>> + select GENERIC_PHY
>> + help
>> + Enable this to support the Rockchip EMMC PHY.
>> +
>> config PHY_ST_SPEAR1310_MIPHY
>> tristate "ST SPEAR1310-MIPHY driver"
>> select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 075db1a..ed8f175 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) +=
>> phy-s5pv210-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
>> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
>> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
>> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
>> new file mode 100644
>> index 0000000..6a157c2
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-emmc.c
>> @@ -0,0 +1,241 @@
>> +/*
>> + * Rockchip emmc PHY driver
>> + *
>> + * Copyright (C) 2015 Shawn Lin <shawn.lin@rock-chips.com>
>> + * Copyright (C) 2015 ROCKCHIP, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +/*
>> + * The higher 16-bit of this register is used for write protection
>> + * only if BIT(x + 16) set to 1 the BIT(x) can be written.
>> + */
>> +#define HIWORD_UPDATE(val, mask, shift) \
>> + ((val) << (shift) | (mask) << ((shift) + 16))
>> +
>> +/* Register definition */
>> +#define GRF_EMMCPHY_CON0 0x0
>> +#define GRF_EMMCPHY_CON1 0x4
>> +#define GRF_EMMCPHY_CON2 0x8
>> +#define GRF_EMMCPHY_CON3 0xc
>> +#define GRF_EMMCPHY_CON4 0x10
>> +#define GRF_EMMCPHY_CON5 0x14
>> +#define GRF_EMMCPHY_CON6 0x18
>> +#define GRF_EMMCPHY_STATUS 0x20
>> +
>> +#define PHYCTRL_PDB_MASK 0x1
>> +#define PHYCTRL_PDB_SHIFT 0x0
>> +#define PHYCTRL_PDB_PWR_ON 0x1
>> +#define PHYCTRL_PDB_PWR_OFF 0x0
>> +#define PHYCTRL_ENDLL_MASK 0x1
>> +#define PHYCTRL_ENDLL_SHIFT 0x1
>> +#define PHYCTRL_ENDLL_ENABLE 0x1
>> +#define PHYCTRL_ENDLL_DISABLE 0x0
>> +#define PHYCTRL_CALDONE_MASK 0x1
>> +#define PHYCTRL_CALDONE_SHIFT 0x6
>> +#define PHYCTRL_CALDONE_DONE 0x1
>> +#define PHYCTRL_CALDONE_GOING 0x0
>> +#define PHYCTRL_DLLRDY_MASK 0x1
>> +#define PHYCTRL_DLLRDY_SHIFT 0x5
>> +#define PHYCTRL_DLLRDY_DONE 0x1
>> +#define PHYCTRL_DLLRDY_GOING 0x0
>> +
>> +struct rockchip_emmc_phy {
>> + unsigned int reg_offset;
>> + struct regmap *reg_base;
>> +};
>> +
>> +static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
>> + bool on_off)
>> +{
>> + unsigned int caldone;
>> + unsigned int dllrdy;
>> +
>> + /*
>> + * Keep phyctrl_pdb and phyctrl_endll low to allow
>> + * initialization of CALIO state M/C DFFs
>> + */
>> + regmap_write(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
>> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
>> + PHYCTRL_PDB_MASK,
>> + PHYCTRL_PDB_SHIFT));
>> + regmap_write(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
>> + HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
>> + PHYCTRL_ENDLL_MASK,
>> + PHYCTRL_ENDLL_SHIFT));
>> +
>> + /* Already finish power_off above */
>> + if (on_off == PHYCTRL_PDB_PWR_OFF)
>> + return 0;
>> +
>> + /*
>> + * According to the user manual, calpad calibration
>> + * cycle takes more than 2us without the minimal recommended
>> + * value, so we may need a little margin here
>> + */
>> + udelay(3);
>> + regmap_write(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
>> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
>> + PHYCTRL_PDB_MASK,
>> + PHYCTRL_PDB_SHIFT));
>> +
>> + /*
>> + * According to the user manual, it asks driver to
>> + * wait 5us for calpad busy trimming
>> + */
>> + udelay(5);
>> + regmap_read(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
>> + &caldone);
>> + caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
>> + if (caldone != PHYCTRL_CALDONE_DONE) {
>> + pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + /*
>> + * Enable analog DLL circuits, and we need extra 10.2us
>> + * for dll to be ready for work.
>> + */
>> + regmap_write(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
>> + HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
>> + PHYCTRL_ENDLL_MASK,
>> + PHYCTRL_ENDLL_SHIFT));
>> + udelay(11);
>> + regmap_read(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
>> + &dllrdy);
>> + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
>> + if (dllrdy != PHYCTRL_DLLRDY_DONE) {
>> + pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_emmc_phy_power_off(struct phy *phy)
>> +{
>> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
>> + int ret = 0;
>> +
>> + /* Power down emmc phy analog blocks */
>> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_emmc_phy_power_on(struct phy *phy)
>> +{
>> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
>> + int ret = 0;
>> +
>> + /* Power up emmc phy analog blocks */
>> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_emmc_phy_init(struct phy *phy)
>> +{
>> + return 0;
>> +}
>> +
>> +static int rockchip_emmc_phy_exit(struct phy *phy)
>> +{
>> + return 0;
>> +}
>> +
>> +static const struct phy_ops ops = {
>> + .init = rockchip_emmc_phy_init,
>> + .exit = rockchip_emmc_phy_exit,
>> + .power_on = rockchip_emmc_phy_power_on,
>> + .power_off = rockchip_emmc_phy_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_emmc_phy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct rockchip_emmc_phy *rk_phy;
>> + struct phy *generic_phy;
>> + struct phy_provider *phy_provider;
>> + struct regmap *grf;
>> + unsigned int reg_offset;
>> +
>> + grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
>> + if (IS_ERR(grf)) {
>> + dev_err(dev, "Missing rockchip,grf property\n");
>> + return PTR_ERR(grf);
>> + }
>> +
>> + rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
>> + if (!rk_phy)
>> + return -ENOMEM;
>> +
>> + if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
>> + dev_err(dev, "missing reg property in node %s\n",
>> + dev->of_node->name);
>> + return -EINVAL;
>> + }
>> +
>> + rk_phy->reg_offset = reg_offset;
>> + rk_phy->reg_base = grf;
>> +
>> + generic_phy = devm_phy_create(dev, dev->of_node, &ops);
>> + if (IS_ERR(generic_phy)) {
>> + dev_err(dev, "failed to create PHY\n");
>> + return PTR_ERR(generic_phy);
>> + }
>> +
>> + phy_set_drvdata(generic_phy, rk_phy);
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
>> + { .compatible = "rockchip,rk3399-emmc-phy" },
>> + {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_emmc_driver = {
>> + .probe = rockchip_emmc_phy_probe,
>> + .driver = {
>> + .name = "rockchip-emmc-phy",
>> + .of_match_table = rockchip_emmc_phy_dt_ids,
>> + },
>> +};
>> +
>> +module_platform_driver(rockchip_emmc_driver);
>> +
>> +MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal eMMC PHY
2016-01-05 1:08 ` [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal " Shawn Lin
2016-01-25 7:49 ` Shawn Lin
@ 2016-02-03 6:39 ` Kishon Vijay Abraham I
2016-02-03 7:24 ` Shawn Lin
1 sibling, 1 reply; 6+ messages in thread
From: Kishon Vijay Abraham I @ 2016-02-03 6:39 UTC (permalink / raw)
To: Shawn Lin; +Cc: linux-kernel, linux-rockchip
Hi,
On Tuesday 05 January 2016 06:38 AM, Shawn Lin wrote:
> This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
> Access the PHY via registers provided by GRF (general register
> files) module.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
>
> Changes in v2:
> - remove phy from rockchip_emmc_phy
> - remove state from rockchip_emmc_phy
> - remove on/off from init/exit
>
> drivers/phy/Kconfig | 7 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-emmc.c | 241 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 249 insertions(+)
> create mode 100644 drivers/phy/phy-rockchip-emmc.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 03cb3ea..47d16e3 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -320,6 +320,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_EMMC
> + tristate "Rockchip EMMC PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip EMMC PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 075db1a..ed8f175 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
> new file mode 100644
> index 0000000..6a157c2
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-emmc.c
> @@ -0,0 +1,241 @@
> +/*
> + * Rockchip emmc PHY driver
> + *
> + * Copyright (C) 2015 Shawn Lin <shawn.lin@rock-chips.com>
> + * Copyright (C) 2015 ROCKCHIP, Inc.
2016?
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +/*
> + * The higher 16-bit of this register is used for write protection
> + * only if BIT(x + 16) set to 1 the BIT(x) can be written.
> + */
> +#define HIWORD_UPDATE(val, mask, shift) \
> + ((val) << (shift) | (mask) << ((shift) + 16))
> +
> +/* Register definition */
> +#define GRF_EMMCPHY_CON0 0x0
> +#define GRF_EMMCPHY_CON1 0x4
> +#define GRF_EMMCPHY_CON2 0x8
> +#define GRF_EMMCPHY_CON3 0xc
> +#define GRF_EMMCPHY_CON4 0x10
> +#define GRF_EMMCPHY_CON5 0x14
> +#define GRF_EMMCPHY_CON6 0x18
> +#define GRF_EMMCPHY_STATUS 0x20
> +
> +#define PHYCTRL_PDB_MASK 0x1
> +#define PHYCTRL_PDB_SHIFT 0x0
> +#define PHYCTRL_PDB_PWR_ON 0x1
> +#define PHYCTRL_PDB_PWR_OFF 0x0
> +#define PHYCTRL_ENDLL_MASK 0x1
> +#define PHYCTRL_ENDLL_SHIFT 0x1
> +#define PHYCTRL_ENDLL_ENABLE 0x1
> +#define PHYCTRL_ENDLL_DISABLE 0x0
> +#define PHYCTRL_CALDONE_MASK 0x1
> +#define PHYCTRL_CALDONE_SHIFT 0x6
> +#define PHYCTRL_CALDONE_DONE 0x1
> +#define PHYCTRL_CALDONE_GOING 0x0
> +#define PHYCTRL_DLLRDY_MASK 0x1
> +#define PHYCTRL_DLLRDY_SHIFT 0x5
> +#define PHYCTRL_DLLRDY_DONE 0x1
> +#define PHYCTRL_DLLRDY_GOING 0x0
> +
> +struct rockchip_emmc_phy {
> + unsigned int reg_offset;
> + struct regmap *reg_base;
> +};
> +
> +static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
> + bool on_off)
> +{
> + unsigned int caldone;
> + unsigned int dllrdy;
> +
> + /*
> + * Keep phyctrl_pdb and phyctrl_endll low to allow
> + * initialization of CALIO state M/C DFFs
> + */
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
> + PHYCTRL_PDB_MASK,
> + PHYCTRL_PDB_SHIFT));
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
> + PHYCTRL_ENDLL_MASK,
> + PHYCTRL_ENDLL_SHIFT));
> +
> + /* Already finish power_off above */
> + if (on_off == PHYCTRL_PDB_PWR_OFF)
> + return 0;
> +
> + /*
> + * According to the user manual, calpad calibration
> + * cycle takes more than 2us without the minimal recommended
> + * value, so we may need a little margin here
> + */
> + udelay(3);
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
> + PHYCTRL_PDB_MASK,
> + PHYCTRL_PDB_SHIFT));
> +
> + /*
> + * According to the user manual, it asks driver to
> + * wait 5us for calpad busy trimming
> + */
> + udelay(5);
> + regmap_read(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
> + &caldone);
> + caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
> + if (caldone != PHYCTRL_CALDONE_DONE) {
> + pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
> + return -ETIMEDOUT;
> + }
> +
> + /*
> + * Enable analog DLL circuits, and we need extra 10.2us
> + * for dll to be ready for work.
> + */
> + regmap_write(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
> + HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
> + PHYCTRL_ENDLL_MASK,
> + PHYCTRL_ENDLL_SHIFT));
> + udelay(11);
add a comment for this delay too.
> + regmap_read(rk_phy->reg_base,
> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
> + &dllrdy);
> + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
> + if (dllrdy != PHYCTRL_DLLRDY_DONE) {
> + pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_power_off(struct phy *phy)
> +{
> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + /* Power down emmc phy analog blocks */
> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_power_on(struct phy *phy)
> +{
> + struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + /* Power up emmc phy analog blocks */
> + ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_init(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static int rockchip_emmc_phy_exit(struct phy *phy)
> +{
> + return 0;
> +}
empty init/exit functions are not required.
Thanks
Kishon
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal eMMC PHY
2016-02-03 6:39 ` Kishon Vijay Abraham I
@ 2016-02-03 7:24 ` Shawn Lin
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Lin @ 2016-02-03 7:24 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: shawn.lin, linux-kernel, linux-rockchip
Hi Kishon,
On 2016/2/3 14:39, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 05 January 2016 06:38 AM, Shawn Lin wrote:
>> This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
>> Access the PHY via registers provided by GRF (general register
[...]
>> + *
>> + * Copyright (C) 2015 Shawn Lin <shawn.lin@rock-chips.com>
>> + * Copyright (C) 2015 ROCKCHIP, Inc.
>
> 2016?
:) I will update it.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
[...]
>> + }
>> +
>> + /*
>> + * Enable analog DLL circuits, and we need extra 10.2us
>> + * for dll to be ready for work.
>> + */
>> + regmap_write(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_CON6,
>> + HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
>> + PHYCTRL_ENDLL_MASK,
>> + PHYCTRL_ENDLL_SHIFT));
>> + udelay(11);
>
> add a comment for this delay too.
Got it.
>> + regmap_read(rk_phy->reg_base,
>> + rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
>> + &dllrdy);
>> + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
>> + if (dllrdy != PHYCTRL_DLLRDY_DONE) {
>> + pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + return 0;
>> +}
>> +
[...]
>> +static int rockchip_emmc_phy_init(struct phy *phy)
>> +{
>> + return 0;
>> +}
>> +
>> +static int rockchip_emmc_phy_exit(struct phy *phy)
>> +{
>> + return 0;
>> +}
>
> empty init/exit functions are not required.
>
yep.
> Thanks
> Kishon
>
>
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-02-03 7:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-05 1:07 [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip eMMC PHY Shawn Lin
2016-01-05 1:08 ` [PATCH v2 2/2] phy: add a driver for the Rockchip SoC internal " Shawn Lin
2016-01-25 7:49 ` Shawn Lin
2016-02-01 6:03 ` Kishon Vijay Abraham I
2016-02-03 6:39 ` Kishon Vijay Abraham I
2016-02-03 7:24 ` Shawn Lin
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