[PATCH v3 0/9] Add the family patches to support for kylin board

[PATCH v3 0/9] Add the family patches to support for kylin board

[Caesar Wang]

Hi all,

This series patches are based on kernel 4.4.0 release version
(Linux version 4.4.0+ (wxt@ubuntu) (...) #167 SMP Fri Jan 15 19:18:28 CST 2016)

This series pacthes are verified on the following github:
https://github.com/Caesar-github/rockchip/commits/kylin-next

This series has 9 patches: (9--->1)
2b1afd6 ARM: dts: rockchip: add pl330-broken-no-flushp quirk for rk3036 SoCs
cc706ee ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs
cdad8f3 ARM: dts: rockchip: add the sdmmc for kylin board
9ece822 ARM: dts: rockchip: add the sdio power sequence for kylin board
28eba08 ARM: dts: rockchip: enable the high speed on sdio for kylin board
858e2cc ARM: dts: rockchip: enable the uart0 for kylin board
59aecc9 ASoC: rockchip: i2s: add support for grabbing output clock to codec
d2b5890 ARM: dts: rockchip: add i2s_clk_out to list of clocks used on rk3036 i2s
98c9c09 ARM: dts: rockchip: add hdmi/vop device node for rk3036
..

This series patches can apply into Heiko v4.6-armsoc/dts32 branch.
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.6-armsoc/dts32
---

This series patches have the following decriptions:

PATCH[1/9]: ====> add hdmi/vop display node for rk3036
ARM: dts: rockchip: add hdmi/vop device node for rk3036

I fetch some vop and drm/rockchip patches from the Mark Yao branch.
https://github.com/markyzq/kernel-drm-rockchip/commits/drm-rockchip-next-2015-12-28

Add the following patches, verified on my github.
(https://github.com/Caesar-github/rockchip/commits/kylin-next)

....
cf2631b FORMLIST: clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_bus
a80ae4e FORMLIST: dt-bindings: add document for Innosilicon HDMI on Rockchip platform
b460291 FORMLIST: drm: rockchip/hdmi: add Innosilicon HDMI support
fe52935 FORMLIST: dt-bindings: add document for rk3036-vop
b556daa FORMLIST: drm/rockchip: vop: add rk3036 vop support
447e2b8 drm/rockchip: vop: spilt scale regsters
4ec4740 drm/rockchip: vop: spilt register related into rockchip_reg_vop.c
da528d7 drm/rockchip: vop: move interrupt registers into vop_data
a207639 drm/rockchip: vop: merge vop cfg_done into vop_data
1656da5 drm/rockchip: dw_hdmi: use encoder enable function
2b5f45b drm/rockchip: direct config connecter gate and out_mode
dcf2718 drm/rockchip: support atomic asynchronous commit
722dd38 drm/rockchip: Optimization vop mode set
f1b407a drm/rockchip: Convert to support atomic API
6ec2936 drm/rockchip: vop: replace dpms with enable/disable
5cfe7d1 drm/rockchip: Use new vblank api drm_crtc_vblank_*
ff1b1a3 UPSTREAM: drm: use dev_name as default unique name in drm_dev_alloc()
2155d11 drm: make drm_dev_set_unique() not use a format string
649f441 drm/rockchip: Constify function pointer structs
5096c80 UPSTREAM: drm: Pass 'name' to drm_encoder_init()
26c4d13 UPSTREAM: drm: Pass 'name' to drm_universal_plane_init()
0b795a0 UPSTREAM: drm: Pass 'name' to drm_crtc_init_with_planes()
...
----

PATCH[2/9-3/9]:====> Add the i2c clock output for rk3036

59aecc9 ASoC: rockchip: i2s: add support for grabbing output clock to codec
d2b5890 ARM: dts: rockchip: add i2s_clk_out to list of clocks used on rk3036 i2s

This patches is working for codec rt5616 on kylin board. (RK3036 SoCs)

That's needed the following rt5616 driver from Mark Brown Branch.
(cherry picked from git.kernel.org broonie/sound.git for-next)

cf94b7a UPSTREAM: ASoC: rt5616: rename some alsa control names
86f561d UPSTREAM: ASoC: rt5616: add devicetree document for rt5616
0e0f5f8 UPSTREAM: ASoC: rt5616: add an of_match table
263a330 UPSTREAM: ASoC: rt5616: Return error if device ID mismatch
0094139 UPSTREAM: ASoC: rt5616: add rt5616 codec driver

Notes:
I'm run it with the ubuntu 15.04 to set the configure.
./amixer "HP Playback Switch" 1
./amixer "HP Playback Volume" 20
./amixer "HPO MIX DAC1 Switch" 1
./amixer "OUT MIXR DAC R1 Switch" 1
./amixer "OUT MIXL DAC L1 Switch" 1
./amixer "Stereo DAC MIXR DAC R1 Switch" 1
./amixer "Stereo DAC MIXL DAC L1 Switch" 1

root@linaro-alip:/media/aplay# ./aplay pcm.wav
Playing sample: 2 ch, 48000 hz, 16 bit
..
That can be normal playing the music.
----

PATCH[4/9-6/9]: ====> Support wifi/bt module for kylin board
858e2cc ARM: dts: rockchip: enable the uart0 for kylin board
28eba08 ARM: dts: rockchip: enable the high speed on sdio for kylin board
9ece822 ARM: dts: rockchip: add the sdio power sequence for kylin board

The wifi/bt driver hasn't land in mainline, the driver is in here:
https://github.com/Caesar-github/rockchip/commit/76d91ce5ac2bff226f77b000e8a736bcd72b034f

/* create wpa_supplicant in /etc/wifi */
ctrl_interface=/var/run/wpa_supplicant
update_config=1

wpa_supplicant -Dnl80211 -c /etc/wifi/wpa_supplicant.conf -i wlan0 -B
wpa_cli add_network
wpa_cli set_network 1 ssid \"wxt\"
wpa_cli set_network 1 psk \"123456789\"
wpa_cli select_network 1
wpa_cli save_config

ifconfig wlan0 192.168.1.105
route add default gw 192.168.1.1

root@linaro-alip:/# ping 192.168.1.1
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=6.83 ms
64 bytes from 192.168.1.1: icmp_seq=2 ttl=64 time=184 ms
64 bytes from 192.168.1.1: icmp_seq=3 ttl=64 time=9.21 ms
64 bytes from 192.168.1.1: icmp_seq=4 ttl=64 time=6.84 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=64 time=11.2 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=64 time=9.24 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=64 time=12.9 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=64 time=7.02 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=64 time=24.3 ms
64 bytes from 192.168.1.1: icmp_seq=10 ttl=64 time=13.6 ms
64 bytes from 192.168.1.1: icmp_seq=11 ttl=64 time=3.87 m
...

The wifi throughput:

iperf -s -i 1
...
[  4] 116.0-117.0 sec  2.88 MBytes  24.1 Mbits/sec
[  4] 117.0-118.0 sec  2.99 MBytes  25.0 Mbits/sec
[  4] 118.0-119.0 sec  3.01 MBytes  25.2 Mbits/sec
[  4] 119.0-120.0 sec  2.89 MBytes  24.2 Mbits/sec
[  4]  0.0-120.4 sec   332 MBytes  23.1 Mbits/sec
----

PATCH[7/9]: ====> sdmmc patch for kylin board
ARM: dts: rockchip: add the sdmmc for kylin board

You should mark it "okay" if you want to use the sdmmc.
This patch default is disabing the sdmmc since the sdmmc and
uart2(debug port) is reusing pin.
----

PATCH[8/9]: ====> reboot mode support
ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs

This patch is depend on Andy's patches on
http://www.spinics.net/lists/kernel/msg2160362.html

----

PATCH[9/9]:====> DMA Patchs
ARM: dts: rockchip: add pl330-broken-no-flushp quirk for rk3036 SoCs

In order to be better read/write for emmc.
This patch is based on the following:(Fix broken DMAFLUSHP on Rockchips platform)

3055695 FROMLIST: DMA: dmaengine: expose max burst capability to clientmZ
(am from https://patchwork.kernel.org/patch/7399361/)
ed56bee FROMLIST: DMA: pl330: add quirk for broken no flushp
(am from https://patchwork.kernel.org/patch/7399371/)
0c43bc3 FROMLIST: Documentation: arm-pl330: add description of arm, pl330-broken-no-flushp
(am from https://patchwork.kernel.org/patch/7399371/)
623a699 FROMLIST: DMA: pl330: support burst mode for dev-to-mem and mem-to-dev transmit
(am from https://patchwork.kernel.org/patch/7399381/)
----


Changes in v3:
- As the perious discuss on https://patchwork.kernel.org/patch/5427131/,
  I think Mark likes do it in codec driver, I have to say I agree this
  patch in here since that's the i2s block output. I don't know if the
  Mark has changed his mind.
- Add the suspend/resume handle the clock.
- As Javier/Heiko discuss on https://patchwork.kernel.org/patch/7974311/,
  try to change dts with reset-gpios handle.
- fix the commit content in sdmmc patch.
- fix the commit content in pl330* quirk patch.

Caesar Wang (8):
  ARM: dts: rockchip: add hdmi/vop device node for rk3036
  ARM: dts: rockchip: add i2s_clk_out to list of clocks used on rk3036
    i2s
  ARM: dts: rockchip: enable the uart0 for kylin board
  ARM: dts: rockchip: enable the high speed on sdio for kylin board
  ARM: dts: rockchip: add the sdio power sequence for kylin board
  ARM: dts: rockchip: add the sdmmc for kylin board
  ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs
  ARM: dts: rockchip: add pl330-broken-no-flushp quirk for rk3036 SoCs

Sonny Rao (1):
  ASoC: rockchip: i2s: add support for grabbing output clock to codec

 arch/arm/boot/dts/rk3036-kylin.dts | 62 ++++++++++++++++++++++++
 arch/arm/boot/dts/rk3036.dtsi      | 99 ++++++++++++++++++++++++++++++++++++--
 sound/soc/rockchip/rockchip_i2s.c  | 24 +++++++++
 3 files changed, 182 insertions(+), 3 deletions(-)

-- 
1.9.1

[PATCH v3 1/9] ARM: dts: rockchip: add hdmi/vop device node for rk3036

[Caesar Wang]

This patch adds the needed display info for rk3036 SOCs.

The rk3036 support two overlay plane and one hwc plane,
it support IOMMU, and its IOMMU same as rk3288's.
Meanwhile, add the inno hdmi for HDMI display.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None

 arch/arm/boot/dts/rk3036-kylin.dts | 12 +++++++
 arch/arm/boot/dts/rk3036.dtsi      | 66 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index b287625..30a9aca 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -88,6 +88,10 @@
 	status = "okay";
 };
 
+&hdmi {
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 
@@ -320,6 +324,14 @@
 	status = "okay";
 };
 
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
 &pinctrl {
 	pmic {
 		pmic_int: pmic-int {
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ee457a2..0b128be 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -147,6 +147,42 @@
 		};
 	};
 
+	vop: vop@10118000 {
+		compatible = "rockchip,rk3036-vop";
+		reg = <0x10118000 0x19c>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vop_mmu>;
+
+		status = "disabled";
+
+		vop_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vop_out_hdmi: endpoint@0 {
+				reg = <1>;
+				remote-endpoint = <&hdmi_in_vop>;
+			};
+		};
+	};
+
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
+	vop_mmu: iommu@10118300 {
+		compatible = "rockchip,iommu";
+		reg = <0x10118300 0x100>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vop_mmu";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@10139000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
@@ -274,6 +310,27 @@
 		status = "disabled";
 	};
 
+	hdmi: hdmi@20034000 {
+		compatible = "rockchip,rk3036-inno-hdmi";
+		reg = <0x20034000 0x4000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru  PCLK_HDMI>;
+		clock-names = "pclk";
+		rockchip,grf = <&grf>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_ctl>;
+		status = "disabled";
+
+		hdmi_in: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			hdmi_in_vop: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&vop_out_hdmi>;
+			};
+		};
+	};
+
 	timer: timer@20044000 {
 		compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 		reg = <0x20044000 0x20>;
@@ -588,6 +645,15 @@
 			};
 		};
 
+		hdmi {
+			hdmi_ctl: hdmi-ctl {
+				rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
+						<1 9  RK_FUNC_1 &pcfg_pull_none>,
+						<1 10 RK_FUNC_1 &pcfg_pull_none>,
+						<1 11 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		uart0 {
 			uart0_xfer: uart0-xfer {
 				rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
-- 
1.9.1

[PATCH v3 2/9] ARM: dts: rockchip: add i2s_clk_out to list of clocks used on rk3036 i2s

[Caesar Wang]

The I2S block that it needs to claim that output clock. This also
adds properties to model the relationship between the output clock and
the i2s clock itself, to ensure that the clock muxing is set correctly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None

 arch/arm/boot/dts/rk3036.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 0b128be..cf0968c 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -277,8 +277,8 @@
 		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clock-names = "i2s_clk", "i2s_hclk";
-		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
+		clock-names = "i2s_clk", "i2s_hclk", "i2s_clk_out";
+		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>, <&cru SCLK_I2S_OUT>;
 		dmas = <&pdma 0>, <&pdma 1>;
 		dma-names = "tx", "rx";
 		pinctrl-names = "default";
-- 
1.9.1

[PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Caesar Wang]

From: Sonny Rao <sonnyrao@chromium.org>

We need to claim the clock which is driving the codec so that when we
enable clock gating, we continue to clock the codec when needed.
I make this an optional clock since there might be some applications
where we don't need it but can still use the I2S block.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v3:
- As the perious discuss on https://patchwork.kernel.org/patch/5427131/,
  I think Mark likes do it in codec driver, I have to say I agree this
  patch in here since that's the i2s block output. I don't know if the
  Mark has changed his mind.
- Add the suspend/resume handle the clock.

 sound/soc/rockchip/rockchip_i2s.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index 58ee645..5889bba 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -28,6 +28,7 @@ struct rk_i2s_dev {
 
 	struct clk *hclk;
 	struct clk *mclk;
+	struct clk *oclk;
 
 	struct snd_dmaengine_dai_dma_data capture_dma_data;
 	struct snd_dmaengine_dai_dma_data playback_dma_data;
@@ -47,6 +48,9 @@ static int i2s_runtime_suspend(struct device *dev)
 {
 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 
+	if (i2s->oclk)
+		clk_disable_unprepare(i2s->oclk);
+
 	clk_disable_unprepare(i2s->mclk);
 
 	return 0;
@@ -63,6 +67,14 @@ static int i2s_runtime_resume(struct device *dev)
 		return ret;
 	}
 
+	if (i2s->oclk) {
+		ret = clk_prepare_enable(i2s->oclk);
+		if (ret) {
+			dev_err(i2s->dev, "oclk enable failed %d\n", ret);
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
@@ -480,6 +492,15 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
 		return PTR_ERR(i2s->mclk);
 	}
 
+	i2s->oclk = devm_clk_get(&pdev->dev, "i2s_clk_out");
+	if (IS_ERR(i2s->oclk)) {
+		dev_dbg(&pdev->dev, "Didn't find output clock\n");
+		i2s->oclk = NULL;
+	}
+
+	if (i2s->oclk)
+		ret = clk_prepare_enable(i2s->oclk);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(regs))
@@ -552,6 +573,9 @@ static int rockchip_i2s_remove(struct platform_device *pdev)
 	if (!pm_runtime_status_suspended(&pdev->dev))
 		i2s_runtime_suspend(&pdev->dev);
 
+	if (i2s->oclk)
+		clk_disable_unprepare(i2s->oclk);
+
 	clk_disable_unprepare(i2s->mclk);
 	clk_disable_unprepare(i2s->hclk);
 
-- 
1.9.1

[PATCH v3 4/9] ARM: dts: rockchip: enable the uart0 for kylin board

[Caesar Wang]

This patch is enabling the uart0 for bluetooth module.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None

 arch/arm/boot/dts/rk3036-kylin.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 30a9aca..2a45be7 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -316,6 +316,10 @@
 	status = "okay";
 };
 
+&uart0 {
+	status = "okay";
+};
+
 &usb_host {
 	status = "okay";
 };
-- 
1.9.1

[PATCH v3 5/9] ARM: dts: rockchip: enable the high speed on sdio for kylin board

[Caesar Wang]

We want to the higher speed for wifi module working.

Bootup kernel log:
...
mmc_host mmc0: Bus speed (slot 0) = 37125000Hz (slot req 37500000Hz,
actual 37125000HZ div = 0)

or run 'cat /sys/kernel/debug/clk/clk_summary |grep phase -C 1' to check
Otherwise, the mmc0 will run 400khz defalult value to work.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None

 arch/arm/boot/dts/rk3036-kylin.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 2a45be7..4fbd0a3 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -303,6 +303,11 @@
 
 	broken-cd;
 	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
 	cap-sdio-irq;
 	default-sample-phase = <90>;
 	keep-power-in-suspend;
-- 
1.9.1

[PATCH v3 6/9] ARM: dts: rockchip: add the sdio power sequence for kylin board

[Caesar Wang]

This patch adds the sdio power sequence for kylin board.
The WLAN attached to a SDIO interface, wifi/bluetooth have
reset and power been needed to enable.

AFAIK, the simple power sequence provider sets a value for multiple GPIOs.
So the reset and power of WlAN chip can be handled in mmc power sequence.
On the module itself this is one of these, that should can be handled
by reset GPIOs in simple mmc power sequence.

The Bluetooth host wake is high active from bootup, this patch is also
set pinctrl bias as the default to enable the pull up in soc internal.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v3:
- As Javier/Heiko discuss on https://patchwork.kernel.org/patch/7974311/,
  try to change dts with reset-gpios handle.

 arch/arm/boot/dts/rk3036-kylin.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 4fbd0a3..d30a6dd 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -78,6 +78,23 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_wake_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - SDIO_RESET_L_WL_RST
+		 * - SDIO_RESET_L_BT_EN
+		 */
+		reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
+			      <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */
+			      <&gpio2 9  GPIO_ACTIVE_LOW>; /* BT_EN */
+	};
 };
 
 &acodec {
@@ -311,6 +328,7 @@
 	cap-sdio-irq;
 	default-sample-phase = <90>;
 	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
 	non-removable;
 	num-slots = <1>;
 	pinctrl-names = "default";
@@ -348,6 +366,12 @@
 		};
 	};
 
+	sdio {
+		bt_wake_h: bt-wake-h {
+			rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>;
+		};
+	};
+
 	sleep {
 		global_pwroff: global-pwroff {
 			rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
-- 
1.9.1

[PATCH v3 7/9] ARM: dts: rockchip: add the sdmmc for kylin board

[Caesar Wang]

Although We can add the sdmmc node, shouldn't enable it.
Since the sdmmc is reusing the same pin with uart2.
Unfortunately, the uart2 is used by the debug port, so that will cause
the debug information can't display on console if enabling the sdmmc.

As we have supported the sdmmc (sd card) on hardware for kylin board.
So, maybe we can have the sdmmc node in kylin dts, not to enable it.

Anyway, you only need add the okay status if someone want to enable the
sdmmc.

e.g.
if you use the adb to debug with android os.
You can add the
status = "okay" to enable the sdmmc for sd card working.
The defauly status is disabling it.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v3:
- fix the commit content in sdmmc patch.

 arch/arm/boot/dts/rk3036-kylin.dts | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index d30a6dd..8bdbb95 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -335,6 +335,17 @@
 	pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
 };
 
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+};
+
 &uart2 {
 	status = "okay";
 };
@@ -372,6 +383,12 @@
 		};
 	};
 
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sleep {
 		global_pwroff: global-pwroff {
 			rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
-- 
1.9.1

[PATCH v3 8/9] ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs

[Caesar Wang]

Add reboot mode driver DT node for rk3036 platform.
This patch adds the needed reboot mode node for rk3036.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None

 arch/arm/boot/dts/rk3036.dtsi | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index cf0968c..f5ecfff 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -43,6 +43,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3036-cru.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
 #include "skeleton.dtsi"
 
 / {
@@ -297,8 +298,33 @@
 	};
 
 	grf: syscon@20008000 {
-		compatible = "rockchip,rk3036-grf", "syscon";
+		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 		reg = <0x20008000 0x1000>;
+
+		reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x1d8>;
+
+			normal {
+				linux,mode = "normal";
+				loader,magic = <BOOT_NORMAL>;
+			};
+
+			loader {
+				linux,mode = "loader";
+				loader,magic = <BOOT_LOADER>;
+			};
+
+			recovery {
+				linux,mode = "recovery";
+				loader,magic = <BOOT_RECOVERY>;
+			};
+
+			fastboot {
+				linux,mode = "fastboot";
+				loader,magic = <BOOT_FASTBOOT>;
+			};
+		};
 	};
 
 	acodec: acodec-ana@20030000 {
-- 
1.9.1

[PATCH v3 9/9] ARM: dts: rockchip: add pl330-broken-no-flushp quirk for rk3036 SoCs

[Caesar Wang]

Pl330 integrated in rk3036 platform that doesn't support
DMAFLUSHP function. So we add 'arm,pl330-broken-no-flushp' quirk
for rk3036.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v3:
- fix the commit content in pl330* quirk patch.

 arch/arm/boot/dts/rk3036.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index f5ecfff..c029f6f 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -103,6 +103,7 @@
 		pdma: pdma@20078000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x20078000 0x4000>;
+			arm,pl330-broken-no-flushp;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
-- 
1.9.1

Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Mark Brown]

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On Fri, Jan 15, 2016 at 09:49:50PM +0800, Caesar Wang wrote:

> We need to claim the clock which is driving the codec so that when we
> enable clock gating, we continue to clock the codec when needed.
> I make this an optional clock since there might be some applications
> where we don't need it but can still use the I2S block.

> - As the perious discuss on https://patchwork.kernel.org/patch/5427131/,
>   I think Mark likes do it in codec driver, I have to say I agree this
>   patch in here since that's the i2s block output. I don't know if the
>   Mark has changed his mind.

If the I2S block is providing a clock to the CODEC then that's what the
software should do so that the CODEC can gate and ungate the clock as
required.  This patch has the I2S block using a clock, not providing
one.

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Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Sonny Rao]

On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown <broonie@kernel.org> wrote:
> On Fri, Jan 15, 2016 at 09:49:50PM +0800, Caesar Wang wrote:
>
>> We need to claim the clock which is driving the codec so that when we
>> enable clock gating, we continue to clock the codec when needed.
>> I make this an optional clock since there might be some applications
>> where we don't need it but can still use the I2S block.
>
>> - As the perious discuss on https://patchwork.kernel.org/patch/5427131/,
>>   I think Mark likes do it in codec driver, I have to say I agree this
>>   patch in here since that's the i2s block output. I don't know if the
>>   Mark has changed his mind.
>
> If the I2S block is providing a clock to the CODEC then that's what the
> software should do so that the CODEC can gate and ungate the clock as
> required.  This patch has the I2S block using a clock, not providing
> one.

>From my read of the clock diagram for RK3288  there is a single clock
signal (labeled "clk_i2s0") that comes out of a fractional divider,
and it is split such that one path gets sent to the I2S block and the
second path is sent to a mux after which that signal is sent to an
external pin that goes to the codec.

There are separate clock gates for the two paths: one for the I2S
block and one after that mux before the external pin.

I'm not sure if it's being modeled that way in the Linux code or not,
but at least physically I don't think this clock signal actually goes
through the I2S block before being sent to the codec.

Does that help clarify?

Re: [PATCH v3 8/9] ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs

[Heiko Stuebner]

Hi Caesar, Andy,

Am Freitag, 15. Januar 2016, 21:49:55 schrieb Caesar Wang:
> Add reboot mode driver DT node for rk3036 platform.
> This patch adds the needed reboot mode node for rk3036.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

this obviously depends on Andy's reboot series.

Andy, could you include this patch into further submissions of your series 
please? That way it won't keep floating unconnected on the lists :-)


Thanks
Heiko

> ---
> 
> Changes in v3: None
> 
>  arch/arm/boot/dts/rk3036.dtsi | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
> index cf0968c..f5ecfff 100644
> --- a/arch/arm/boot/dts/rk3036.dtsi
> +++ b/arch/arm/boot/dts/rk3036.dtsi
> @@ -43,6 +43,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/pinctrl/rockchip.h>
>  #include <dt-bindings/clock/rk3036-cru.h>
> +#include <dt-bindings/soc/rockchip_boot-mode.h>
>  #include "skeleton.dtsi"
> 
>  / {
> @@ -297,8 +298,33 @@
>  	};
> 
>  	grf: syscon@20008000 {
> -		compatible = "rockchip,rk3036-grf", "syscon";
> +		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
>  		reg = <0x20008000 0x1000>;
> +
> +		reboot-mode {
> +			compatible = "syscon-reboot-mode";
> +			offset = <0x1d8>;
> +
> +			normal {
> +				linux,mode = "normal";
> +				loader,magic = <BOOT_NORMAL>;
> +			};
> +
> +			loader {
> +				linux,mode = "loader";
> +				loader,magic = <BOOT_LOADER>;
> +			};
> +
> +			recovery {
> +				linux,mode = "recovery";
> +				loader,magic = <BOOT_RECOVERY>;
> +			};
> +
> +			fastboot {
> +				linux,mode = "fastboot";
> +				loader,magic = <BOOT_FASTBOOT>;
> +			};
> +		};
>  	};
> 
>  	acodec: acodec-ana@20030000 {

Re: [PATCH v3 9/9] ARM: dts: rockchip: add pl330-broken-no-flushp quirk for rk3036 SoCs

[Heiko Stuebner]

Hi Caesar,

Am Freitag, 15. Januar 2016, 21:49:56 schrieb Caesar Wang:
> Pl330 integrated in rk3036 platform that doesn't support
> DMAFLUSHP function. So we add 'arm,pl330-broken-no-flushp' quirk
> for rk3036.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

can you try to find out if Shawn plans on respinning his work on the pl330 
quirk that is needed for this. His last submission seems to be from october.


Thanks
Heiko

Re: [PATCH v3 4/9] ARM: dts: rockchip: enable the uart0 for kylin board

[Heiko Stuebner]

Am Freitag, 15. Januar 2016, 21:49:51 schrieb Caesar Wang:
> This patch is enabling the uart0 for bluetooth module.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

applied to my dts32 branch for 4.6,

after moving your uart0 node _above_ the already existing uart2 node.


Heiko

Re: [PATCH v3 5/9] ARM: dts: rockchip: enable the high speed on sdio for kylin board

[Heiko Stuebner]

Am Freitag, 15. Januar 2016, 21:49:52 schrieb Caesar Wang:
> We want to the higher speed for wifi module working.
> 
> Bootup kernel log:
> ...
> mmc_host mmc0: Bus speed (slot 0) = 37125000Hz (slot req 37500000Hz,
> actual 37125000HZ div = 0)
> 
> or run 'cat /sys/kernel/debug/clk/clk_summary |grep phase -C 1' to check
> Otherwise, the mmc0 will run 400khz defalult value to work.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

applied to my dts32 branch for 4.6

Re: [PATCH v3 6/9] ARM: dts: rockchip: add the sdio power sequence for kylin board

[Heiko Stuebner]

Am Freitag, 15. Januar 2016, 21:49:53 schrieb Caesar Wang:
> This patch adds the sdio power sequence for kylin board.
> The WLAN attached to a SDIO interface, wifi/bluetooth have
> reset and power been needed to enable.
> 
> AFAIK, the simple power sequence provider sets a value for multiple GPIOs.
> So the reset and power of WlAN chip can be handled in mmc power sequence.
> On the module itself this is one of these, that should can be handled by
> reset GPIOs in simple mmc power sequence.
> 
> The Bluetooth host wake is high active from bootup, this patch is also
> set pinctrl bias as the default to enable the pull up in soc internal.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

applied to my dts32 branch for 4.6,

after moving the sdio-pwrseq node to its correct alphabetical position. 
Please try to keep to the sorting :-)


Thanks
Heiko

Re: [PATCH v3 7/9] ARM: dts: rockchip: add the sdmmc for kylin board

[Heiko Stuebner]

Am Freitag, 15. Januar 2016, 21:49:54 schrieb Caesar Wang:
> Although We can add the sdmmc node, shouldn't enable it.
> Since the sdmmc is reusing the same pin with uart2.
> Unfortunately, the uart2 is used by the debug port, so that will cause
> the debug information can't display on console if enabling the sdmmc.
> 
> As we have supported the sdmmc (sd card) on hardware for kylin board.
> So, maybe we can have the sdmmc node in kylin dts, not to enable it.
> 
> Anyway, you only need add the okay status if someone want to enable the
> sdmmc.
> 
> e.g.
> if you use the adb to debug with android os.
> You can add the
> status = "okay" to enable the sdmmc for sd card working.
> The defauly status is disabling it.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

applied to my dts32 branch for 4.6


Thanks
Heiko

Re: [PATCH v3 8/9] ARM: dts: rockchip: add reboot-mode node for rk3036 SoCs

[Andy Yan]

Hi Heiko, Caesar:

On 2016年01月18日 03:18, Heiko Stuebner wrote:
> Hi Caesar, Andy,
>
> Am Freitag, 15. Januar 2016, 21:49:55 schrieb Caesar Wang:
>> Add reboot mode driver DT node for rk3036 platform.
>> This patch adds the needed reboot mode node for rk3036.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> this obviously depends on Andy's reboot series.
>
> Andy, could you include this patch into further submissions of your series
> please? That way it won't keep floating unconnected on the lists :-)
>
>
> Thanks
> Heiko
>


     Okay, I will add it in my next series.
>> ---
>>
>> Changes in v3: None
>>
>>   arch/arm/boot/dts/rk3036.dtsi | 28 +++++++++++++++++++++++++++-
>>   1 file changed, 27 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
>> index cf0968c..f5ecfff 100644
>> --- a/arch/arm/boot/dts/rk3036.dtsi
>> +++ b/arch/arm/boot/dts/rk3036.dtsi
>> @@ -43,6 +43,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/pinctrl/rockchip.h>
>>   #include <dt-bindings/clock/rk3036-cru.h>
>> +#include <dt-bindings/soc/rockchip_boot-mode.h>
>>   #include "skeleton.dtsi"
>>
>>   / {
>> @@ -297,8 +298,33 @@
>>   	};
>>
>>   	grf: syscon@20008000 {
>> -		compatible = "rockchip,rk3036-grf", "syscon";
>> +		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
>>   		reg = <0x20008000 0x1000>;
>> +
>> +		reboot-mode {
>> +			compatible = "syscon-reboot-mode";
>> +			offset = <0x1d8>;
>> +
>> +			normal {
>> +				linux,mode = "normal";
>> +				loader,magic = <BOOT_NORMAL>;
>> +			};
>> +
>> +			loader {
>> +				linux,mode = "loader";
>> +				loader,magic = <BOOT_LOADER>;
>> +			};
>> +
>> +			recovery {
>> +				linux,mode = "recovery";
>> +				loader,magic = <BOOT_RECOVERY>;
>> +			};
>> +
>> +			fastboot {
>> +				linux,mode = "fastboot";
>> +				loader,magic = <BOOT_FASTBOOT>;
>> +			};
>> +		};
>>   	};
>>
>>   	acodec: acodec-ana@20030000 {
>
>
>
>

Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1495 bytes --]

On Fri, Jan 15, 2016 at 01:48:04PM -0800, Sonny Rao wrote:
> On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown <broonie@kernel.org> wrote:

> > If the I2S block is providing a clock to the CODEC then that's what the
> > software should do so that the CODEC can gate and ungate the clock as
> > required.  This patch has the I2S block using a clock, not providing
> > one.

> From my read of the clock diagram for RK3288  there is a single clock
> signal (labeled "clk_i2s0") that comes out of a fractional divider,
> and it is split such that one path gets sent to the I2S block and the
> second path is sent to a mux after which that signal is sent to an
> external pin that goes to the codec.

> There are separate clock gates for the two paths: one for the I2S
> block and one after that mux before the external pin.

> I'm not sure if it's being modeled that way in the Linux code or not,
> but at least physically I don't think this clock signal actually goes
> through the I2S block before being sent to the codec.

That's not really the issue here, the issue is that it's not the I2S
controller that is consuming the clock so it should not be the I2S
controller driver that ensures that the clock is enabled.  The driver
that manages the clock should be the one that uses it, like I say this
means you should add the code to enable the clock to the CODEC driver if
the CODEC driver needs the clock enabled.

> Does that help clarify?

The problem here isn't a lack of clarity in the situation.

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Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Jianqun Xu]

Hi Mark

在 23/01/2016 01:18, Mark Brown 写道:
> On Fri, Jan 15, 2016 at 01:48:04PM -0800, Sonny Rao wrote:
>> On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown <broonie@kernel.org> wrote:
>
>>> If the I2S block is providing a clock to the CODEC then that's what the
>>> software should do so that the CODEC can gate and ungate the clock as
>>> required.  This patch has the I2S block using a clock, not providing
>>> one.
>
>>  From my read of the clock diagram for RK3288  there is a single clock
>> signal (labeled "clk_i2s0") that comes out of a fractional divider,
>> and it is split such that one path gets sent to the I2S block and the
>> second path is sent to a mux after which that signal is sent to an
>> external pin that goes to the codec.
>
>> There are separate clock gates for the two paths: one for the I2S
>> block and one after that mux before the external pin.
>
>> I'm not sure if it's being modeled that way in the Linux code or not,
>> but at least physically I don't think this clock signal actually goes
>> through the I2S block before being sent to the codec.
>
> That's not really the issue here, the issue is that it's not the I2S
> controller that is consuming the clock so it should not be the I2S
> controller driver that ensures that the clock is enabled.  The driver
> that manages the clock should be the one that uses it, like I say this
> means you should add the code to enable the clock to the CODEC driver if
> the CODEC driver needs the clock enabled.
>
Agree, now we almost use the simple-card for the CODEC driver, so I 
think we should enable the mclk(i2s-outclk) in the simple-card driver, 
is it ?

I found a subnode property from simple-card document:
- mclk-fs                               : Multiplication factor between 
stream
                                           rate and codec mclk, applied 
only for
                                           the dai-link.
But the property responsible to the factor, not care if the mclk source 
clock is enabled or not. So does the simple-card driver can add support 
to enable/disable mclk ?

>> Does that help clarify?
>
> The problem here isn't a lack of clarity in the situation.
>

Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Heiko Stübner]

Hi Jay,

Am Montag, 25. Januar 2016, 09:15:31 schrieb Jianqun Xu:
> 在 23/01/2016 01:18, Mark Brown 写道:
> > On Fri, Jan 15, 2016 at 01:48:04PM -0800, Sonny Rao wrote:
> >> On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown <broonie@kernel.org> wrote:
> >>> If the I2S block is providing a clock to the CODEC then that's what the
> >>> software should do so that the CODEC can gate and ungate the clock as
> >>> required.  This patch has the I2S block using a clock, not providing
> >>> one.
> >>> 
> >>  From my read of the clock diagram for RK3288  there is a single clock
> >> 
> >> signal (labeled "clk_i2s0") that comes out of a fractional divider,
> >> and it is split such that one path gets sent to the I2S block and the
> >> second path is sent to a mux after which that signal is sent to an
> >> external pin that goes to the codec.
> >> 
> >> There are separate clock gates for the two paths: one for the I2S
> >> block and one after that mux before the external pin.
> >> 
> >> I'm not sure if it's being modeled that way in the Linux code or not,
> >> but at least physically I don't think this clock signal actually goes
> >> through the I2S block before being sent to the codec.
> > 
> > That's not really the issue here, the issue is that it's not the I2S
> > controller that is consuming the clock so it should not be the I2S
> > controller driver that ensures that the clock is enabled.  The driver
> > that manages the clock should be the one that uses it, like I say this
> > means you should add the code to enable the clock to the CODEC driver if
> > the CODEC driver needs the clock enabled.
> 
> Agree, now we almost use the simple-card for the CODEC driver, so I
> think we should enable the mclk(i2s-outclk) in the simple-card driver,
> is it ?
> 
> I found a subnode property from simple-card document:
> - mclk-fs                               : Multiplication factor between
> stream
>                                            rate and codec mclk, applied
> only for
>                                            the dai-link.
> But the property responsible to the factor, not care if the mclk source
> clock is enabled or not. So does the simple-card driver can add support
> to enable/disable mclk ?

The mclk-input is part of the codec I'd think. So you'd want the clocks-
property in the i2c entry describing the codec itself and implement the clk 
operations in the codec driver as well.

See codec-drivers for da7213, da7218,max98090 and many more for reference.


Heiko



> >> Does that help clarify?
> > 
> > The problem here isn't a lack of clarity in the situation.

Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Mark Brown]

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On Tue, Jan 26, 2016 at 10:52:25AM +0100, Heiko Stübner wrote:
> Am Montag, 25. Januar 2016, 09:15:31 schrieb Jianqun Xu:
> > 在 23/01/2016 01:18, Mark Brown 写道:

> > > controller driver that ensures that the clock is enabled.  The driver
> > > that manages the clock should be the one that uses it, like I say this
> > > means you should add the code to enable the clock to the CODEC driver if
> > > the CODEC driver needs the clock enabled.

> > But the property responsible to the factor, not care if the mclk source
> > clock is enabled or not. So does the simple-card driver can add support
> > to enable/disable mclk ?

> The mclk-input is part of the codec I'd think. So you'd want the clocks-
> property in the i2c entry describing the codec itself and implement the clk 
> operations in the codec driver as well.

> See codec-drivers for da7213, da7218,max98090 and many more for reference.

Yes, as I have said repeatedly including in the mail quoted above the
CODEC is using the clock so should be managing it.

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