* [PATCH v1 1/2] x86/platform/intel-mid: enable 64-bit build
@ 2016-01-15 20:11 Andy Shevchenko
2016-01-15 20:11 ` [PATCH v1 2/2] x86/platform/intel-mid: Join string and fix SoC name Andy Shevchenko
2016-01-19 13:37 ` [tip:x86/urgent] x86/platform/intel-mid: Enable 64-bit build tip-bot for Andy Shevchenko
0 siblings, 2 replies; 4+ messages in thread
From: Andy Shevchenko @ 2016-01-15 20:11 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, linux-kernel,
Mika Westerberg
Cc: Andy Shevchenko
Intel Tangier SoC is known to have 64-bit dual core CPU. Enable 64-bit build
for it.
The kernel has been tested on Intel Edison board.
Linux buildroot 4.4.0-next-20160115+ #25 SMP Fri Jan 15 22:03:19 EET 2016 x86_64 GNU/Linux
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 74
model name : Genuine Intel(R) CPU 4000 @ 500MHz
stepping : 8
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/Kconfig | 3 +--
arch/x86/kernel/head64.c | 8 ++++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ebb810f..0ebc19a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -510,11 +510,10 @@ config X86_INTEL_CE
config X86_INTEL_MID
bool "Intel MID platform support"
- depends on X86_32
depends on X86_EXTENDED_PLATFORM
depends on X86_PLATFORM_DEVICES
depends on PCI
- depends on PCI_GOANY
+ depends on X86_64 || (PCI_GOANY && X86_32)
depends on X86_IO_APIC
select SFI
select I2C
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index f129a9a..2c0f340 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -192,5 +192,13 @@ void __init x86_64_start_reservations(char *real_mode_data)
reserve_ebda_region();
+ switch (boot_params.hdr.hardware_subarch) {
+ case X86_SUBARCH_INTEL_MID:
+ x86_intel_mid_early_setup();
+ break;
+ default:
+ break;
+ }
+
start_kernel();
}
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 2/2] x86/platform/intel-mid: Join string and fix SoC name
2016-01-15 20:11 [PATCH v1 1/2] x86/platform/intel-mid: enable 64-bit build Andy Shevchenko
@ 2016-01-15 20:11 ` Andy Shevchenko
2016-01-19 13:37 ` [tip:x86/urgent] " tip-bot for Andy Shevchenko
2016-01-19 13:37 ` [tip:x86/urgent] x86/platform/intel-mid: Enable 64-bit build tip-bot for Andy Shevchenko
1 sibling, 1 reply; 4+ messages in thread
From: Andy Shevchenko @ 2016-01-15 20:11 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, linux-kernel,
Mika Westerberg
Cc: Andy Shevchenko
Join string back to make grepping a bit easier. While here, lowering case for
Penwell SoC name in one case to be aligned with the rest messages.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/platform/intel-mid/intel-mid.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbc21e..90bb997 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -138,7 +138,7 @@ static void intel_mid_arch_setup(void)
intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
else {
intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
- pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
+ pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
}
out:
@@ -214,12 +214,10 @@ static inline int __init setup_x86_intel_mid_timer(char *arg)
else if (strcmp("lapic_and_apbt", arg) == 0)
intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
else {
- pr_warn("X86 INTEL_MID timer option %s not recognised"
- " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
- arg);
+ pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
+ arg);
return -EINVAL;
}
return 0;
}
__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
-
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/urgent] x86/platform/intel-mid: Enable 64-bit build
2016-01-15 20:11 [PATCH v1 1/2] x86/platform/intel-mid: enable 64-bit build Andy Shevchenko
2016-01-15 20:11 ` [PATCH v1 2/2] x86/platform/intel-mid: Join string and fix SoC name Andy Shevchenko
@ 2016-01-19 13:37 ` tip-bot for Andy Shevchenko
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Andy Shevchenko @ 2016-01-19 13:37 UTC (permalink / raw)
To: linux-tip-commits
Cc: hpa, torvalds, tglx, peterz, andriy.shevchenko, linux-kernel,
mingo, bp, luto, dvlasenk, brgerst, mika.westerberg
Commit-ID: 3fda5bb420e79b357328b358409e4c547d8f0a18
Gitweb: http://git.kernel.org/tip/3fda5bb420e79b357328b358409e4c547d8f0a18
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Fri, 15 Jan 2016 22:11:07 +0200
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 19 Jan 2016 08:39:56 +0100
x86/platform/intel-mid: Enable 64-bit build
Intel Tangier SoC is known to have 64-bit dual core CPU. Enable
64-bit build for it.
The kernel has been tested on Intel Edison board:
Linux buildroot 4.4.0-next-20160115+ #25 SMP Fri Jan 15 22:03:19 EET 2016 x86_64 GNU/Linux
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 74
model name : Genuine Intel(R) CPU 4000 @ 500MHz
stepping : 8
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1452888668-147116-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/Kconfig | 3 +--
arch/x86/kernel/head64.c | 8 ++++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 258965d..07459a6 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -495,11 +495,10 @@ config X86_INTEL_CE
config X86_INTEL_MID
bool "Intel MID platform support"
- depends on X86_32
depends on X86_EXTENDED_PLATFORM
depends on X86_PLATFORM_DEVICES
depends on PCI
- depends on PCI_GOANY
+ depends on X86_64 || (PCI_GOANY && X86_32)
depends on X86_IO_APIC
select SFI
select I2C
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index f129a9a..2c0f340 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -192,5 +192,13 @@ void __init x86_64_start_reservations(char *real_mode_data)
reserve_ebda_region();
+ switch (boot_params.hdr.hardware_subarch) {
+ case X86_SUBARCH_INTEL_MID:
+ x86_intel_mid_early_setup();
+ break;
+ default:
+ break;
+ }
+
start_kernel();
}
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/urgent] x86/platform/intel-mid: Join string and fix SoC name
2016-01-15 20:11 ` [PATCH v1 2/2] x86/platform/intel-mid: Join string and fix SoC name Andy Shevchenko
@ 2016-01-19 13:37 ` tip-bot for Andy Shevchenko
0 siblings, 0 replies; 4+ messages in thread
From: tip-bot for Andy Shevchenko @ 2016-01-19 13:37 UTC (permalink / raw)
To: linux-tip-commits
Cc: tglx, hpa, luto, bp, mika.westerberg, dvlasenk, mingo,
linux-kernel, torvalds, peterz, brgerst, andriy.shevchenko
Commit-ID: b000de5848441bc4e99c662fe1fd1b854151a84e
Gitweb: http://git.kernel.org/tip/b000de5848441bc4e99c662fe1fd1b854151a84e
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Fri, 15 Jan 2016 22:11:08 +0200
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 19 Jan 2016 08:39:56 +0100
x86/platform/intel-mid: Join string and fix SoC name
Join string back to make grepping a bit easier. While here,
lowering case for Penwell SoC name in one case to be aligned
with the rest messages.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1452888668-147116-2-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/platform/intel-mid/intel-mid.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbc21e..90bb997 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -138,7 +138,7 @@ static void intel_mid_arch_setup(void)
intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
else {
intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
- pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
+ pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
}
out:
@@ -214,12 +214,10 @@ static inline int __init setup_x86_intel_mid_timer(char *arg)
else if (strcmp("lapic_and_apbt", arg) == 0)
intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
else {
- pr_warn("X86 INTEL_MID timer option %s not recognised"
- " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
- arg);
+ pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
+ arg);
return -EINVAL;
}
return 0;
}
__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
-
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-01-19 13:40 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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