From: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
To: Linux Doc Mailing List <linux-doc@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
Mauro Carvalho Chehab <mchehab@infradead.org>,
linux-kernel@vger.kernel.org, Jonathan Corbet <corbet@lwn.net>,
Chris Zankel <chris@zankel.net>,
Max Filippov <jcmvbkbc@gmail.com>,
linux-xtensa@linux-xtensa.org
Subject: [PATCH v2 71/79] docs: xtensa: convert to ReST
Date: Mon, 22 Apr 2019 10:28:00 -0300 [thread overview]
Message-ID: <1456b80eb12c3f2769aa096d67fd377949ac4235.1555938376.git.mchehab+samsung@kernel.org> (raw)
In-Reply-To: <cover.1555938375.git.mchehab+samsung@kernel.org>
Rename the xtensa documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.
At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
---
.../xtensa/{atomctl.txt => atomctl.rst} | 13 +-
.../xtensa/{booting.txt => booting.rst} | 5 +-
Documentation/xtensa/index.rst | 12 ++
Documentation/xtensa/mmu.rst | 195 ++++++++++++++++++
Documentation/xtensa/mmu.txt | 189 -----------------
arch/xtensa/include/asm/initialize_mmu.h | 2 +-
6 files changed, 222 insertions(+), 194 deletions(-)
rename Documentation/xtensa/{atomctl.txt => atomctl.rst} (81%)
rename Documentation/xtensa/{booting.txt => booting.rst} (91%)
create mode 100644 Documentation/xtensa/index.rst
create mode 100644 Documentation/xtensa/mmu.rst
delete mode 100644 Documentation/xtensa/mmu.txt
diff --git a/Documentation/xtensa/atomctl.txt b/Documentation/xtensa/atomctl.rst
similarity index 81%
rename from Documentation/xtensa/atomctl.txt
rename to Documentation/xtensa/atomctl.rst
index 1da783ac200c..1ecbd0ba9a2e 100644
--- a/Documentation/xtensa/atomctl.txt
+++ b/Documentation/xtensa/atomctl.rst
@@ -1,3 +1,7 @@
+===========================================
+Atomic Operation Control (ATOMCTL) Register
+===========================================
+
We Have Atomic Operation Control (ATOMCTL) Register.
This register determines the effect of using a S32C1I instruction
with various combinations of:
@@ -8,7 +12,7 @@ with various combinations of:
2. With and without An Intelligent Memory Controller which
can do Atomic Transactions itself.
-The Core comes up with a default value of for the three types of cache ops:
+The Core comes up with a default value of for the three types of cache ops::
0x28: (WB: Internal, WT: Internal, BY:Exception)
@@ -30,15 +34,18 @@ CUSTOMER-WARNING:
Developers might find using RCW in Bypass mode convenient when testing
with the cache being bypassed; for example studying cache alias problems.
-See Section 4.3.12.4 of ISA; Bits:
+See Section 4.3.12.4 of ISA; Bits::
WB WT BY
5 4 | 3 2 | 1 0
+
+========= ================== ================== ===============
2 Bit
Field
Values WB - Write Back WT - Write Thru BY - Bypass
---------- --------------- ----------------- ----------------
+========= ================== ================== ===============
0 Exception Exception Exception
1 RCW Transaction RCW Transaction RCW Transaction
2 Internal Operation Internal Operation Reserved
3 Reserved Reserved Reserved
+========= ================== ================== ===============
diff --git a/Documentation/xtensa/booting.txt b/Documentation/xtensa/booting.rst
similarity index 91%
rename from Documentation/xtensa/booting.txt
rename to Documentation/xtensa/booting.rst
index 402b33a2619f..e1b83707e5b6 100644
--- a/Documentation/xtensa/booting.txt
+++ b/Documentation/xtensa/booting.rst
@@ -1,10 +1,13 @@
-Passing boot parameters to the kernel.
+=====================================
+Passing boot parameters to the kernel
+=====================================
Boot parameters are represented as a TLV list in the memory. Please see
arch/xtensa/include/asm/bootparam.h for definition of the bp_tag structure and
tag value constants. First entry in the list must have type BP_TAG_FIRST, last
entry must have type BP_TAG_LAST. The address of the first list entry is
passed to the kernel in the register a2. The address type depends on MMU type:
+
- For configurations without MMU, with region protection or with MPU the
address must be the physical address.
- For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n
diff --git a/Documentation/xtensa/index.rst b/Documentation/xtensa/index.rst
new file mode 100644
index 000000000000..5a24e365e35f
--- /dev/null
+++ b/Documentation/xtensa/index.rst
@@ -0,0 +1,12 @@
+:orphan:
+
+===================
+Xtensa Architecture
+===================
+
+.. toctree::
+ :maxdepth: 1
+
+ atomctl
+ booting
+ mmu
diff --git a/Documentation/xtensa/mmu.rst b/Documentation/xtensa/mmu.rst
new file mode 100644
index 000000000000..e52a12960fdc
--- /dev/null
+++ b/Documentation/xtensa/mmu.rst
@@ -0,0 +1,195 @@
+=============================
+MMUv3 initialization sequence
+=============================
+
+The code in the initialize_mmu macro sets up MMUv3 memory mapping
+identically to MMUv2 fixed memory mapping. Depending on
+CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
+located in addresses it was linked for (symbol undefined), or not
+(symbol defined), so it needs to be position-independent.
+
+The code has the following assumptions:
+
+ - This code fragment is run only on an MMU v3.
+ - TLBs are in their reset state.
+ - ITLBCFG and DTLBCFG are zero (reset state).
+ - RASID is 0x04030201 (reset state).
+ - PS.RING is zero (reset state).
+ - LITBASE is zero (reset state, PC-relative literals); required to be PIC.
+
+TLB setup proceeds along the following steps.
+
+ Legend:
+
+ - VA = virtual address (two upper nibbles of it);
+ - PA = physical address (two upper nibbles of it);
+ - pc = physical range that contains this code;
+
+After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
+or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
+0x40000000 or above. That address corresponds to next instruction to execute
+in this code. After step 4, we jump to intended (linked) address of this code.
+The scheme below assumes that the kernel is loaded below 0x40000000.
+
+ ====== ===== ===== ===== ===== ====== ===== =====
+ - Step0 Step1 Step2 Step3 Step4 Step5
+
+ VA PA PA PA PA VA PA PA
+ ====== ===== ===== ===== ===== ====== ===== =====
+ E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
+ C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
+ A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
+ 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
+ 60..7F -> 60 -> 60 -> 60
+ 40..5F -> 40 -> pc -> pc 40..5F -> pc
+ 20..3F -> 20 -> 20 -> 20
+ 00..1F -> 00 -> 00 -> 00
+ ====== ===== ===== ===== ===== ====== ===== =====
+
+The default location of IO peripherals is above 0xf0000000. This may be changed
+using a "ranges" property in a device tree simple-bus node. See the Devicetree
+Specification, section 4.5 for details on the syntax and semantics of
+simple-bus nodes. The following limitations apply:
+
+1. Only top level simple-bus nodes are considered
+
+2. Only one (first) simple-bus node is considered
+
+3. Empty "ranges" properties are not supported
+
+4. Only the first triplet in the "ranges" property is considered
+
+5. The parent-bus-address value is rounded down to the nearest 256MB boundary
+
+6. The IO area covers the entire 256MB segment of parent-bus-address; the
+ "ranges" triplet length field is ignored
+
+
+MMUv3 address space layouts.
+============================
+
+Default MMUv2-compatible layout::
+
+ Symbol VADDR Size
+ +------------------+
+ | Userspace | 0x00000000 TASK_SIZE
+ +------------------+ 0x40000000
+ +------------------+
+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
+ +------------------+
+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
+ +------------------+ 0x8e400000
+ +------------------+
+ | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
+ +------------------+ VMALLOC_END
+ | Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
+ | remap area 1 |
+ +------------------+
+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
+ | remap area 2 |
+ +------------------+
+ +------------------+
+ | KMAP area | PKMAP_BASE PTRS_PER_PTE *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ | | (4MB * DCACHE_N_COLORS)
+ +------------------+
+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
+ | | NR_CPUS *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ +------------------+ FIXADDR_TOP 0xcffff000
+ +------------------+
+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
+ +------------------+
+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
+ +------------------+
+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
+ +------------------+
+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
+ +------------------+
+
+
+256MB cached + 256MB uncached layout::
+
+ Symbol VADDR Size
+ +------------------+
+ | Userspace | 0x00000000 TASK_SIZE
+ +------------------+ 0x40000000
+ +------------------+
+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
+ +------------------+
+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
+ +------------------+ 0x8e400000
+ +------------------+
+ | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
+ +------------------+ VMALLOC_END
+ | Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
+ | remap area 1 |
+ +------------------+
+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
+ | remap area 2 |
+ +------------------+
+ +------------------+
+ | KMAP area | PKMAP_BASE PTRS_PER_PTE *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ | | (4MB * DCACHE_N_COLORS)
+ +------------------+
+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
+ | | NR_CPUS *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ +------------------+ FIXADDR_TOP 0xaffff000
+ +------------------+
+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
+ +------------------+
+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
+ +------------------+
+ +------------------+
+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
+ +------------------+
+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
+ +------------------+
+
+
+512MB cached + 512MB uncached layout::
+
+ Symbol VADDR Size
+ +------------------+
+ | Userspace | 0x00000000 TASK_SIZE
+ +------------------+ 0x40000000
+ +------------------+
+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
+ +------------------+
+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
+ +------------------+ 0x8e400000
+ +------------------+
+ | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
+ +------------------+ VMALLOC_END
+ | Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
+ | remap area 1 |
+ +------------------+
+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
+ | remap area 2 |
+ +------------------+
+ +------------------+
+ | KMAP area | PKMAP_BASE PTRS_PER_PTE *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ | | (4MB * DCACHE_N_COLORS)
+ +------------------+
+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
+ | | NR_CPUS *
+ | | DCACHE_N_COLORS *
+ | | PAGE_SIZE
+ +------------------+ FIXADDR_TOP 0x9ffff000
+ +------------------+
+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
+ +------------------+
+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
+ +------------------+
+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
+ +------------------+
+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
+ +------------------+
diff --git a/Documentation/xtensa/mmu.txt b/Documentation/xtensa/mmu.txt
deleted file mode 100644
index 318114de63f3..000000000000
--- a/Documentation/xtensa/mmu.txt
+++ /dev/null
@@ -1,189 +0,0 @@
-MMUv3 initialization sequence.
-
-The code in the initialize_mmu macro sets up MMUv3 memory mapping
-identically to MMUv2 fixed memory mapping. Depending on
-CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
-located in addresses it was linked for (symbol undefined), or not
-(symbol defined), so it needs to be position-independent.
-
-The code has the following assumptions:
- This code fragment is run only on an MMU v3.
- TLBs are in their reset state.
- ITLBCFG and DTLBCFG are zero (reset state).
- RASID is 0x04030201 (reset state).
- PS.RING is zero (reset state).
- LITBASE is zero (reset state, PC-relative literals); required to be PIC.
-
-TLB setup proceeds along the following steps.
-
- Legend:
- VA = virtual address (two upper nibbles of it);
- PA = physical address (two upper nibbles of it);
- pc = physical range that contains this code;
-
-After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
-or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
-0x40000000 or above. That address corresponds to next instruction to execute
-in this code. After step 4, we jump to intended (linked) address of this code.
-The scheme below assumes that the kernel is loaded below 0x40000000.
-
- Step0 Step1 Step2 Step3 Step4 Step5
- ===== ===== ===== ===== ===== =====
- VA PA PA PA PA VA PA PA
- ------ -- -- -- -- ------ -- --
- E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
- C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
- A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
- 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
- 60..7F -> 60 -> 60 -> 60
- 40..5F -> 40 -> pc -> pc 40..5F -> pc
- 20..3F -> 20 -> 20 -> 20
- 00..1F -> 00 -> 00 -> 00
-
-The default location of IO peripherals is above 0xf0000000. This may be changed
-using a "ranges" property in a device tree simple-bus node. See the Devicetree
-Specification, section 4.5 for details on the syntax and semantics of
-simple-bus nodes. The following limitations apply:
-
-1. Only top level simple-bus nodes are considered
-
-2. Only one (first) simple-bus node is considered
-
-3. Empty "ranges" properties are not supported
-
-4. Only the first triplet in the "ranges" property is considered
-
-5. The parent-bus-address value is rounded down to the nearest 256MB boundary
-
-6. The IO area covers the entire 256MB segment of parent-bus-address; the
- "ranges" triplet length field is ignored
-
-
-MMUv3 address space layouts.
-============================
-
-Default MMUv2-compatible layout.
-
- Symbol VADDR Size
-+------------------+
-| Userspace | 0x00000000 TASK_SIZE
-+------------------+ 0x40000000
-+------------------+
-| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
-+------------------+
-| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
-+------------------+ 0x8e400000
-+------------------+
-| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
-+------------------+ VMALLOC_END
-| Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
-| remap area 1 |
-+------------------+
-| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
-| remap area 2 |
-+------------------+
-+------------------+
-| KMAP area | PKMAP_BASE PTRS_PER_PTE *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-| | (4MB * DCACHE_N_COLORS)
-+------------------+
-| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
-| | NR_CPUS *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-+------------------+ FIXADDR_TOP 0xcffff000
-+------------------+
-| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
-+------------------+
-| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
-+------------------+
-| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
-+------------------+
-| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
-+------------------+
-
-
-256MB cached + 256MB uncached layout.
-
- Symbol VADDR Size
-+------------------+
-| Userspace | 0x00000000 TASK_SIZE
-+------------------+ 0x40000000
-+------------------+
-| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
-+------------------+
-| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
-+------------------+ 0x8e400000
-+------------------+
-| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
-+------------------+ VMALLOC_END
-| Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
-| remap area 1 |
-+------------------+
-| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
-| remap area 2 |
-+------------------+
-+------------------+
-| KMAP area | PKMAP_BASE PTRS_PER_PTE *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-| | (4MB * DCACHE_N_COLORS)
-+------------------+
-| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
-| | NR_CPUS *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-+------------------+ FIXADDR_TOP 0xaffff000
-+------------------+
-| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
-+------------------+
-| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
-+------------------+
-+------------------+
-| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
-+------------------+
-| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
-+------------------+
-
-
-512MB cached + 512MB uncached layout.
-
- Symbol VADDR Size
-+------------------+
-| Userspace | 0x00000000 TASK_SIZE
-+------------------+ 0x40000000
-+------------------+
-| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
-+------------------+
-| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
-+------------------+ 0x8e400000
-+------------------+
-| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
-+------------------+ VMALLOC_END
-| Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
-| remap area 1 |
-+------------------+
-| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
-| remap area 2 |
-+------------------+
-+------------------+
-| KMAP area | PKMAP_BASE PTRS_PER_PTE *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-| | (4MB * DCACHE_N_COLORS)
-+------------------+
-| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
-| | NR_CPUS *
-| | DCACHE_N_COLORS *
-| | PAGE_SIZE
-+------------------+ FIXADDR_TOP 0x9ffff000
-+------------------+
-| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
-+------------------+
-| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
-+------------------+
-| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
-+------------------+
-| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
-+------------------+
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index 10e9852b2fb4..f75f7f8fc93e 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -46,7 +46,7 @@
#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
/*
* We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
- * For details see Documentation/xtensa/atomctl.txt
+ * For details see Documentation/xtensa/atomctl.rst
*/
#if XCHAL_DCACHE_IS_COHERENT
movi a3, 0x25 /* For SMP/MX -- internal for writeback,
--
2.20.1
next prev parent reply other threads:[~2019-04-22 13:34 UTC|newest]
Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190423132100.GB7132@redhat.com>
2019-04-22 13:26 ` [PATCH v2 00/79] Convert files to ReST Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 01/79] docs: core-api: fix broken references for div64.c and gcd.c Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 02/79] docs: trace: fix some Sphinx warnings Mauro Carvalho Chehab
2019-04-24 15:10 ` Steven Rostedt
2019-04-22 13:26 ` [PATCH v2 03/79] scripts/documentation-file-ref-check: don't parse Next/ dir Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 04/79] docs: aoe: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 05/79] docs: arm64: convert docs to ReST and rename to .rst Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 06/79] docs: cdrom-standard.tex: convert from LaTeX to ReST Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 07/79] docs: cdrom: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 08/79] docs: cgroup-v1: " Mauro Carvalho Chehab
2019-05-06 15:47 ` Tejun Heo
2019-04-22 13:26 ` [PATCH v2 09/79] docs: cgroup-v1/blkio-controller.rst: add a note about CFQ scheduler Mauro Carvalho Chehab
2019-04-22 13:26 ` [PATCH v2 10/79] docs: cpu-freq: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-23 8:21 ` Rafael J. Wysocki
2019-04-22 13:27 ` [PATCH v2 11/79] docs: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 12/79] docs: fault-injection: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 13/79] docs: fb: " Mauro Carvalho Chehab
2019-05-06 13:40 ` Bartlomiej Zolnierkiewicz
2019-04-22 13:27 ` [PATCH v2 14/79] docs: fpga: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 15/79] docs: gpio: " Mauro Carvalho Chehab
2019-04-23 11:23 ` Linus Walleij
2019-04-23 12:36 ` Mauro Carvalho Chehab
2019-04-23 21:30 ` Linus Walleij
2019-04-22 13:27 ` [PATCH v2 16/79] docs: ide: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 17/79] docs: infiniband: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 19/79] docs: kdump: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 20/79] docs: livepatch: " Mauro Carvalho Chehab
2019-04-26 8:10 ` Petr Mladek
2019-04-26 9:04 ` Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 21/79] docs: locking: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 22/79] docs: mic: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 23/79] docs: netlabel: " Mauro Carvalho Chehab
2019-04-22 18:10 ` Paul Moore
2019-04-22 13:27 ` [PATCH v2 24/79] docs: pcmcia: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 25/79] docs: " Mauro Carvalho Chehab
2019-04-22 13:48 ` Bjorn Helgaas
2019-04-22 14:07 ` Mauro Carvalho Chehab
2019-04-25 18:07 ` Mark Brown
2019-04-26 9:46 ` Mauro Carvalho Chehab
2019-04-27 17:25 ` Mark Brown
2019-04-27 18:13 ` Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 26/79] docs: powerpc: " Mauro Carvalho Chehab
2019-04-24 1:15 ` Andrew Donnellan
2019-04-22 13:27 ` [PATCH v2 27/79] docs: pps.txt: convert to ReST and rename to pps.rst Mauro Carvalho Chehab
2019-04-22 16:19 ` Rodolfo Giometti
2019-04-22 13:27 ` [PATCH v2 28/79] docs: ptp.txt: convert to ReST and move to driver-api Mauro Carvalho Chehab
2019-04-22 15:40 ` Richard Cochran
2019-04-22 13:27 ` [PATCH v2 29/79] docs: riscv: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 30/79] docs: Debugging390.txt: convert table to ascii artwork Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 31/79] docs: s390: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-23 16:12 ` Farhan Ali
2019-04-23 19:46 ` Mauro Carvalho Chehab
2019-04-24 11:41 ` Cornelia Huck
2019-04-24 12:30 ` Heiko Carstens
2019-04-24 12:44 ` Mauro Carvalho Chehab
2019-04-24 12:52 ` Cornelia Huck
2019-04-22 13:27 ` [PATCH v2 32/79] s390: include/asm/debug.h add kerneldoc markups Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 33/79] docs: serial: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 34/79] docs: target: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 35/79] docs: timers: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 36/79] docs: watchdog: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 37/79] docs: xilinx: convert eemi.txt to eemi.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 38/79] docs: scheduler: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-23 8:29 ` Peter Zijlstra
2019-04-23 10:32 ` Ingo Molnar
2019-04-23 11:19 ` Peter Zijlstra
2019-04-23 12:30 ` Ingo Molnar
2019-04-22 13:27 ` [PATCH v2 39/79] docs: EDID/HOWTO.txt: convert it and rename to howto.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 40/79] convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 41/79] docs: lcd-panel-cgram.txt: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 42/79] docs: lp855x-driver.txt: convert to ReST and move to kernel-api Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 43/79] docs: m68k: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-05-03 11:55 ` Geert Uytterhoeven
2019-04-22 13:27 ` [PATCH v2 44/79] docs: cma/debugfs.txt: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 45/79] docs: console.txt: " Mauro Carvalho Chehab
2019-05-06 13:41 ` Bartlomiej Zolnierkiewicz
2019-04-22 13:27 ` [PATCH v2 46/79] docs: pti_intel_mid.txt: convert it to pti_intel_mid.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 47/79] docs: early-userspace: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 48/79] docs: driver-model: " Mauro Carvalho Chehab
2019-04-22 14:47 ` Julia Lawall
2019-04-22 22:30 ` Guenter Roeck
2019-04-22 13:27 ` [PATCH v2 50/79] docs: memory-devices: convert ti-emif.txt to ReST Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 51/79] docs: xen-tpmfront.txt: convert it to .rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 52/79] docs: bus-devices: ti-gpmc.rst: convert it to ReST Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 53/79] docs: nvmem: convert docs to ReST and rename to *.rst Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 54/79] docs: phy: convert samsung-usb2.txt to ReST format Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 55/79] docs: rbtree.txt: fix Sphinx build warnings Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 57/79] docs: accounting: convert to ReST Mauro Carvalho Chehab
2019-05-06 15:46 ` Tejun Heo
2019-04-22 13:27 ` [PATCH v2 58/79] docs: fmc: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 59/79] docs: hid: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 60/79] docs: ia64: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 61/79] docs: leds: " Mauro Carvalho Chehab
2019-04-23 19:00 ` Jacek Anaszewski
2019-04-22 13:27 ` [PATCH v2 62/79] docs: laptops: " Mauro Carvalho Chehab
2019-05-06 8:59 ` Andy Shevchenko
2019-04-22 13:27 ` [PATCH v2 63/79] docs: iio: " Mauro Carvalho Chehab
2019-04-22 14:25 ` Jonathan Cameron
2019-04-22 13:27 ` [PATCH v2 64/79] docs: ioctl-number.txt: convert it to ReST format Mauro Carvalho Chehab
2019-04-22 14:05 ` Doug Ledford
2019-04-22 14:17 ` Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 65/79] docs: ioctl: convert to ReST Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 66/79] docs: namespaces: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 67/79] docs: nfc: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 68/79] docs: md: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 69/79] docs: mtd: " Mauro Carvalho Chehab
2019-04-22 13:27 ` [PATCH v2 70/79] docs: nvdimm: " Mauro Carvalho Chehab
2019-04-22 13:28 ` Mauro Carvalho Chehab [this message]
2019-04-22 13:28 ` [PATCH v2 72/79] docs: mmc: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 73/79] docs: sparc: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 74/79] docs: thermal: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 75/79] docs: rapidio: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 76/79] docs: blockdev: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 77/79] docs: perf: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 78/79] docs: sysctl: " Mauro Carvalho Chehab
2019-04-22 13:28 ` [PATCH v2 79/79] docs: block: " Mauro Carvalho Chehab
2019-04-22 14:51 ` [PATCH v2 00/79] Convert files " Mauro Carvalho Chehab
[not found] ` <cda57849a6462ccc72dcd360b30068ab6a1021c4.1555938376.git.mchehab+samsung@kernel.org>
[not found] ` <20190423083135.GA11158@hirez.programming.kicks-ass.net>
[not found] ` <20190423125519.GA7104@redhat.com>
[not found] ` <20190423130132.GT4038@hirez.programming.kicks-ass.net>
2019-04-23 14:52 ` [PATCH v2 56/79] docs: Documentation/*.txt: rename all ReST files to *.rst David Howells
2019-04-23 16:54 ` Jonathan Corbet
2019-04-23 17:12 ` Peter Zijlstra
2019-04-23 20:26 ` Mauro Carvalho Chehab
2019-04-24 11:51 ` Mike Rapoport
2019-04-24 12:57 ` Mauro Carvalho Chehab
2019-04-23 19:37 ` Mauro Carvalho Chehab
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