* [PATCH v3 1/8] ARM: dts: Add initial pin configuration for exynos3250-rinato
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree, Kukjin Kim
This patch adds initial pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pins in normal state.
All pins included in this patch are NC (not connected) pin.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 38 +++++++++++++++++
arch/arm/boot/dts/exynos3250-rinato.dts | 71 ++++++++++++++++++++++++++++++-
2 files changed, 107 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 5ab81c39e2c9..ecf79386e891 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -16,11 +16,49 @@
#define PIN_PULL_DOWN 1
#define PIN_PULL_UP 3
+#define PIN_DRV_LV1 0
+#define PIN_DRV_LV2 2
+#define PIN_DRV_LV3 1
+#define PIN_DRV_LV4 3
+
#define PIN_PDN_OUT0 0
#define PIN_PDN_OUT1 1
#define PIN_PDN_INPUT 2
#define PIN_PDN_PREV 3
+#define PIN_IN(_pin, _pull, _drv) \
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-function = <0>; \
+ samsung,pin-pud = <PIN_PULL_ ##_pull>; \
+ samsung,pin-drv = <PIN_DRV_ ##_drv>; \
+ }
+
+#define PIN_OUT(_pin, _drv) \
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-function = <1>; \
+ samsung,pin-pud = <0>; \
+ samsung,pin-drv = <PIN_DRV_ ##_drv>; \
+ }
+
+#define PIN_OUT_SET(_pin, _val, _drv) \
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-function = <1>; \
+ samsung,pin-pud = <0>; \
+ samsung,pin-drv = <PIN_DRV_ ##_drv>; \
+ samsung,pin-val = <_val>; \
+ }
+
+#define PIN_CFG(_pin, _sel, _pull, _drv) \
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-function = <_sel>; \
+ samsung,pin-pud = <PIN_PULL_ ##_pull>; \
+ samsung,pin-drv = <PIN_DRV_ ##_drv>; \
+ }
+
#define PIN_SLP(_pin, _mode, _pull) \
_pin { \
samsung,pins = #_pin; \
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3e64d5dcdd60..a01e61b20385 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -681,7 +681,21 @@
&pinctrl_0 {
pinctrl-names = "default";
- pinctrl-0 = <&sleep0>;
+ pinctrl-0 = <&initial0 &sleep0>;
+
+ initial0: initial-state {
+ PIN_IN(gpa1-4, DOWN, LV1);
+ PIN_IN(gpa1-5, DOWN, LV1);
+
+ PIN_IN(gpc0-0, DOWN, LV1);
+ PIN_IN(gpc0-1, DOWN, LV1);
+ PIN_IN(gpc0-2, DOWN, LV1);
+ PIN_IN(gpc0-3, DOWN, LV1);
+ PIN_IN(gpc0-4, DOWN, LV1);
+
+ PIN_IN(gpd0-0, DOWN, LV1);
+ PIN_IN(gpd0-1, DOWN, LV1);
+ };
sleep0: sleep-state {
PIN_SLP(gpa0-0, INPUT, DOWN);
@@ -735,7 +749,60 @@
&pinctrl_1 {
pinctrl-names = "default";
- pinctrl-0 = <&sleep1>;
+ pinctrl-0 = <&initial1 &sleep1>;
+
+ initial1: initial-state {
+ PIN_IN(gpe0-6, DOWN, LV1);
+ PIN_IN(gpe0-7, DOWN, LV1);
+
+ PIN_IN(gpe1-0, DOWN, LV1);
+ PIN_IN(gpe1-3, DOWN, LV1);
+ PIN_IN(gpe1-4, DOWN, LV1);
+ PIN_IN(gpe1-5, DOWN, LV1);
+ PIN_IN(gpe1-6, DOWN, LV1);
+
+ PIN_IN(gpk2-0, DOWN, LV1);
+ PIN_IN(gpk2-1, DOWN, LV1);
+ PIN_IN(gpk2-2, DOWN, LV1);
+ PIN_IN(gpk2-3, DOWN, LV1);
+ PIN_IN(gpk2-4, DOWN, LV1);
+ PIN_IN(gpk2-5, DOWN, LV1);
+ PIN_IN(gpk2-6, DOWN, LV1);
+
+ PIN_IN(gpm0-0, DOWN, LV1);
+ PIN_IN(gpm0-1, DOWN, LV1);
+ PIN_IN(gpm0-2, DOWN, LV1);
+ PIN_IN(gpm0-3, DOWN, LV1);
+ PIN_IN(gpm0-4, DOWN, LV1);
+ PIN_IN(gpm0-5, DOWN, LV1);
+ PIN_IN(gpm0-6, DOWN, LV1);
+ PIN_IN(gpm0-7, DOWN, LV1);
+
+ PIN_IN(gpm1-0, DOWN, LV1);
+ PIN_IN(gpm1-1, DOWN, LV1);
+ PIN_IN(gpm1-2, DOWN, LV1);
+ PIN_IN(gpm1-3, DOWN, LV1);
+ PIN_IN(gpm1-4, DOWN, LV1);
+ PIN_IN(gpm1-5, DOWN, LV1);
+ PIN_IN(gpm1-6, DOWN, LV1);
+
+ PIN_IN(gpm2-0, DOWN, LV1);
+ PIN_IN(gpm2-1, DOWN, LV1);
+
+ PIN_IN(gpm3-0, DOWN, LV1);
+ PIN_IN(gpm3-1, DOWN, LV1);
+ PIN_IN(gpm3-2, DOWN, LV1);
+ PIN_IN(gpm3-3, DOWN, LV1);
+ PIN_IN(gpm3-4, DOWN, LV1);
+
+ PIN_IN(gpm4-1, DOWN, LV1);
+ PIN_IN(gpm4-2, DOWN, LV1);
+ PIN_IN(gpm4-3, DOWN, LV1);
+ PIN_IN(gpm4-4, DOWN, LV1);
+ PIN_IN(gpm4-5, DOWN, LV1);
+ PIN_IN(gpm4-6, DOWN, LV1);
+ PIN_IN(gpm4-7, DOWN, LV1);
+ };
sleep1: sleep-state {
PIN_SLP(gpe0-0, PREV, NONE);
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 1/8] ARM: dts: Add initial pin configuration for exynos3250-rinato Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-24 23:39 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
From: Pankaj Dubey <pankaj.dubey@samsung.com>
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
include/dt-bindings/clock/exynos3250.h | 6 +++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index fdd41b17a24f..bc60e399d1bc 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 63d01c15d2b3..ddb874130d86 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,7 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
/* Dividers */
#define CLK_DIV_GPL 64
@@ -127,6 +128,7 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -223,6 +225,7 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -249,12 +252,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 248
+#define CLK_NR_CLKS 249
/*
* CMU DMC
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock
2016-03-15 7:38 ` [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
@ 2016-03-24 23:39 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-24 23:39 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
linux-samsung-soc, linux-arm-kernel, linux-kernel, devicetree
Ping.
Hi Sylwester,
Could you review this patch?
Regards,
Chanwoo Choi
On 2016년 03월 15일 16:38, Chanwoo Choi wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
> include/dt-bindings/clock/exynos3250.h | 6 +++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index fdd41b17a24f..bc60e399d1bc 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
>
> /* SRC_PERIL0 */
> + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
> MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>
> @@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> /* DIV_PERIL0 */
> + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>
> @@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> +
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> @@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> };
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index 63d01c15d2b3..ddb874130d86 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -79,6 +79,7 @@
> #define CLK_MOUT_CORE 58
> #define CLK_MOUT_APLL 59
> #define CLK_MOUT_ACLK_266_SUB 60
> +#define CLK_MOUT_UART2 61
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -127,6 +128,7 @@
> #define CLK_DIV_CORE 107
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> +#define CLK_DIV_UART2 110
>
> /* Gates */
> #define CLK_ASYNC_G3D 128
> @@ -223,6 +225,7 @@
> #define CLK_BLOCK_MFC 219
> #define CLK_BLOCK_CAM 220
> #define CLK_SMIES 221
> +#define CLK_UART2 222
>
> /* Special clocks */
> #define CLK_SCLK_JPEG 224
> @@ -249,12 +252,13 @@
> #define CLK_SCLK_SPI0 245
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0 247
> +#define CLK_SCLK_UART2 248
>
> /*
> * Total number of clocks of main CMU.
> * NOTE: Must be equal to last clock ID increased by one.
> */
> -#define CLK_NR_CLKS 248
> +#define CLK_NR_CLKS 249
>
> /*
> * CMU DMC
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 1/8] ARM: dts: Add initial pin configuration for exynos3250-rinato Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-24 23:39 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 4/8] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++
include/dt-bindings/clock/exynos3250.h | 7 ++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index bc60e399d1bc..16575ee874cb 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
/* SRC_FSYS */
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
@@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
/* DIV_PERIL0 */
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index ddb874130d86..c796ff02ceeb 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -80,6 +80,7 @@
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
#define CLK_MOUT_UART2 61
+#define CLK_MOUT_MMC2 62
/* Dividers */
#define CLK_DIV_GPL 64
@@ -129,6 +130,8 @@
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
#define CLK_DIV_UART2 110
+#define CLK_DIV_MMC2_PRE 111
+#define CLK_DIV_MMC2 112
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -226,6 +229,7 @@
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
#define CLK_UART2 222
+#define CLK_SDMMC2 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -253,12 +257,13 @@
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
#define CLK_SCLK_UART2 248
+#define CLK_SCLK_MMC2 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 249
+#define CLK_NR_CLKS 250
/*
* CMU DMC
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-15 7:38 ` [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
@ 2016-03-24 23:39 ` Chanwoo Choi
2016-03-25 9:50 ` Sylwester Nawrocki
0 siblings, 1 reply; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-24 23:39 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
linux-samsung-soc, linux-arm-kernel, linux-kernel, devicetree
Ping.
Hi Sylwester,
Could you review this patch?
Regards,
Chanwoo Choi
On 2016년 03월 15일 16:38, Chanwoo Choi wrote:
> This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++
> include/dt-bindings/clock/exynos3250.h | 7 ++++++-
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index bc60e399d1bc..16575ee874cb 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
>
> /* SRC_FSYS */
> MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
> + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
> MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
>
> @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
> CLK_SET_RATE_PARENT, 0),
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> + /* DIV_FSYS2 */
> + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
> + CLK_SET_RATE_PARENT, 0),
> + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
> +
> /* DIV_PERIL0 */
> DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
> GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
> + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
> GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
> @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
> GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
> GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
> GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
> GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
> GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index ddb874130d86..c796ff02ceeb 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -80,6 +80,7 @@
> #define CLK_MOUT_APLL 59
> #define CLK_MOUT_ACLK_266_SUB 60
> #define CLK_MOUT_UART2 61
> +#define CLK_MOUT_MMC2 62
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -129,6 +130,8 @@
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> #define CLK_DIV_UART2 110
> +#define CLK_DIV_MMC2_PRE 111
> +#define CLK_DIV_MMC2 112
>
> /* Gates */
> #define CLK_ASYNC_G3D 128
> @@ -226,6 +229,7 @@
> #define CLK_BLOCK_CAM 220
> #define CLK_SMIES 221
> #define CLK_UART2 222
> +#define CLK_SDMMC2 223
>
> /* Special clocks */
> #define CLK_SCLK_JPEG 224
> @@ -253,12 +257,13 @@
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0 247
> #define CLK_SCLK_UART2 248
> +#define CLK_SCLK_MMC2 249
>
> /*
> * Total number of clocks of main CMU.
> * NOTE: Must be equal to last clock ID increased by one.
> */
> -#define CLK_NR_CLKS 249
> +#define CLK_NR_CLKS 250
>
> /*
> * CMU DMC
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-24 23:39 ` Chanwoo Choi
@ 2016-03-25 9:50 ` Sylwester Nawrocki
2016-03-28 0:44 ` Chanwoo Choi
0 siblings, 1 reply; 20+ messages in thread
From: Sylwester Nawrocki @ 2016-03-25 9:50 UTC (permalink / raw)
To: Chanwoo Choi
Cc: k.kozlowski, kgene, tomasz.figa, jh80.chung, andi.shyti,
inki.dae, sw0312.kim, pankaj.dubey, linux-samsung-soc,
linux-arm-kernel, linux-kernel, devicetree
Hi Chanwoo,
On 03/25/2016 12:39 AM, Chanwoo Choi wrote:
> diff --git a/include/dt-bindings/clock/exynos3250.h
> b/include/dt-bindings/clock/exynos3250.h
>> index ddb874130d86..c796ff02ceeb 100644
>> --- a/include/dt-bindings/clock/exynos3250.h
>> +++ b/include/dt-bindings/clock/exynos3250.h
...
>> -#define CLK_NR_CLKS 249
>> +#define CLK_NR_CLKS 250
What do you think about putting all the changes to include/dt-bindings/
clock/exynos3250.h into a separate patch? Now in patch 3/8 there
is being changed again what was added in patch 2/8. However, my main
point is to have a minimum required in a common topic branch for the clk
and the arm-soc trees, so there is no need for arm-soc to pull all
the drives/clk changes.
It might not be that sensible in case of just those 2 patches in your
series, nevertheless it would be good to keep that in mind for future
submissions.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-25 9:50 ` Sylwester Nawrocki
@ 2016-03-28 0:44 ` Chanwoo Choi
2016-03-29 1:48 ` Krzysztof Kozlowski
2016-03-30 9:30 ` Sylwester Nawrocki
0 siblings, 2 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-28 0:44 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: k.kozlowski, kgene, tomasz.figa, jh80.chung, andi.shyti,
inki.dae, sw0312.kim, pankaj.dubey, linux-samsung-soc,
linux-arm-kernel, linux-kernel, devicetree
Hi Sylwester,
On 2016년 03월 25일 18:50, Sylwester Nawrocki wrote:
> Hi Chanwoo,
>
> On 03/25/2016 12:39 AM, Chanwoo Choi wrote:
>> diff --git a/include/dt-bindings/clock/exynos3250.h
>> b/include/dt-bindings/clock/exynos3250.h
>>> index ddb874130d86..c796ff02ceeb 100644
>>> --- a/include/dt-bindings/clock/exynos3250.h
>>> +++ b/include/dt-bindings/clock/exynos3250.h
> ...
>>> -#define CLK_NR_CLKS 249
>>> +#define CLK_NR_CLKS 250
>
> What do you think about putting all the changes to include/dt-bindings/
> clock/exynos3250.h into a separate patch? Now in patch 3/8 there
> is being changed again what was added in patch 2/8. However, my main
> point is to have a minimum required in a common topic branch for the clk
> and the arm-soc trees, so there is no need for arm-soc to pull all
> the drives/clk changes.
> It might not be that sensible in case of just those 2 patches in your
> series, nevertheless it would be good to keep that in mind for future
> submissions.
You mean that separate patch1 include only the new clock id about both UART2 and MMC2
and the patch2/patch3 just use the new clock id as following:
patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
patch2 clk: samsung: exynos3250: Add UART2 clock
patch3 clk: samsung: exynos3250: Add MMC2 clock
As far as I understand it is that right?
If it is ok, I'll modify it on v4 patchset as you comment.
Best Regards,
Chanwoo Choi
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-28 0:44 ` Chanwoo Choi
@ 2016-03-29 1:48 ` Krzysztof Kozlowski
2016-03-30 9:37 ` Sylwester Nawrocki
2016-03-31 11:04 ` Sylwester Nawrocki
2016-03-30 9:30 ` Sylwester Nawrocki
1 sibling, 2 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2016-03-29 1:48 UTC (permalink / raw)
To: Chanwoo Choi, Sylwester Nawrocki
Cc: kgene, tomasz.figa, jh80.chung, andi.shyti, inki.dae, sw0312.kim,
pankaj.dubey, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
On 28.03.2016 09:44, Chanwoo Choi wrote:
> You mean that separate patch1 include only the new clock id about both UART2 and MMC2
> and the patch2/patch3 just use the new clock id as following:
>
> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
> patch2 clk: samsung: exynos3250: Add UART2 clock
> patch3 clk: samsung: exynos3250: Add MMC2 clock
>
> As far as I understand it is that right?
> If it is ok, I'll modify it on v4 patchset as you comment.
Hi Sylwester and Tomasz,
Can you provide me a tag with these exynos3250 clock patches (after
posting v4)? Of course you can also ack/review them and then I'll handle it.
BR,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-29 1:48 ` Krzysztof Kozlowski
@ 2016-03-30 9:37 ` Sylwester Nawrocki
2016-03-31 11:04 ` Sylwester Nawrocki
1 sibling, 0 replies; 20+ messages in thread
From: Sylwester Nawrocki @ 2016-03-30 9:37 UTC (permalink / raw)
To: Krzysztof Kozlowski, Chanwoo Choi
Cc: kgene, tomasz.figa, jh80.chung, andi.shyti, inki.dae, sw0312.kim,
pankaj.dubey, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
On 03/29/2016 03:48 AM, Krzysztof Kozlowski wrote:
> On 28.03.2016 09:44, Chanwoo Choi wrote:
>> > You mean that separate patch1 include only the new clock id about both UART2 and MMC2
>> > and the patch2/patch3 just use the new clock id as following:
>> >
>> > patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>> > patch2 clk: samsung: exynos3250: Add UART2 clock
>> > patch3 clk: samsung: exynos3250: Add MMC2 clock
>> >
>> > As far as I understand it is that right?
>> > If it is ok, I'll modify it on v4 patchset as you comment.
>
> Hi Sylwester and Tomasz,
>
> Can you provide me a tag with these exynos3250 clock patches (after
> posting v4)? Of course you can also ack/review them and then I'll handle it.
OK, I will provide a stable branch as soon as there is v4 available.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-29 1:48 ` Krzysztof Kozlowski
2016-03-30 9:37 ` Sylwester Nawrocki
@ 2016-03-31 11:04 ` Sylwester Nawrocki
2016-04-01 0:15 ` Krzysztof Kozlowski
1 sibling, 1 reply; 20+ messages in thread
From: Sylwester Nawrocki @ 2016-03-31 11:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chanwoo Choi, kgene, tomasz.figa, jh80.chung, andi.shyti,
inki.dae, sw0312.kim, pankaj.dubey, linux-samsung-soc,
linux-arm-kernel, linux-kernel, devicetree
On 03/29/2016 03:48 AM, Krzysztof Kozlowski wrote:
> On 28.03.2016 09:44, Chanwoo Choi wrote:
>> You mean that separate patch1 include only the new clock id
>> about both UART2 and MMC2
>> and the patch2/patch3 just use the new clock id as following:
>>
>> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>> patch2 clk: samsung: exynos3250: Add UART2 clock
>> patch3 clk: samsung: exynos3250: Add MMC2 clock
>>
>> As far as I understand it is that right?
>> If it is ok, I'll modify it on v4 patchset as you comment.
>
> Hi Sylwester and Tomasz,
>
> Can you provide me a tag with these exynos3250 clock patches (after
> posting v4)? Of course you can also ack/review them and then I'll
> handle it.
Here are tags with only the first (clock id definitions) and the all
three clk patches respectively:
---------------------------------------8<--------------------------------
The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250-dt
for you to fetch changes up to fd00bbcddb59c4866e7c985e30f663b62cfc2588:
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 (2016-03-31 12:25:44 +0200)
----------------------------------------------------------------
Addition of the UART2 and MMC3 clock indices definition
to the exynos3250 clock subsystem dt binding header file.
----------------------------------------------------------------
Chanwoo Choi (1):
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
include/dt-bindings/clock/exynos3250.h | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
--------------------------------------->8--------------------------------
---------------------------------------8<--------------------------------
The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250
for you to fetch changes up to f6764714afdde1f0f511bb0e2d531593c3bec827:
clk: samsung: exynos3250: Add MMC2 clock (2016-03-31 12:25:54 +0200)
----------------------------------------------------------------
Addition of the Exynos3250 SoC's UART2 and MMC2 clocks.
----------------------------------------------------------------
Chanwoo Choi (2):
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
clk: samsung: exynos3250: Add MMC2 clock
Pankaj Dubey (1):
clk: samsung: exynos3250: Add UART2 clock
drivers/clk/samsung/clk-exynos3250.c | 15 +++++++++++++++
include/dt-bindings/clock/exynos3250.h | 11 ++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
--------------------------------------->8--------------------------------
Cheers,
Sylwester
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-31 11:04 ` Sylwester Nawrocki
@ 2016-04-01 0:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2016-04-01 0:15 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Chanwoo Choi, kgene, tomasz.figa, jh80.chung, andi.shyti,
inki.dae, sw0312.kim, pankaj.dubey, linux-samsung-soc,
linux-arm-kernel, linux-kernel, devicetree
On 31.03.2016 20:04, Sylwester Nawrocki wrote:
> On 03/29/2016 03:48 AM, Krzysztof Kozlowski wrote:
>> On 28.03.2016 09:44, Chanwoo Choi wrote:
>>> You mean that separate patch1 include only the new clock id
>>> about both UART2 and MMC2
>>> and the patch2/patch3 just use the new clock id as following:
>>>
>>> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>>> patch2 clk: samsung: exynos3250: Add UART2 clock
>>> patch3 clk: samsung: exynos3250: Add MMC2 clock
>>>
>>> As far as I understand it is that right?
>>> If it is ok, I'll modify it on v4 patchset as you comment.
>>
>> Hi Sylwester and Tomasz,
>>
>> Can you provide me a tag with these exynos3250 clock patches (after
>> posting v4)? Of course you can also ack/review them and then I'll
>> handle it.
>
> Here are tags with only the first (clock id definitions) and the all
> three clk patches respectively:
>
> ---------------------------------------8<--------------------------------
> The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
>
> Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
>
> are available in the git repository at:
>
> git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250-dt
>
> for you to fetch changes up to fd00bbcddb59c4866e7c985e30f663b62cfc2588:
>
> dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 (2016-03-31 12:25:44 +0200)
>
> ----------------------------------------------------------------
> Addition of the UART2 and MMC3 clock indices definition
> to the exynos3250 clock subsystem dt binding header file.
>
> ----------------------------------------------------------------
> Chanwoo Choi (1):
> dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>
> include/dt-bindings/clock/exynos3250.h | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
> --------------------------------------->8--------------------------------
>
>
> ---------------------------------------8<--------------------------------
> The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
>
> Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
>
> are available in the git repository at:
>
> git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250
Thanks pulled.
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock
2016-03-28 0:44 ` Chanwoo Choi
2016-03-29 1:48 ` Krzysztof Kozlowski
@ 2016-03-30 9:30 ` Sylwester Nawrocki
1 sibling, 0 replies; 20+ messages in thread
From: Sylwester Nawrocki @ 2016-03-30 9:30 UTC (permalink / raw)
To: Chanwoo Choi
Cc: k.kozlowski, kgene, tomasz.figa, jh80.chung, andi.shyti,
inki.dae, sw0312.kim, pankaj.dubey, linux-samsung-soc,
linux-arm-kernel, linux-kernel, devicetree
On 03/28/2016 02:44 AM, Chanwoo Choi wrote:
> You mean that separate patch1 include only the new clock id about both UART2 and MMC2
> and the patch2/patch3 just use the new clock id as following:
>
> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
> patch2 clk: samsung: exynos3250: Add UART2 clock
> patch3 clk: samsung: exynos3250: Add MMC2 clock
>
> As far as I understand it is that right?
> If it is ok, I'll modify it on v4 patchset as you comment.
Yeah, that's what I meant.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 4/8] ARM: dts: Add UART2 dt node for Exynos3250 SoC
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
` (2 preceding siblings ...)
2016-03-15 7:38 ` [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 5/8] ARM: dts: Add initial gpio setting of MMC2 device for exynos3250-monk Chanwoo Choi
` (3 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
From: Pankaj Dubey <pankaj.dubey@samsung.com>
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index ecf79386e891..54c587f27265 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -158,6 +158,13 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf48..076677384d20 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
};
cpus {
@@ -465,6 +466,17 @@
status = "disabled";
};
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 5/8] ARM: dts: Add initial gpio setting of MMC2 device for exynos3250-monk
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
` (3 preceding siblings ...)
2016-03-15 7:38 ` [PATCH v3 4/8] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 6/8] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC Chanwoo Choi
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
This patch adds initial pin configuration of MMC2 device on exynos3250-monk
board because the MMC2 gpio pin (gpk2[0-6]) are NC (not connected) state.
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
arch/arm/boot/dts/exynos3250-monk.dts | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 443a35085846..dab965f35352 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -558,7 +558,17 @@
&pinctrl_1 {
pinctrl-names = "default";
- pinctrl-0 = <&sleep1>;
+ pinctrl-0 = <&initial1 &sleep1>;
+
+ initial1: initial-state {
+ PIN_IN(gpk2-0, DOWN, LV1);
+ PIN_IN(gpk2-1, DOWN, LV1);
+ PIN_IN(gpk2-2, DOWN, LV1);
+ PIN_IN(gpk2-3, DOWN, LV1);
+ PIN_IN(gpk2-4, DOWN, LV1);
+ PIN_IN(gpk2-5, DOWN, LV1);
+ PIN_IN(gpk2-6, DOWN, LV1);
+ };
sleep1: sleep-state {
PIN_SLP(gpe0-0, PREV, NONE);
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 6/8] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
` (4 preceding siblings ...)
2016-03-15 7:38 ` [PATCH v3 5/8] ARM: dts: Add initial gpio setting of MMC2 device for exynos3250-monk Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module Chanwoo Choi
2016-03-15 7:38 ` [PATCH v3 8/8] ARM: dts: Add MSHC2 dt node for SD card for exynos3250-artik5-eval board Chanwoo Choi
7 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
Exynos3250 SoC.
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 54c587f27265..40ea7de44933 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -490,6 +490,41 @@
samsung,pin-drv = <3>;
};
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 076677384d20..2fead5730879 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -30,6 +30,7 @@
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
@@ -371,6 +372,18 @@
status = "disabled";
};
+ mshc_2: mshc@12530000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 144 0>;
+ clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
exynos_usbphy: exynos-usbphy@125B0000 {
compatible = "samsung,exynos3250-usb2-phy";
reg = <0x125B0000 0x100>;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
` (5 preceding siblings ...)
2016-03-15 7:38 ` [PATCH v3 6/8] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
2016-03-18 21:01 ` Rob Herring
2016-03-15 7:38 ` [PATCH v3 8/8] ARM: dts: Add MSHC2 dt node for SD card for exynos3250-artik5-eval board Chanwoo Choi
7 siblings, 1 reply; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
- Application Processor (Samsung Exynos3250)
- WiFi/BT Combo chip (Broadcom4354)
- PMIC (Samsung S2MPS14)
- eMMC (4GB)
- DRAM LPDDR3 (512MB)
- Connectors pin (60 Pins x 3 set)
Also, this patch adds the ARTIK5 evaluation board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.
[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-search/en?FV=ffecca14
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
.../bindings/arm/samsung/samsung-boards.txt | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos3250-artik5-eval.dts | 26 ++
arch/arm/boot/dts/exynos3250-artik5.dtsi | 334 +++++++++++++++++++++
4 files changed, 363 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos3250-artik5-eval.dts
create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 12129c011c8f..f5deace2b380 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -2,6 +2,8 @@
Required root node properties:
- compatible = should be one or more of the following.
+ - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
+ - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a4a6d70e8b26..85cd586ea3d2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \
dtb-$(CONFIG_ARCH_EFM32) += \
efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
+ exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
exynos3250-rinato.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += \
diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
new file mode 100644
index 000000000000..b476154590a5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
@@ -0,0 +1,26 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 evaluation board
+ * which is based on Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250-artik5.dtsi"
+
+/ {
+ model = "Samsung ARTIK5 evaluation board";
+ compatible = "samsung,artik5-eval", "samsung,artik5",
+ "samsung,exynos3250", "samsung,exynos3";
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
new file mode 100644
index 000000000000..130e946f1414
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -0,0 +1,334 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 module device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 module which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos3250.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
+
+ chosen {
+ stdout-path = &serial_2;
+ };
+
+ memory {
+ reg = <0x40000000 0x1ff00000>;
+ };
+
+ firmware@0205f000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0205f000 0x1000>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 500MHz */
+ cooling-device = <&cpu0 5 5>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 8 8>;
+ };
+ };
+ };
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo7_reg>;
+ assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+ assigned-clock-rates = <6000000>;
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&i2c_0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ s2mps14_pmic@66 {
+ compatible = "samsung,s2mps14-pmic";
+ interrupt-parent = <&gpx3>;
+ interrupts = <5 IRQ_TYPE_NONE>;
+ reg = <0x66>;
+
+ s2mps14_osc: clocks {
+ compatible = "samsung,s2mps14-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps14_ap", "unused",
+ "s2mps14_bt";
+ };
+
+ regulators {
+ ldo1_reg: LDO1 {
+ /* VDD_ALIVE15x */
+ regulator-name = "VLDO1_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ /* VDDQM176 ~ VDDQM185 */
+ regulator-name = "VLDO2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ /*
+ * VDD1_E106 ~ VDD1_E111
+ * DVDD_RTC_AP, DVDD_MMC2_AP
+ */
+ regulator-name = "VLDO3_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ /* AVDD_PLL1120 ~ AVDD_PLL11201 */
+ regulator-name = "VLDO4_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
+ regulator-name = "VLDO5_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ /* VDD_USB, VDD10_HSIC */
+ regulator-name = "VLDO6_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ /*
+ * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
+ * AVDD_ADC, AVDD_ABB_0, M4S_VDD18
+ */
+ regulator-name = "VLDO7_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: LDO8 {
+ /* AVDD33_UOTG */
+ regulator-name = "VLDO8_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ ldo9_reg: LDO9 {
+ /* VDDQ_E86 ~ VDDQ_E105*/
+ regulator-name = "VLDO9_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VLDO10_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo11_reg: LDO11 {
+ /* VDD74 ~ VDD75 */
+ regulator-name = "VLDO11_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ ldo12_reg: LDO12 {
+ /* VDD72 ~ VDD73 */
+ regulator-name = "VLDO12_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VLDO13_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VLDO14_2.7V";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VLDO_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VLDO16_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VLDO17_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo18_reg: LDO18 {
+ /* DVDD_MMC2_AP */
+ regulator-name = "VLDO18_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VLDO19_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VLDO20_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VLDO21_1.25V";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VLDO22_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo23_reg: LDO23 {
+ /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
+ regulator-name = "VLDO23_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VLDO24_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VLDO25_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ /* VDD_MIF */
+ regulator-name = "VBUCK1_1.0V";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ buck2_reg: BUCK2 {
+ /* VDD_CPU */
+ regulator-name = "VBUCK2_1.2V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck3_reg: BUCK3 {
+ /* VDD_G3D */
+ regulator-name = "VBUCK3_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VBUCK4_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VBUCK5_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&mshc_0 {
+ num-slots = <1>;
+ non-removable;
+ cap-mmc-highspeed;
+ card-detect-delay = <200>;
+ vmmc-supply = <&ldo12_reg>;
+ clock-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+ status = "okay";
+};
+
+&tmu {
+ status = "okay";
+};
+
+&xusbxti {
+ clock-frequency = <24000000>;
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module
2016-03-15 7:38 ` [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module Chanwoo Choi
@ 2016-03-18 21:01 ` Rob Herring
2016-03-19 11:44 ` Chanwoo Choi
0 siblings, 1 reply; 20+ messages in thread
From: Rob Herring @ 2016-03-18 21:01 UTC (permalink / raw)
To: Chanwoo Choi
Cc: k.kozlowski, kgene, s.nawrocki, tomasz.figa, jh80.chung,
andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
linux-samsung-soc, linux-arm-kernel, linux-kernel, devicetree
On Tue, Mar 15, 2016 at 04:38:09PM +0900, Chanwoo Choi wrote:
> This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
> based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
s/follwoing/following/
> - Application Processor (Samsung Exynos3250)
> - WiFi/BT Combo chip (Broadcom4354)
> - PMIC (Samsung S2MPS14)
> - eMMC (4GB)
> - DRAM LPDDR3 (512MB)
> - Connectors pin (60 Pins x 3 set)
>
> Also, this patch adds the ARTIK5 evaluation board[2] dts file which includes
> the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
> ethernet port, uart port and so on.
>
> [1] https://www.artik.io/hardware/artik-5
> [2] http://www.digikey.com/product-search/en?FV=ffecca14
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 2 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos3250-artik5-eval.dts | 26 ++
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 334 +++++++++++++++++++++
> 4 files changed, 363 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos3250-artik5-eval.dts
> create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
Otherwise,
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module
2016-03-18 21:01 ` Rob Herring
@ 2016-03-19 11:44 ` Chanwoo Choi
0 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-19 11:44 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozłowski, Kukjin Kim, Sylwester Nawrocki,
Tomasz Figa, jh80.chung, andi.shyti, inki.dae, Seung-Woo Kim,
pankaj.dubey, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
Hi Rob,
On Sat, Mar 19, 2016 at 6:01 AM, Rob Herring <robh@kernel.org> wrote:
> On Tue, Mar 15, 2016 at 04:38:09PM +0900, Chanwoo Choi wrote:
>> This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
>> based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
>
> s/follwoing/following/
I'll fix it.
>
>> - Application Processor (Samsung Exynos3250)
>> - WiFi/BT Combo chip (Broadcom4354)
>> - PMIC (Samsung S2MPS14)
>> - eMMC (4GB)
>> - DRAM LPDDR3 (512MB)
>> - Connectors pin (60 Pins x 3 set)
>>
>> Also, this patch adds the ARTIK5 evaluation board[2] dts file which includes
>> the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
>> ethernet port, uart port and so on.
>>
>> [1] https://www.artik.io/hardware/artik-5
>> [2] http://www.digikey.com/product-search/en?FV=ffecca14
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>> ---
>> .../bindings/arm/samsung/samsung-boards.txt | 2 +
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/exynos3250-artik5-eval.dts | 26 ++
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 334 +++++++++++++++++++++
>> 4 files changed, 363 insertions(+)
>> create mode 100644 arch/arm/boot/dts/exynos3250-artik5-eval.dts
>> create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
>
> Otherwise,
>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks for your review.
Best Regards,
Chanwoo Choi
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 8/8] ARM: dts: Add MSHC2 dt node for SD card for exynos3250-artik5-eval board
2016-03-15 7:38 [PATCH v3 0/8] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file Chanwoo Choi
` (6 preceding siblings ...)
2016-03-15 7:38 ` [PATCH v3 7/8] ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module Chanwoo Choi
@ 2016-03-15 7:38 ` Chanwoo Choi
7 siblings, 0 replies; 20+ messages in thread
From: Chanwoo Choi @ 2016-03-15 7:38 UTC (permalink / raw)
To: k.kozlowski, kgene, s.nawrocki, tomasz.figa
Cc: jh80.chung, andi.shyti, inki.dae, sw0312.kim, pankaj.dubey,
cw00.choi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
devicetree
From: Jaehoon Chung <jh80.chung@samsung.com>
This patch adds MSHC (Mobile Storage Host Controller) dt node for
Exynos3250 SoC. MSHC is an interface between the system and the SD card
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
arch/arm/boot/dts/exynos3250-artik5-eval.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
index b476154590a5..be4d6aa379f3 100644
--- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts
+++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
@@ -21,6 +21,23 @@
"samsung,exynos3250", "samsung,exynos3";
};
+&mshc_2 {
+ num-slots = <1>;
+ cap-sd-highspeed;
+ disable-wp;
+ vqmmc-supply = <&ldo3_reg>;
+ card-detect-delay = <200>;
+ clock-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&serial_2 {
status = "okay";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread