[PATCH v2 0/2] rockchip: power-domain: support qos save and restore

[PATCH v2 0/2] rockchip: power-domain: support qos save and restore

[Elaine Zhang]

add qos document in dt-bingings.
modify power domain driver to support qos save and restore.

Changes in v2:
[PATCH V2 2/2]: add some error handling.
		fix up the define and request space for qos_regmap and qos_save_regs. 

Elaine Zhang (2):
  dt-bindings: modify document of Rockchip power domains
  rockchip: power-domain: support qos save and restore

 .../bindings/soc/rockchip/power_domain.txt         |   8 ++
 drivers/soc/rockchip/pm_domains.c                  | 104 ++++++++++++++++++++-
 2 files changed, 109 insertions(+), 3 deletions(-)

-- 
1.9.1

[PATCH v2 1/2] dt-bindings: modify document of Rockchip power domains

[Elaine Zhang]

Add qos example for power domain which found on Rockchip SoCs.
These qos register description in TRMs
(rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same.

Changes in v2:
	No Changes.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
index 98085c888d65..6c571a40cd31 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -21,6 +21,13 @@ Required properties for power domain sub nodes:
 - clocks (optional): phandles to clocks which need to be enabled while power domain
 	switches state.
 
+Qos Example:
+
+	qos_gpu: qos_gpu@ffaf0000 {
+		compatible ="syscon";
+		reg = <0x0 0xffaf0000 0x0 0x20>;
+	};
+
 Example:
 
 	power: power-controller {
@@ -32,6 +39,7 @@ Example:
 		pd_gpu {
 			reg = <RK3288_PD_GPU>;
 			clocks = <&cru ACLK_GPU>;
+			pm_qos = <&qos_gpu>;
 		};
 	};
 
-- 
1.9.1

Re: [PATCH v2 1/2] dt-bindings: modify document of Rockchip power domains

[Heiko Stübner]

Hi Elaine,

Am Donnerstag, 14. April 2016, 10:10:55 schrieb Elaine Zhang:
> Add qos example for power domain which found on Rockchip SoCs.
> These qos register description in TRMs
> (rk3036, rk3228, rk3288, rk3366, rk3368, rk3399) looks the same.
> 
> Changes in v2:
> 	No Changes.

Changelogs please below the "---" below your Signed-off-by and not as part of 
the commit message.

Also could please check if a commit message like

---- 8< ----
Rockchip SoCs contain quality of service (qos) blocks managing priority, 
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.

These qos blocks also are similar over all currently available Rockchip 
SoCs.
---- 8< ----

works for you? [See replies to your v1 series]

> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---

[changelog here]

>  Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 8
> ++++++++ 1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt index
> 98085c888d65..6c571a40cd31 100644
> --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> @@ -21,6 +21,13 @@ Required properties for power domain sub nodes:
>  - clocks (optional): phandles to clocks which need to be enabled while
> power domain switches state.
> 
> +Qos Example:
> +
> +	qos_gpu: qos_gpu@ffaf0000 {
> +		compatible ="syscon";
> +		reg = <0x0 0xffaf0000 0x0 0x20>;
> +	};
> +
>  Example:
> 
>  	power: power-controller {
> @@ -32,6 +39,7 @@ Example:
>  		pd_gpu {
>  			reg = <RK3288_PD_GPU>;
>  			clocks = <&cru ACLK_GPU>;
> +			pm_qos = <&qos_gpu>;
>  		};
>  	};

[PATCH v2 2/2] rockchip: power-domain: support qos save and restore

[Elaine Zhang]

support qos save and restore when power domain on/off.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/soc/rockchip/pm_domains.c | 104 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 101 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index ac729fe42cc9..58218143da54 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -46,10 +46,20 @@ struct rockchip_pmu_info {
 	const struct rockchip_domain_info *domain_info;
 };
 
+#define MAX_QOS_REGS_NUM	5
+#define QOS_PRIORITY		0x08
+#define QOS_MODE		0x0c
+#define QOS_BANDWIDTH		0x10
+#define QOS_SATURATION		0x14
+#define QOS_EXTCONTROL		0x18
+
 struct rockchip_pm_domain {
 	struct generic_pm_domain genpd;
 	const struct rockchip_domain_info *info;
 	struct rockchip_pmu *pmu;
+	int num_qos;
+	struct regmap **qos_regmap;
+	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
 	int num_clks;
 	struct clk *clks[];
 };
@@ -118,6 +128,55 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 	return 0;
 }
 
+static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
+{
+	int i;
+
+	for (i = 0; i < pd->num_qos; i++) {
+		regmap_read(pd->qos_regmap[i],
+			    QOS_PRIORITY,
+			    &pd->qos_save_regs[0][i]);
+		regmap_read(pd->qos_regmap[i],
+			    QOS_MODE,
+			    &pd->qos_save_regs[1][i]);
+		regmap_read(pd->qos_regmap[i],
+			    QOS_BANDWIDTH,
+			    &pd->qos_save_regs[2][i]);
+		regmap_read(pd->qos_regmap[i],
+			    QOS_SATURATION,
+			    &pd->qos_save_regs[3][i]);
+		regmap_read(pd->qos_regmap[i],
+			    QOS_EXTCONTROL,
+			    &pd->qos_save_regs[4][i]);
+	}
+	return 0;
+}
+
+static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
+{
+	int i;
+
+	for (i = 0; i < pd->num_qos; i++) {
+		regmap_write(pd->qos_regmap[i],
+			     QOS_PRIORITY,
+			     pd->qos_save_regs[0][i]);
+		regmap_write(pd->qos_regmap[i],
+			     QOS_MODE,
+			     pd->qos_save_regs[1][i]);
+		regmap_write(pd->qos_regmap[i],
+			     QOS_BANDWIDTH,
+			     pd->qos_save_regs[2][i]);
+		regmap_write(pd->qos_regmap[i],
+			     QOS_SATURATION,
+			     pd->qos_save_regs[3][i]);
+		regmap_write(pd->qos_regmap[i],
+			     QOS_EXTCONTROL,
+			     pd->qos_save_regs[4][i]);
+	}
+
+	return 0;
+}
+
 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 {
 	struct rockchip_pmu *pmu = pd->pmu;
@@ -161,7 +220,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 			clk_enable(pd->clks[i]);
 
 		if (!power_on) {
-			/* FIXME: add code to save AXI_QOS */
+			rockchip_pmu_save_qos(pd);
 
 			/* if powering down, idle request to NIU first */
 			rockchip_pmu_set_idle_request(pd, true);
@@ -173,7 +232,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 			/* if powering up, leave idle mode */
 			rockchip_pmu_set_idle_request(pd, false);
 
-			/* FIXME: add code to restore AXI_QOS */
+			rockchip_pmu_restore_qos(pd);
 		}
 
 		for (i = pd->num_clks - 1; i >= 0; i--)
@@ -241,9 +300,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 {
 	const struct rockchip_domain_info *pd_info;
 	struct rockchip_pm_domain *pd;
+	struct device_node *qos_node;
 	struct clk *clk;
 	int clk_cnt;
-	int i;
+	int i, j;
 	u32 id;
 	int error;
 
@@ -303,6 +363,44 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 			clk, node->name);
 	}
 
+	pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
+						 NULL);
+
+	if (pd->num_qos < 0) {
+		dev_err(pmu->dev,
+			"the qos node num is error qos_num = %d\n",
+			pd->num_qos);
+		error = pd->num_qos;
+		goto err_out;
+	}
+
+	pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
+				      sizeof(*pd->qos_regmap), GFP_KERNEL);
+	if (!pd->qos_regmap)
+		return -ENOMEM;
+
+	for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
+		pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, pd->num_qos,
+						    sizeof(u32), GFP_KERNEL);
+		if (!pd->qos_save_regs[j])
+			return -ENOMEM;
+	}
+
+	for (j = 0; j < pd->num_qos; j++) {
+		qos_node = of_parse_phandle(node, "pm_qos", j);
+		if (!qos_node) {
+			error = -ENODEV;
+			goto err_out;
+		}
+		pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
+		if (IS_ERR(pd->qos_regmap[j])) {
+			error = -ENODEV;
+			of_node_put(qos_node);
+			goto err_out;
+		}
+		of_node_put(qos_node);
+	}
+
 	error = rockchip_pd_power(pd, true);
 	if (error) {
 		dev_err(pmu->dev,
-- 
1.9.1

[RESEND PATCH v2 0/2] rockchip: power-domain: support qos save and restore

[Elaine Zhang]

add qos document in dt-bingings.
modify power domain driver to support qos save and restore.

Changes in v2:
[PATCH V2 1/2]: fix up the commit message.
[PATCH V2 2/2]: add some error handling.
		fix up the define and request space for qos_regmap and qos_save_regs. 

Elaine Zhang (2):
  dt-bindings: modify document of Rockchip power domains
  rockchip: power-domain: support qos save and restore

 .../bindings/soc/rockchip/power_domain.txt         |   8 ++
 drivers/soc/rockchip/pm_domains.c                  | 104 ++++++++++++++++++++-
 2 files changed, 109 insertions(+), 3 deletions(-)

-- 
1.9.1

[PATCH v2 1/2] dt-bindings: modify document of Rockchip power domains

[Elaine Zhang]

Rockchip Socs contain quality of service (qos) blocks managing priority, 
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.

These qos blocks also are similar over all currently available Rockchip 
SoCs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
index 98085c888d65..6c571a40cd31 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -21,6 +21,13 @@ Required properties for power domain sub nodes:
 - clocks (optional): phandles to clocks which need to be enabled while power domain
 	switches state.
 
+Qos Example:
+
+	qos_gpu: qos_gpu@ffaf0000 {
+		compatible ="syscon";
+		reg = <0x0 0xffaf0000 0x0 0x20>;
+	};
+
 Example:
 
 	power: power-controller {
@@ -32,6 +39,7 @@ Example:
 		pd_gpu {
 			reg = <RK3288_PD_GPU>;
 			clocks = <&cru ACLK_GPU>;
+			pm_qos = <&qos_gpu>;
 		};
 	};
 
-- 
1.9.1