[PATCH 0/2] DRA7x: Increase QSPI frequency to 64MHz

[PATCH 0/2] DRA7x: Increase QSPI frequency to 64MHz

[Vignesh R]

This patch series increases QSPI bus frequency to 64MHz and switch to
SPI mode 0 in order to increase read/write throughput.
First patch removes QSPI pinmux from DT as pinmux can only be done in
U-Boot(see patch commit message for more info). Second patch does the
dts changes to support 64MHz mode 0 operation.


Tested on DRA74 and DRA72 EVM with U-Boot 2016.05-rc1.

Vignesh R (2):
  ARM: dts: dra7x: Remove QSPI pinmux
  ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

 Documentation/devicetree/bindings/spi/ti_qspi.txt |  7 +++++++
 arch/arm/boot/dts/dra7-evm.dts                    | 23 ++---------------------
 arch/arm/boot/dts/dra72-evm.dts                   | 20 ++------------------
 3 files changed, 11 insertions(+), 39 deletions(-)

-- 
2.8.1

[PATCH 1/2] ARM: dts: dra7x: Remove QSPI pinmux

[Vignesh R]

DRA7 family of processors from Texas Instruments, have a hardware module
called IODELAYCONFIG Module which is expected to be configured. This
block allows very specific custom fine tuning for electrical
characteristics of IO pins that are necessary for functionality and
device lifetime requirements. IODelay module has it's own register space
with registers to configure various pins.

According to AM572x TRM SPRUHZ6E October 2014–Revised January 2016[1]
section 18.4.6.1 Pad Configuration, in addition to pinmuxing(MUXMODE),
when operating a pad in certain mode, Virtual/Manual IO Timing Mode must
also be configured to ensure that IO timings are met (DELAYMODE and
MODESELECT fields of pad's IODELAYCONFIG module register). According to
section 18.4.6.1.7 Isolation Requirements of above TRM, when
reprogramming MUXMODE, DELAYMODE, and MODESELECT fields, there is a
potential for a significant glitch on the corresponding IO. It is hence
recommended to do this with I/O isolation (which can only be done in
initial stages of bootloader). QSPI is one such module that requires
IODELAY configuration. So, this patch removes the pinmux for
QSPI for DRA74/DRA72 EVM as it needs to be done in bootloader (U-Boot)
and cannot be done in kernel.

Users should migrate to U-Boot v2016.05-rc1 or higher.

[1] http://www.ti.com/lit/ug/spruhz6e/spruhz6e.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts  | 17 -----------------
 arch/arm/boot/dts/dra72-evm.dts | 14 --------------
 2 files changed, 31 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index d272cf140197..47d0745a08ad 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -226,21 +226,6 @@
 		>;
 	};
 
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
-			DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
-			DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
-			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
-			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
-			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
-			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
-			DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
-			DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
-			DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
-		>;
-	};
-
 	usb1_pins: pinmux_usb1_pins {
                 pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
@@ -678,8 +663,6 @@
 
 &qspi {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
 
 	spi-max-frequency = <48000000>;
 	m25p80@0 {
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 3e63f660cd7c..479b74e1641e 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -247,18 +247,6 @@
 		>;
 	};
 
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1)	/* gpmc_a13.qspi1_rtclk */
-			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)	/* gpmc_a14.qspi1_d3 */
-			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)	/* gpmc_a15.qspi1_d2 */
-			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)	/* gpmc_a16.qspi1_d1 */
-			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)	/* gpmc_a17.qspi1_d0 */
-			DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1)	/* qpmc_a18.qspi1_sclk */
-			DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1)	/* gpmc_cs2.qspi1_cs0 */
-		>;
-	};
-
 	hdmi_pins: pinmux_hdmi_pins {
 		pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
@@ -715,8 +703,6 @@
 
 &qspi {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
 
 	spi-max-frequency = <48000000>;
 	m25p80@0 {
-- 
2.8.1

[PATCH 2/2] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

[Vignesh R]

According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/spi/ti_qspi.txt | 7 +++++++
 arch/arm/boot/dts/dra7-evm.dts                    | 6 ++----
 arch/arm/boot/dts/dra72-evm.dts                   | 6 ++----
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index cc8304aa64ac..50b14f6b53a3 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -19,6 +19,13 @@ Optional properties:
 - syscon-chipselects: Handle to system control region contains QSPI
 		      chipselect register and offset of that register.
 
+NOTE: TI QSPI controller requires different pinmux and IODelay
+paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
+the bootloader (U-Boot). Default configuration only supports Mode-0
+operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
+specified in the slave nodes of TI QSPI controller without appropriate
+modification to bootloader.
+
 Example:
 
 For am4372:
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 47d0745a08ad..507a8ec0a268 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -664,15 +664,13 @@
 &qspi {
 	status = "okay";
 
-	spi-max-frequency = <48000000>;
+	spi-max-frequency = <64000000>;
 	m25p80@0 {
 		compatible = "s25fl256s1";
-		spi-max-frequency = <48000000>;
+		spi-max-frequency = <64000000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 479b74e1641e..46e1b72866f5 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -704,15 +704,13 @@
 &qspi {
 	status = "okay";
 
-	spi-max-frequency = <48000000>;
+	spi-max-frequency = <64000000>;
 	m25p80@0 {
 		compatible = "s25fl256s1";
-		spi-max-frequency = <48000000>;
+		spi-max-frequency = <64000000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-- 
2.8.1

Re: [PATCH 2/2] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

[Rob Herring]

On Thu, Apr 14, 2016 at 03:48:21PM +0530, Vignesh R wrote:
> According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
> DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
> MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
> throughput.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/spi/ti_qspi.txt | 7 +++++++
>  arch/arm/boot/dts/dra7-evm.dts                    | 6 ++----
>  arch/arm/boot/dts/dra72-evm.dts                   | 6 ++----
>  3 files changed, 11 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
> index cc8304aa64ac..50b14f6b53a3 100644
> --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
> +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
> @@ -19,6 +19,13 @@ Optional properties:
>  - syscon-chipselects: Handle to system control region contains QSPI
>  		      chipselect register and offset of that register.
>  
> +NOTE: TI QSPI controller requires different pinmux and IODelay
> +paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
> +the bootloader (U-Boot). Default configuration only supports Mode-0
> +operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
> +specified in the slave nodes of TI QSPI controller without appropriate
> +modification to bootloader.

But these properties are properties of what the slave device supports, 
right? I don't see how you can change them based on the controller.

Rob

Re: [PATCH 2/2] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

[R, Vignesh]

On 04/14/2016 10:42 PM, Rob Herring wrote:
> On Thu, Apr 14, 2016 at 03:48:21PM +0530, Vignesh R wrote:
>> According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
>> DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
>> MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
>> throughput.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/spi/ti_qspi.txt | 7 +++++++
>>  arch/arm/boot/dts/dra7-evm.dts                    | 6 ++----
>>  arch/arm/boot/dts/dra72-evm.dts                   | 6 ++----
>>  3 files changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
>> index cc8304aa64ac..50b14f6b53a3 100644
>> --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
>> +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
>> @@ -19,6 +19,13 @@ Optional properties:
>>  - syscon-chipselects: Handle to system control region contains QSPI
>>  		      chipselect register and offset of that register.
>>  
>> +NOTE: TI QSPI controller requires different pinmux and IODelay
>> +paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
>> +the bootloader (U-Boot). Default configuration only supports Mode-0
>> +operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
>> +specified in the slave nodes of TI QSPI controller without appropriate
>> +modification to bootloader.
> 
> But these properties are properties of what the slave device supports, 
> right? I don't see how you can change them based on the controller.

Yeah, although these are properties of slave device, they indicate what
clock phase and clock polarity(mode) should the controller use to
communicate with slave. AFAIK, most slave normally support Mode 0 and
Mode 3 operation. If "spi-cpol" and "spi-cpha" are defined then
communication is Mode 3 else (if both properties are absent) its Mode 0.
SPI controller driver then uses the appropriate clock polarity and clock
phase.
Depending on controller capabilities, slave capabilities and board
specific constraints either Mode 0 or Mode 3 is chosen(not both).
The above NOTE is to indicate that its _not possible_ to use spi slave
that strictly require mode-3(indicated by defining "spi-cpol" and
"spi-cpha" DT properties) with ti-qspi controller without appropriate
modification to bootloader. In other words Mode-3 slaves are not
supported by TI QSPI driver with upstream U-Boot.

-- 
Regards
Vignesh