[PATCH 0/2] sunxi factors clock predivider handling

[PATCH 0/2] sunxi factors clock predivider handling

[Vishnu Patekar]

For allwinner A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.

Currently, it's being handled in clock specific functions. 

A83t ahb1 and a31 ahb1 are similar clocks except a83t parent index 0b10 and 0b11
are pll6/prediv and a31 ahb1 parent index 0x11 is pll6/prediv.
with only this change, code duplication was needed.

To handle this, this patch adds predivider table with parent index, prediv 
shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic factors
recalc. clock specific recalc was currently used only by a31 ahb1.

For getter, it differentiates parents with prediv, with non-zero prediv width.

I've tested this patch on a83t bpi-m3 board. I do not have a31 device.
a83t changes are not included in this patch, It'll be included in separate patch.

Vishnu Patekar (2):
  clk: sunxi: add predivider handling for factors clock
  clk: sunxi: add prediv table for a31 ahb1 clock

 drivers/clk/sunxi/clk-factors.c | 31 +++++++++++++++----------------
 drivers/clk/sunxi/clk-factors.h | 10 +++++++++-
 drivers/clk/sunxi/clk-sunxi.c   | 31 +++++++++----------------------
 3 files changed, 33 insertions(+), 39 deletions(-)

-- 
1.9.1

[PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Vishnu Patekar]

For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
To handle this, this patch adds predivider table with parent index,
prediv shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic
factors recalc.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 drivers/clk/sunxi/clk-factors.c | 31 +++++++++++++++----------------
 drivers/clk/sunxi/clk-factors.h | 10 +++++++++-
 2 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index ddefe96..8f3b637 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -45,10 +45,12 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
 					     unsigned long parent_rate)
 {
 	u8 n = 1, k = 0, p = 0, m = 0;
+	u8 par_index = 0;
 	u32 reg;
 	unsigned long rate;
 	struct clk_factors *factors = to_clk_factors(hw);
 	const struct clk_factors_config *config = factors->config;
+	const struct clk_factors_prediv *prediv = factors->prediv_config;
 
 	/* Fetch the register value */
 	reg = readl(factors->reg);
@@ -63,24 +65,16 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
 	if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
 		p = FACTOR_GET(config->pshift, config->pwidth, reg);
 
-	if (factors->recalc) {
-		struct factors_request factors_req = {
-			.parent_rate = parent_rate,
-			.n = n,
-			.k = k,
-			.m = m,
-			.p = p,
-		};
-
+	if (prediv) {
 		/* get mux details from mux clk structure */
 		if (factors->mux)
-			factors_req.parent_index =
-				(reg >> factors->mux->shift) &
-				factors->mux->mask;
-
-		factors->recalc(&factors_req);
+			par_index = (reg >> factors->mux->shift) &
+					factors->mux->mask;
 
-		return factors_req.rate;
+		if (prediv[par_index].width != SUNXI_FACTORS_NOT_APPLICABLE) {
+			m = FACTOR_GET(prediv[par_index].shift,
+				prediv[par_index].width, reg);
+		}
 	}
 
 	/* Calculate the rate */
@@ -102,8 +96,12 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
 	for (i = 0; i < num_parents; i++) {
 		struct factors_request factors_req = {
 			.rate = req->rate,
-			.parent_index = i,
 		};
+
+		if (factors->prediv_config)
+			factors_req.prediv_width =
+						factors->prediv_config[i].width;
+
 		parent = clk_hw_get_parent_by_index(hw, i);
 		if (!parent)
 			continue;
@@ -211,6 +209,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
 	/* set up factors properties */
 	factors->reg = reg;
 	factors->config = data->table;
+	factors->prediv_config = data->prediv_table;
 	factors->get_factors = data->getter;
 	factors->recalc = data->recalc;
 	factors->lock = lock;
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 1e63c5b..b1b7745 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -18,10 +18,16 @@ struct clk_factors_config {
 	u8 n_start;
 };
 
+struct clk_factors_prediv {
+	u8 parent_index;
+	u8 shift;
+	u8 width;
+};
+
 struct factors_request {
 	unsigned long rate;
 	unsigned long parent_rate;
-	u8 parent_index;
+	u8 prediv_width;
 	u8 n;
 	u8 k;
 	u8 m;
@@ -33,6 +39,7 @@ struct factors_data {
 	int mux;
 	int muxmask;
 	const struct clk_factors_config *table;
+	const struct clk_factors_prediv *prediv_table;
 	void (*getter)(struct factors_request *req);
 	void (*recalc)(struct factors_request *req);
 	const char *name;
@@ -42,6 +49,7 @@ struct clk_factors {
 	struct clk_hw hw;
 	void __iomem *reg;
 	const struct clk_factors_config *config;
+	const struct clk_factors_prediv *prediv_config;
 	void (*get_factors)(struct factors_request *req);
 	void (*recalc)(struct factors_request *req);
 	spinlock_t *lock;
-- 
1.9.1

[PATCH 2/2] clk: sunxi: add prediv table for a31 ahb1 clock

[Vishnu Patekar]

For ahb1 clock, move mshift and mwidth to parent specific width and shift.
getter differentiates parents with prediv, with non-zero prediv width.

Also, removed unused ahb1 recalc function, it's now handled in generic
factors recalc.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 drivers/clk/sunxi/clk-sunxi.c | 31 +++++++++----------------------
 1 file changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 91de0a0..5a5f26b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -282,8 +282,6 @@ static void sun5i_a13_get_ahb_factors(struct factors_request *req)
 	req->p = div;
 }
 
-#define SUN6I_AHB1_PARENT_PLL6	3
-
 /**
  * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
  * AHB rate is calculated as follows
@@ -307,7 +305,7 @@ static void sun6i_get_ahb1_factors(struct factors_request *req)
 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
 
 	/* calculate pre-divider if parent is pll6 */
-	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
+	if (req->prediv_width) {
 		if (div < 4)
 			calcp = 0;
 		else if (div / 2 < 4)
@@ -329,22 +327,6 @@ static void sun6i_get_ahb1_factors(struct factors_request *req)
 }
 
 /**
- * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
- *			 parent index
- */
-static void sun6i_ahb1_recalc(struct factors_request *req)
-{
-	req->rate = req->parent_rate;
-
-	/* apply pre-divider first if parent is pll6 */
-	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
-		req->rate /= req->m + 1;
-
-	/* clk divider */
-	req->rate >>= req->p;
-}
-
-/**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);
@@ -474,12 +456,17 @@ static const struct clk_factors_config sun5i_a13_ahb_config = {
 };
 
 static const struct clk_factors_config sun6i_ahb1_config = {
-	.mshift = 6,
-	.mwidth = 2,
 	.pshift = 4,
 	.pwidth = 2,
 };
 
+static const struct clk_factors_prediv sun6i_ahb1_prediv[] = {
+	{.parent_index = 0, .shift = 0, .width = 0 },	/* LOSC  */
+	{.parent_index = 1, .shift = 0, .width = 0 },	/* OSC24MHz */
+	{.parent_index = 2, .shift = 0, .width = 0 },	/* AXI */
+	{.parent_index = 3, .shift = 6, .width = 2 }	/* PLL6/Pre_div */
+};
+
 static const struct clk_factors_config sun4i_apb1_config = {
 	.mshift = 0,
 	.mwidth = 5,
@@ -551,8 +538,8 @@ static const struct factors_data sun6i_ahb1_data __initconst = {
 	.mux = 12,
 	.muxmask = BIT(1) | BIT(0),
 	.table = &sun6i_ahb1_config,
+	.prediv_table = sun6i_ahb1_prediv,
 	.getter = sun6i_get_ahb1_factors,
-	.recalc = sun6i_ahb1_recalc,
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {
-- 
1.9.1

Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[kbuild test robot]

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Hi Vishnu,

[auto build test ERROR on clk/clk-next]
[also build test ERROR on v4.6-rc3 next-20160415]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-sunxi_defconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

Note: the linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801 HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

   drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
>> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request' has no member named 'parent_index'
     if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
            ^
   drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
   drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request' has no member named 'parent_index'
     if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
            ^

vim +310 drivers/clk/sunxi/clk-sunxi.c

a78bb355 Chen-Yu Tsai 2016-01-25  304  	if (req->parent_rate && req->rate > req->parent_rate)
a78bb355 Chen-Yu Tsai 2016-01-25  305  		req->rate = req->parent_rate;
a78bb355 Chen-Yu Tsai 2016-01-25  306  
a78bb355 Chen-Yu Tsai 2016-01-25  307  	div = DIV_ROUND_UP(req->parent_rate, req->rate);
a78bb355 Chen-Yu Tsai 2016-01-25  308  
a78bb355 Chen-Yu Tsai 2016-01-25  309  	/* calculate pre-divider if parent is pll6 */
a78bb355 Chen-Yu Tsai 2016-01-25 @310  	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
a78bb355 Chen-Yu Tsai 2016-01-25  311  		if (div < 4)
a78bb355 Chen-Yu Tsai 2016-01-25  312  			calcp = 0;
a78bb355 Chen-Yu Tsai 2016-01-25  313  		else if (div / 2 < 4)

:::::: The code at line 310 was first introduced by commit
:::::: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc

:::::: TO: Chen-Yu Tsai <wens@csie.org>
:::::: CC: Maxime Ripard <maxime.ripard@free-electrons.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Philip Li]

On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote:
> Both of these patches in series has to be applied at the same time.
> I think this is the reason, it fails.

hi Xiaolong, would you help do a check whether we apply the patches in correct sequence for this case?


> On 17 Apr 2016 09:26, "kbuild test robot" <lkp@intel.com> wrote:
> 
> > Hi Vishnu,
> >
> > [auto build test ERROR on clk/clk-next]
> > [also build test ERROR on v4.6-rc3 next-20160415]
> > [if your patch is applied to the wrong git tree, please drop us a note to
> > help improving the system]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
> > base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
> > clk-next
> > config: arm-sunxi_defconfig (attached as .config)
> > reproduce:
> >         wget
> > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
> > -O ~/bin/make.cross
> >         chmod +x ~/bin/make.cross
> >         # save the attached .config to linux build tree
> >         make.cross ARCH=arm
> >
> > Note: the
> > linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
> > HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
> >       It only hurts bisectibility.
> >
> > All errors (new ones prefixed by >>):
> >
> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
> > >> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request'
> > has no member named 'parent_index'
> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
> >             ^
> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
> >    drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request'
> > has no member named 'parent_index'
> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
> >             ^
> >
> > vim +310 drivers/clk/sunxi/clk-sunxi.c
> >
> > a78bb355 Chen-Yu Tsai 2016-01-25  304   if (req->parent_rate && req->rate
> > > req->parent_rate)
> > a78bb355 Chen-Yu Tsai 2016-01-25  305           req->rate =
> > req->parent_rate;
> > a78bb355 Chen-Yu Tsai 2016-01-25  306
> > a78bb355 Chen-Yu Tsai 2016-01-25  307   div =
> > DIV_ROUND_UP(req->parent_rate, req->rate);
> > a78bb355 Chen-Yu Tsai 2016-01-25  308
> > a78bb355 Chen-Yu Tsai 2016-01-25  309   /* calculate pre-divider if parent
> > is pll6 */
> > a78bb355 Chen-Yu Tsai 2016-01-25 @310   if (req->parent_index ==
> > SUN6I_AHB1_PARENT_PLL6) {
> > a78bb355 Chen-Yu Tsai 2016-01-25  311           if (div < 4)
> > a78bb355 Chen-Yu Tsai 2016-01-25  312                   calcp = 0;
> > a78bb355 Chen-Yu Tsai 2016-01-25  313           else if (div / 2 < 4)
> >
> > :::::: The code at line 310 was first introduced by commit
> > :::::: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite
> > sun6i-a31-ahb1-clk using factors clk with custom recalc
> >
> > :::::: TO: Chen-Yu Tsai <wens@csie.org>
> > :::::: CC: Maxime Ripard <maxime.ripard@free-electrons.com>
> >
> > ---
> > 0-DAY kernel test infrastructure                Open Source Technology
> > Center
> > https://lists.01.org/pipermail/kbuild-all                   Intel
> > Corporation
> >

Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Chen-Yu Tsai]

On Tue, Apr 19, 2016 at 6:22 PM, Philip Li <philip.li@intel.com> wrote:
> On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote:
>> Both of these patches in series has to be applied at the same time.
>> I think this is the reason, it fails.

You should probably squash the second patch into the first.

ChenYu

> hi Xiaolong, would you help do a check whether we apply the patches in correct sequence for this case?
>
>
>> On 17 Apr 2016 09:26, "kbuild test robot" <lkp@intel.com> wrote:
>>
>> > Hi Vishnu,
>> >
>> > [auto build test ERROR on clk/clk-next]
>> > [also build test ERROR on v4.6-rc3 next-20160415]
>> > [if your patch is applied to the wrong git tree, please drop us a note to
>> > help improving the system]
>> >
>> > url:
>> > https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>> > base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
>> > clk-next
>> > config: arm-sunxi_defconfig (attached as .config)
>> > reproduce:
>> >         wget
>> > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>> > -O ~/bin/make.cross
>> >         chmod +x ~/bin/make.cross
>> >         # save the attached .config to linux build tree
>> >         make.cross ARCH=arm
>> >
>> > Note: the
>> > linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>> > HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
>> >       It only hurts bisectibility.
>> >
>> > All errors (new ones prefixed by >>):
>> >
>> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
>> > >> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request'
>> > has no member named 'parent_index'
>> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
>> >             ^
>> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
>> >    drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request'
>> > has no member named 'parent_index'
>> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
>> >             ^
>> >
>> > vim +310 drivers/clk/sunxi/clk-sunxi.c
>> >
>> > a78bb355 Chen-Yu Tsai 2016-01-25  304   if (req->parent_rate && req->rate
>> > > req->parent_rate)
>> > a78bb355 Chen-Yu Tsai 2016-01-25  305           req->rate =
>> > req->parent_rate;
>> > a78bb355 Chen-Yu Tsai 2016-01-25  306
>> > a78bb355 Chen-Yu Tsai 2016-01-25  307   div =
>> > DIV_ROUND_UP(req->parent_rate, req->rate);
>> > a78bb355 Chen-Yu Tsai 2016-01-25  308
>> > a78bb355 Chen-Yu Tsai 2016-01-25  309   /* calculate pre-divider if parent
>> > is pll6 */
>> > a78bb355 Chen-Yu Tsai 2016-01-25 @310   if (req->parent_index ==
>> > SUN6I_AHB1_PARENT_PLL6) {
>> > a78bb355 Chen-Yu Tsai 2016-01-25  311           if (div < 4)
>> > a78bb355 Chen-Yu Tsai 2016-01-25  312                   calcp = 0;
>> > a78bb355 Chen-Yu Tsai 2016-01-25  313           else if (div / 2 < 4)
>> >
>> > :::::: The code at line 310 was first introduced by commit
>> > :::::: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite
>> > sun6i-a31-ahb1-clk using factors clk with custom recalc
>> >
>> > :::::: TO: Chen-Yu Tsai <wens@csie.org>
>> > :::::: CC: Maxime Ripard <maxime.ripard@free-electrons.com>
>> >
>> > ---
>> > 0-DAY kernel test infrastructure                Open Source Technology
>> > Center
>> > https://lists.01.org/pipermail/kbuild-all                   Intel
>> > Corporation
>> >

Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

[Vishnu Patekar]

Hello Wens,

On Tue, Apr 19, 2016 at 10:16 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Apr 19, 2016 at 6:22 PM, Philip Li <philip.li@intel.com> wrote:
>> On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote:
>>> Both of these patches in series has to be applied at the same time.
>>> I think this is the reason, it fails.
>
> You should probably squash the second patch into the first.
Yes, I should have, I'll send v2 by combining both patches into one.
>
> ChenYu
>
>> hi Xiaolong, would you help do a check whether we apply the patches in correct sequence for this case?
>>
>>
>>> On 17 Apr 2016 09:26, "kbuild test robot" <lkp@intel.com> wrote:
>>>
>>> > Hi Vishnu,
>>> >
>>> > [auto build test ERROR on clk/clk-next]
>>> > [also build test ERROR on v4.6-rc3 next-20160415]
>>> > [if your patch is applied to the wrong git tree, please drop us a note to
>>> > help improving the system]
>>> >
>>> > url:
>>> > https://github.com/0day-ci/linux/commits/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>>> > base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
>>> > clk-next
>>> > config: arm-sunxi_defconfig (attached as .config)
>>> > reproduce:
>>> >         wget
>>> > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>>> > -O ~/bin/make.cross
>>> >         chmod +x ~/bin/make.cross
>>> >         # save the attached .config to linux build tree
>>> >         make.cross ARCH=arm
>>> >
>>> > Note: the
>>> > linux-review/Vishnu-Patekar/sunxi-factors-clock-predivider-handling/20160417-025801
>>> > HEAD 19bb5fc952754381d9f4f9b2e57a1fa09f467359 builds fine.
>>> >       It only hurts bisectibility.
>>> >
>>> > All errors (new ones prefixed by >>):
>>> >
>>> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_get_ahb1_factors':
>>> > >> drivers/clk/sunxi/clk-sunxi.c:310:9: error: 'struct factors_request'
>>> > has no member named 'parent_index'
>>> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
>>> >             ^
>>> >    drivers/clk/sunxi/clk-sunxi.c: In function 'sun6i_ahb1_recalc':
>>> >    drivers/clk/sunxi/clk-sunxi.c:340:9: error: 'struct factors_request'
>>> > has no member named 'parent_index'
>>> >      if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
>>> >             ^
>>> >
>>> > vim +310 drivers/clk/sunxi/clk-sunxi.c
>>> >
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  304   if (req->parent_rate && req->rate
>>> > > req->parent_rate)
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  305           req->rate =
>>> > req->parent_rate;
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  306
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  307   div =
>>> > DIV_ROUND_UP(req->parent_rate, req->rate);
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  308
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  309   /* calculate pre-divider if parent
>>> > is pll6 */
>>> > a78bb355 Chen-Yu Tsai 2016-01-25 @310   if (req->parent_index ==
>>> > SUN6I_AHB1_PARENT_PLL6) {
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  311           if (div < 4)
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  312                   calcp = 0;
>>> > a78bb355 Chen-Yu Tsai 2016-01-25  313           else if (div / 2 < 4)
>>> >
>>> > :::::: The code at line 310 was first introduced by commit
>>> > :::::: a78bb35552a800949b2bf68f372d3d6ccabdd790 clk: sunxi: rewrite
>>> > sun6i-a31-ahb1-clk using factors clk with custom recalc
>>> >
>>> > :::::: TO: Chen-Yu Tsai <wens@csie.org>
>>> > :::::: CC: Maxime Ripard <maxime.ripard@free-electrons.com>
>>> >
>>> > ---
>>> > 0-DAY kernel test infrastructure                Open Source Technology
>>> > Center
>>> > https://lists.01.org/pipermail/kbuild-all                   Intel
>>> > Corporation
>>> >