[PATCH 0/6] soc/tegra: Add support for IO pads control via pinctrl interface

[PATCH 0/6] soc/tegra: Add support for IO pads control via pinctrl interface

[Laxman Dewangan]

The IO pins of Tegra SoCs are grouped for common control of IO
interface like setting voltage signal levels and power state of
the interface. The group is generally referred as IO pads. The 
power state and voltage control of IO pins can be done at IO pads
level.

Before Tegra210, the voltage level of IO rails are auto detected and
configure IO pads accordingly but on T210, it is require to set
explicitly by SW.

This series:
- add public APIs from Tegra PMC interface for io pads control
  for power state and voltage levels.
- Add pincontrol driver to use these APIs to configure the IO
  pads voltage and power state.

---
Changes from V1: 
- Use pinconfig generic property for power enable/disable.
- Rename power-source-voltage properties.
- Make all register read/write value to u32.
- Add IO pads macros and APIs which is nearest definiton of HW blocks.

Laxman Dewangan (6):
  soc/tegra: pmc: Use BIT macro for register field definition
  soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()
  soc/tegra: pmc: Add support for IO pads power state and voltage
  soc/tegra: pmc: Register PMC child devices as platform device
  pinctrl: tegra: Add DT binding for io pads control
  pinctrl: tegra: Add driver to configure voltage and power state of io
    pads

 .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    |  88 ++++++
 drivers/pinctrl/tegra/Makefile                     |   1 +
 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c    | 301 +++++++++++++++++++++
 drivers/soc/tegra/pmc.c                            | 284 +++++++++++++++++--
 .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  |  20 ++
 include/soc/tegra/pmc.h                            |  87 ++++++
 6 files changed, 757 insertions(+), 24 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h

-- 
2.1.4

[PATCH 1/6] soc/tegra: pmc: Use BIT macro for register field definition

[Laxman Dewangan]

Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
- Remove the indenting of line which is not for BIT macro usage.
---
 drivers/soc/tegra/pmc.c | 40 ++++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index bb17345..2c3f1f9 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -45,28 +45,28 @@
 #include <soc/tegra/pmc.h>
 
 #define PMC_CNTRL			0x0
-#define  PMC_CNTRL_SYSCLK_POLARITY	(1 << 10)  /* sys clk polarity */
-#define  PMC_CNTRL_SYSCLK_OE		(1 << 11)  /* system clock enable */
-#define  PMC_CNTRL_SIDE_EFFECT_LP0	(1 << 14)  /* LP0 when CPU pwr gated */
-#define  PMC_CNTRL_CPU_PWRREQ_POLARITY	(1 << 15)  /* CPU pwr req polarity */
-#define  PMC_CNTRL_CPU_PWRREQ_OE	(1 << 16)  /* CPU pwr req enable */
-#define  PMC_CNTRL_INTR_POLARITY	(1 << 17)  /* inverts INTR polarity */
+#define PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
+#define PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
+#define PMC_CNTRL_SIDE_EFFECT_LP0	BIT(14) /* LP0 when CPU pwr gated */
+#define PMC_CNTRL_CPU_PWRREQ_POLARITY	BIT(15) /* CPU pwr req polarity */
+#define PMC_CNTRL_CPU_PWRREQ_OE		BIT(16) /* CPU pwr req enable */
+#define PMC_CNTRL_INTR_POLARITY		BIT(17)/* inverts INTR polarity */
 
 #define DPD_SAMPLE			0x020
-#define  DPD_SAMPLE_ENABLE		(1 << 0)
-#define  DPD_SAMPLE_DISABLE		(0 << 0)
+#define DPD_SAMPLE_ENABLE		BIT(0)
+#define DPD_SAMPLE_DISABLE		(0 << 0)
 
 #define PWRGATE_TOGGLE			0x30
-#define  PWRGATE_TOGGLE_START		(1 << 8)
+#define PWRGATE_TOGGLE_START		BIT(8)
 
 #define REMOVE_CLAMPING			0x34
 
 #define PWRGATE_STATUS			0x38
 
 #define PMC_SCRATCH0			0x50
-#define  PMC_SCRATCH0_MODE_RECOVERY	(1 << 31)
-#define  PMC_SCRATCH0_MODE_BOOTLOADER	(1 << 30)
-#define  PMC_SCRATCH0_MODE_RCM		(1 << 1)
+#define PMC_SCRATCH0_MODE_RECOVERY	BIT(31)
+#define PMC_SCRATCH0_MODE_BOOTLOADER	BIT(30)
+#define PMC_SCRATCH0_MODE_RCM		BIT(1)
 #define  PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \
 					 PMC_SCRATCH0_MODE_BOOTLOADER | \
 					 PMC_SCRATCH0_MODE_RCM)
@@ -77,14 +77,14 @@
 #define PMC_SCRATCH41			0x140
 
 #define PMC_SENSOR_CTRL			0x1b0
-#define PMC_SENSOR_CTRL_SCRATCH_WRITE	(1 << 2)
-#define PMC_SENSOR_CTRL_ENABLE_RST	(1 << 1)
+#define PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
+#define PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
 
 #define IO_DPD_REQ			0x1b8
-#define  IO_DPD_REQ_CODE_IDLE		(0 << 30)
-#define  IO_DPD_REQ_CODE_OFF		(1 << 30)
-#define  IO_DPD_REQ_CODE_ON		(2 << 30)
-#define  IO_DPD_REQ_CODE_MASK		(3 << 30)
+#define IO_DPD_REQ_CODE_IDLE		(0 << 30)
+#define IO_DPD_REQ_CODE_OFF		(1U << 30)
+#define IO_DPD_REQ_CODE_ON		(2U << 30)
+#define IO_DPD_REQ_CODE_MASK		(3U << 30)
 
 #define IO_DPD_STATUS			0x1bc
 #define IO_DPD2_REQ			0x1c0
@@ -96,10 +96,10 @@
 #define PMC_SCRATCH54_ADDR_SHIFT	0
 
 #define PMC_SCRATCH55			0x25c
-#define PMC_SCRATCH55_RESET_TEGRA	(1 << 31)
+#define PMC_SCRATCH55_RESET_TEGRA	BIT(31)
 #define PMC_SCRATCH55_CNTRL_ID_SHIFT	27
 #define PMC_SCRATCH55_PINMUX_SHIFT	24
-#define PMC_SCRATCH55_16BITOP		(1 << 15)
+#define PMC_SCRATCH55_16BITOP		BIT(15)
 #define PMC_SCRATCH55_CHECKSUM_SHIFT	16
 #define PMC_SCRATCH55_I2CSLV1_SHIFT	0
 
-- 
2.1.4

[PATCH 2/6] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()

[Laxman Dewangan]

The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
-This is new in series as per discussion on V1 series to use u32 for
tegra_pmc_readl.
---
 drivers/soc/tegra/pmc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 2c3f1f9..fc4f7b2 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -878,7 +878,7 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
 			      unsigned long val, unsigned long timeout)
 {
-	unsigned long value;
+	u32 value;
 
 	timeout = jiffies + msecs_to_jiffies(timeout);
 
@@ -900,8 +900,9 @@ static void tegra_io_rail_unprepare(void)
 
 int tegra_io_rail_power_on(unsigned int id)
 {
-	unsigned long request, status, value;
+	unsigned long request, status;
 	unsigned int bit, mask;
+	u32 value;
 	int err;
 
 	mutex_lock(&pmc->powergates_lock);
@@ -935,8 +936,9 @@ EXPORT_SYMBOL(tegra_io_rail_power_on);
 
 int tegra_io_rail_power_off(unsigned int id)
 {
-	unsigned long request, status, value;
+	unsigned long request, status;
 	unsigned int bit, mask;
+	u32 value;
 	int err;
 
 	mutex_lock(&pmc->powergates_lock);
-- 
2.1.4

[PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Laxman Dewangan]

The IO pins of Tegra SoCs are grouped for common control of IO
interface like setting voltage signal levels and power state of
the interface. The group is generally referred as IO pads. The
power state and voltage control of IO pins can be done at IO pads
level.

Tegra generation SoC supports the power down of IO pads when it
is not used even in the active state of system. This saves power
from that IO interface.

Tegra generation SoC supports multiple voltage level in IO pins for
interfacing on some of pads. Till Tegra124, the IO rail voltage was
detected automatically and IO pads power voltage level sets accordingly.
But from Tegra210, it is required to program by SW explicitly.

Add support to set the power states and voltage level of the IO pads
from client driver. The implementation for the APIs are in generic
which is applicable for all generation os Tegra SoC.

IO pads ID and information of bit field for power state and voltage
level controls are added for Tegra210.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
This is reworked on earlier path to have separation between IO rails and
io pads and add power state and voltage control APIs in single call.
---
 drivers/soc/tegra/pmc.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++-
 include/soc/tegra/pmc.h |  87 +++++++++++++++++++++++
 2 files changed, 268 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index fc4f7b2..b3be4b9 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -76,6 +76,10 @@
 
 #define PMC_SCRATCH41			0x140
 
+/* Power detect for pad voltage */
+#define PMC_PWR_DET			0x48
+#define PMC_PWR_DET_VAL			0xe4
+
 #define PMC_SENSOR_CTRL			0x1b0
 #define PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
 #define PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
@@ -115,12 +119,19 @@ struct tegra_powergate {
 	unsigned int num_resets;
 };
 
+struct tegra_io_pads_control {
+	int pad_id;
+	int dpd_bit_pos;
+	int pwr_val_pos;
+};
+
 struct tegra_pmc_soc {
 	unsigned int num_powergates;
 	const char *const *powergates;
 	unsigned int num_cpu_powergates;
 	const u8 *cpu_powergates;
-
+	const struct tegra_io_pads_control *io_pads_control;
+	unsigned int num_io_pads;
 	bool has_tsense_reset;
 	bool has_gpu_clamps;
 };
@@ -196,6 +207,14 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
 	writel(value, pmc->base + offset);
 }
 
+static void tegra_pmc_read_modify_write(unsigned long offset, u32 mask, u32 val)
+{
+	u32 pmc_reg = tegra_pmc_readl(offset);
+
+	pmc_reg = (pmc_reg & ~mask) | (val & mask);
+	tegra_pmc_writel(pmc_reg, offset);
+}
+
 static inline bool tegra_powergate_state(int id)
 {
 	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
@@ -970,6 +989,165 @@ error:
 }
 EXPORT_SYMBOL(tegra_io_rail_power_off);
 
+#define TEGRA_IO_PADS_CONTROL(_pad, _dpd, _pwr)		\
+{							\
+	.pad_id = (TEGRA_IO_PAD_##_pad),		\
+	.dpd_bit_pos = (_dpd),				\
+	.pwr_val_pos = (_pwr),				\
+}
+
+struct tegra_io_pads_control tegra210_io_pads_control[] = {
+	TEGRA_IO_PADS_CONTROL(CSIA, 0, -1),
+	TEGRA_IO_PADS_CONTROL(CSIB, 1, -1),
+	TEGRA_IO_PADS_CONTROL(DSI, 2, -1),
+	TEGRA_IO_PADS_CONTROL(MIPI_BIAS, 3, -1),
+	TEGRA_IO_PADS_CONTROL(PEX_BIAS, 4, -1),
+	TEGRA_IO_PADS_CONTROL(PEX_CLK1, 5, -1),
+	TEGRA_IO_PADS_CONTROL(PEX_CLK2, 6, -1),
+	TEGRA_IO_PADS_CONTROL(USB0, 9, -1),
+	TEGRA_IO_PADS_CONTROL(USB1, 10, -1),
+	TEGRA_IO_PADS_CONTROL(USB2, 11, -1),
+	TEGRA_IO_PADS_CONTROL(USB_BIAS, 12, -1),
+	TEGRA_IO_PADS_CONTROL(UART, 14, -1),
+	TEGRA_IO_PADS_CONTROL(AUDIO, 17, -1),
+	TEGRA_IO_PADS_CONTROL(USB3, 18, -1),
+	TEGRA_IO_PADS_CONTROL(HSIC, 19, -1),
+	TEGRA_IO_PADS_CONTROL(DBG, 25, -1),
+	TEGRA_IO_PADS_CONTROL(DEBUG_NONAO, 26, -1),
+	TEGRA_IO_PADS_CONTROL(GPIO, 27, 21),
+	TEGRA_IO_PADS_CONTROL(HDMI, 28, -1),
+	TEGRA_IO_PADS_CONTROL(SDMMC1, 33, 12),
+	TEGRA_IO_PADS_CONTROL(SDMMC3, 34, 13),
+	TEGRA_IO_PADS_CONTROL(EMMC, 35, -1),
+	TEGRA_IO_PADS_CONTROL(CAM, 36, -1),
+	TEGRA_IO_PADS_CONTROL(EMMC2, 37, -1),
+	TEGRA_IO_PADS_CONTROL(DSIB, 39, -1),
+	TEGRA_IO_PADS_CONTROL(DSIC, 40, -1),
+	TEGRA_IO_PADS_CONTROL(DSID, 41, -1),
+	TEGRA_IO_PADS_CONTROL(CSIC, 42, -1),
+	TEGRA_IO_PADS_CONTROL(CSID, 43, -1),
+	TEGRA_IO_PADS_CONTROL(CSIE, 44, -1),
+	TEGRA_IO_PADS_CONTROL(CSIF, 45, -1),
+	TEGRA_IO_PADS_CONTROL(SPI, 46, -1),
+	TEGRA_IO_PADS_CONTROL(SPI_HV, 47, 23),
+	TEGRA_IO_PADS_CONTROL(DMIC, 50, -1),
+	TEGRA_IO_PADS_CONTROL(DP, 51, -1),
+	TEGRA_IO_PADS_CONTROL(LVDS, 57, -1),
+	TEGRA_IO_PADS_CONTROL(AUDIO_HV, 61, 18),
+};
+
+static int tegra_io_pads_to_dpd(const struct tegra_pmc_soc *soc, int pad_id)
+{
+	int i;
+
+	if (!soc || !soc->num_io_pads)
+		return -EINVAL;
+
+	for (i = 0; i < soc->num_io_pads; ++i) {
+		if (soc->io_pads_control[i].pad_id == pad_id)
+			return soc->io_pads_control[i].dpd_bit_pos;
+	}
+
+	return -EINVAL;
+}
+
+static int tegra_io_pads_to_power_val(const struct tegra_pmc_soc *soc,
+				      int pad_id)
+{
+	int i;
+
+	if (!soc || !soc->num_io_pads)
+		return -EINVAL;
+
+	for (i = 0; i < soc->num_io_pads; ++i) {
+		if (soc->io_pads_control[i].pad_id == pad_id)
+			return soc->io_pads_control[i].pwr_val_pos;
+	}
+
+	return -EINVAL;
+}
+
+int tegra_io_pads_power_enable(int io_pad_id)
+{
+	int dpd_bit;
+
+	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
+	if (dpd_bit < 0)
+		return dpd_bit;
+
+	return tegra_io_rail_power_on(dpd_bit);
+}
+EXPORT_SYMBOL(tegra_io_pads_power_enable);
+
+int tegra_io_pads_power_disable(int io_pad_id)
+{
+	int dpd_bit;
+
+	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
+	if (dpd_bit < 0)
+		return dpd_bit;
+
+	return tegra_io_rail_power_off(dpd_bit);
+}
+EXPORT_SYMBOL(tegra_io_pads_power_disable);
+
+int tegra_io_pads_power_is_enabled(int io_pad_id)
+{
+	unsigned long status_reg;
+	u32 status;
+	int dpd_bit;
+
+	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
+	if (dpd_bit < 0)
+		return dpd_bit;
+
+	status_reg = (dpd_bit < 32) ? IO_DPD_STATUS : IO_DPD2_STATUS;
+	status = tegra_pmc_readl(status_reg);
+
+	return !!(status & BIT(dpd_bit % 32));
+}
+EXPORT_SYMBOL(tegra_io_pads_power_is_enabled);
+
+int tegra_io_pads_configure_voltage(int io_pad_id, int io_volt_uv)
+{
+	int pwr_bit;
+	u32 bval;
+
+	if ((io_volt_uv != 3300000) && (io_volt_uv != 1800000))
+		return -EINVAL;
+
+	pwr_bit = tegra_io_pads_to_power_val(pmc->soc, io_pad_id);
+	if (pwr_bit < 0)
+		return pwr_bit;
+
+	bval = (io_volt_uv == 3300000) ? BIT(pwr_bit) : 0;
+
+	mutex_lock(&pmc->powergates_lock);
+	tegra_pmc_read_modify_write(PMC_PWR_DET, BIT(pwr_bit), BIT(pwr_bit));
+	tegra_pmc_read_modify_write(PMC_PWR_DET_VAL, BIT(pwr_bit), bval);
+	mutex_unlock(&pmc->powergates_lock);
+
+	usleep_range(100, 250);
+
+	return 0;
+}
+EXPORT_SYMBOL(tegra_io_pads_configure_voltage);
+
+int tegra_io_pads_get_configured_voltage(int io_pad_id)
+{
+	int pwr_bit;
+	u32 pwr_det_val;
+
+	pwr_bit = tegra_io_pads_to_power_val(pmc->soc, io_pad_id);
+	if (pwr_bit < 0)
+		return pwr_bit;
+
+	pwr_det_val = tegra_pmc_readl(PMC_PWR_DET_VAL);
+
+	return (pwr_det_val & BIT(pwr_bit)) ? 3300000 : 1800000;
+}
+EXPORT_SYMBOL(tegra_io_pads_get_configured_voltage);
+
 #ifdef CONFIG_PM_SLEEP
 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
 {
@@ -1443,6 +1621,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.powergates = tegra210_powergates,
 	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
 	.cpu_powergates = tegra210_cpu_powergates,
+	.io_pads_control = tegra210_io_pads_control,
+	.num_io_pads = ARRAY_SIZE(tegra210_io_pads_control),
 	.has_tsense_reset = true,
 	.has_gpu_clamps = true,
 };
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index e9e5347..79e38f5 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -108,6 +108,58 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
 #define TEGRA_IO_RAIL_LVDS	57
 #define TEGRA_IO_RAIL_SYS_DDC	58
 
+/* TEGRA_IO_PAD: The IO pins of Tegra SoCs are grouped for common control
+ * of IO interface like setting voltage signal levels, power state of the
+ * interface. The group is generally referred as io-pads. The power and
+ * voltage control of IO pins are available at io-pads level.
+ * The following macros make the super list all IO pads found on Tegra SoC
+ * generations.
+ */
+#define TEGRA_IO_PAD_AUDIO		0
+#define TEGRA_IO_PAD_AUDIO_HV		1
+#define TEGRA_IO_PAD_BB			2
+#define TEGRA_IO_PAD_CAM		3
+#define TEGRA_IO_PAD_COMP		4
+#define TEGRA_IO_PAD_CSIA		5
+#define TEGRA_IO_PAD_CSIB		6
+#define TEGRA_IO_PAD_CSIC		7
+#define TEGRA_IO_PAD_CSID		8
+#define TEGRA_IO_PAD_CSIE		9
+#define TEGRA_IO_PAD_CSIF		10
+#define TEGRA_IO_PAD_DBG		11
+#define TEGRA_IO_PAD_DEBUG_NONAO	12
+#define TEGRA_IO_PAD_DMIC		13
+#define TEGRA_IO_PAD_DP			14
+#define TEGRA_IO_PAD_DSI		15
+#define TEGRA_IO_PAD_DSIB		16
+#define TEGRA_IO_PAD_DSIC		17
+#define TEGRA_IO_PAD_DSID		18
+#define TEGRA_IO_PAD_EMMC		19
+#define TEGRA_IO_PAD_EMMC2		20
+#define TEGRA_IO_PAD_GPIO		21
+#define TEGRA_IO_PAD_HDMI		22
+#define TEGRA_IO_PAD_HSIC		23
+#define TEGRA_IO_PAD_HV			24
+#define TEGRA_IO_PAD_LVDS		25
+#define TEGRA_IO_PAD_MIPI_BIAS		26
+#define TEGRA_IO_PAD_NAND		27
+#define TEGRA_IO_PAD_PEX_BIAS		28
+#define TEGRA_IO_PAD_PEX_CLK1		29
+#define TEGRA_IO_PAD_PEX_CLK2		30
+#define TEGRA_IO_PAD_PEX_CNTRL		31
+#define TEGRA_IO_PAD_SDMMC1		32
+#define TEGRA_IO_PAD_SDMMC3		33
+#define TEGRA_IO_PAD_SDMMC4		34
+#define TEGRA_IO_PAD_SPI		35
+#define TEGRA_IO_PAD_SPI_HV		36
+#define TEGRA_IO_PAD_SYS_DDC		37
+#define TEGRA_IO_PAD_UART		38
+#define TEGRA_IO_PAD_USB0		39
+#define TEGRA_IO_PAD_USB1		40
+#define TEGRA_IO_PAD_USB2		41
+#define TEGRA_IO_PAD_USB3		42
+#define TEGRA_IO_PAD_USB_BIAS		43
+
 #ifdef CONFIG_ARCH_TEGRA
 int tegra_powergate_is_powered(unsigned int id);
 int tegra_powergate_power_on(unsigned int id);
@@ -120,6 +172,16 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 
 int tegra_io_rail_power_on(unsigned int id);
 int tegra_io_rail_power_off(unsigned int id);
+
+/* Power enable/disable of the IO pads */
+int tegra_io_pads_power_enable(int io_pad_id);
+int tegra_io_pads_power_disable(int io_pad_id);
+int tegra_io_pads_power_is_enabled(int io_pad_id);
+
+/* Set/Get of IO pad voltage */
+int tegra_io_pads_configure_voltage(int io_pad_id, int io_volt_uv);
+int tegra_io_pads_get_configured_voltage(int io_pad_id);
+
 #else
 static inline int tegra_powergate_is_powered(unsigned int id)
 {
@@ -157,6 +219,31 @@ static inline int tegra_io_rail_power_off(unsigned int id)
 {
 	return -ENOSYS;
 }
+
+static inline int tegra_io_pads_power_enable(int io_pad_id)
+{
+	return -ENOTSUPP;
+}
+
+static inline int tegra_io_pads_power_disable(int io_pad_id)
+{
+	return -ENOTSUPP;
+}
+
+static inline int tegra_io_pads_power_is_enabled(int io_pad_id)
+{
+	return -ENOTSUPP;
+}
+
+static inline int tegra_io_pads_configure_voltage(int io_pad_id, int io_volt_uv)
+{
+	return -ENOTSUPP;
+}
+
+static inline int tegra_io_pads_get_configured_voltage(int io_pad_id)
+{
+	return -ENOTSUPP;
+}
 #endif /* CONFIG_ARCH_TEGRA */
 
 #endif /* __SOC_TEGRA_PMC_H__ */
-- 
2.1.4

[PATCH 4/6] soc/tegra: pmc: Register PMC child devices as platform device

[Laxman Dewangan]

Power Management Controller(PMC) of Tegra does the multiple chip
power related functionality for internal and IO interfacing.
Some of the functionalities are power gating of IP blocks, IO pads
voltage and power state configuration, system power state configurations,
wakeup controls etc.

Different functionalities of the PMC are provided through different
framework like IO pads control can be provided through pinctrl framework,
IO power control is via misc driver etc. All sub functionalities are
represented as PMC child devices.

Register the PMC child devices as platform device and fill the child
devices table for Tegra210.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
Reworked on DT for having flat entry and register all child devices
as simple platform device instead of of_populate_device().
---
 drivers/soc/tegra/pmc.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index b3be4b9..625167e 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -132,6 +132,8 @@ struct tegra_pmc_soc {
 	const u8 *cpu_powergates;
 	const struct tegra_io_pads_control *io_pads_control;
 	unsigned int num_io_pads;
+	const char **sub_devs_name;
+	unsigned int num_sub_devs;
 	bool has_tsense_reset;
 	bool has_gpu_clamps;
 };
@@ -158,6 +160,8 @@ struct tegra_pmc_soc {
  * @lp0_vec_size: size of the LP0 warm boot code
  * @powergates_available: Bitmap of available power gates
  * @powergates_lock: mutex for power gate register access
+ * @pdevs: Platform device for PMC child devices.
+ * @num_pdevs: Number of platform devices.
  */
 struct tegra_pmc {
 	struct device *dev;
@@ -184,6 +188,9 @@ struct tegra_pmc {
 	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
 
 	struct mutex powergates_lock;
+
+	struct platform_device **pdevs;
+	unsigned int num_pdevs;
 };
 
 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
@@ -1379,6 +1386,43 @@ out:
 	of_node_put(np);
 }
 
+static int  tegra_pmc_init_sub_devs(struct tegra_pmc *pmc)
+{
+	int ret, i;
+
+	if (!pmc->soc->num_sub_devs)
+		return 0;
+
+	pmc->pdevs = devm_kzalloc(pmc->dev, sizeof(**pmc->pdevs), GFP_KERNEL);
+	if (!pmc->pdevs)
+		return -ENOMEM;
+
+	for (i = 0; i < pmc->soc->num_sub_devs; ++i) {
+		pmc->pdevs[i] = platform_device_register_data(pmc->dev,
+						pmc->soc->sub_devs_name[i],
+						0, NULL, 0);
+		if (IS_ERR(pmc->pdevs[i])) {
+			ret = PTR_ERR(pmc->pdevs[i]);
+			dev_err(pmc->dev,
+				"Failed to register platform device for %s: %d\n",
+				pmc->soc->sub_devs_name[i], ret);
+			goto pdev_cleanups;
+		}
+		pmc->num_pdevs++;
+	}
+
+	return 0;
+
+pdev_cleanups:
+	for (i = pmc->num_pdevs; i > 0; i--) {
+		platform_device_unregister(pmc->pdevs[i - 1]);
+		pmc->pdevs[i - 1] = NULL;
+	}
+	pmc->num_pdevs = 0;
+
+	return ret;
+}
+
 static int tegra_pmc_probe(struct platform_device *pdev)
 {
 	void __iomem *base;
@@ -1408,6 +1452,10 @@ static int tegra_pmc_probe(struct platform_device *pdev)
 
 	tegra_pmc_init_tsense_reset(pmc);
 
+	err = tegra_pmc_init_sub_devs(pmc);
+	if (err < 0)
+		dev_warn(pmc->dev, "Failed to register sub devices: %d\n", err);
+
 	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 		err = tegra_powergate_debugfs_init();
 		if (err < 0)
@@ -1616,6 +1664,10 @@ static const u8 tegra210_cpu_powergates[] = {
 	TEGRA_POWERGATE_CPU3,
 };
 
+static const char *tegra210_sub_devs_name[] = {
+	"pinctrl-tegra210-io-pad",
+};
+
 static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.num_powergates = ARRAY_SIZE(tegra210_powergates),
 	.powergates = tegra210_powergates,
@@ -1623,6 +1675,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.cpu_powergates = tegra210_cpu_powergates,
 	.io_pads_control = tegra210_io_pads_control,
 	.num_io_pads = ARRAY_SIZE(tegra210_io_pads_control),
+	.sub_devs_name = tegra210_sub_devs_name,
+	.num_sub_devs = ARRAY_SIZE(tegra210_sub_devs_name),
 	.has_tsense_reset = true,
 	.has_gpu_clamps = true,
 };
-- 
2.1.4

[PATCH 5/6] pinctrl: tegra: Add DT binding for io pads control

[Laxman Dewangan]

NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also IO pads can be configured for
power down state if it is not in used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.

Add DT binding document for detailing the DT properties for
configuring IO pads voltage levels and its power state.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
- Reworked on DT properties to use generic pinconf DT. Also add macros
for voltage support. Now all DT properties are in flat DT instead of
sub node based.
---
 .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 88 ++++++++++++++++++++++
 .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  | 20 +++++
 2 files changed, 108 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
new file mode 100644
index 0000000..7616380
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
@@ -0,0 +1,88 @@
+NVIDIA Tegra210 PMC IO pad controller
+
+NVIDIA Tegra210 supports IO pads which can operate at 1.8V or 3.3V I/O
+power rail source. SW needs to configure the voltage level of IO pads
+based on platform specific power tree.
+
+The voltage configurations of IO pads should be done in boot if it is not
+going to change other wise dynamically based on IO rail voltage on that
+IO pads.
+
+The DT property of the io pads must be under the node of pmc i.e.
+pmc@7000e400 for Tegra210.
+
+Please refer to <pinctrl-bindings.txt> in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for an
+IO pads, or a list of IO pads. This configuration can include the voltage and
+power enable/disable control
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content. Each subnode only affects those
+parameters that are explicitly listed. Unspecified is represented as an absent
+property,
+
+See the TRM to determine which properties and values apply to each IO pads.
+Macro values for property values are defined in
+<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+
+The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
+	For 1.8V, use TEGRA_IO_PAD_POWER_SOURCE_1800000UV
+	For 3.3V, use TEGRA_IO_PAD_POWER_SOURCE_3300000UV
+
+Required subnode-properties:
+==========================
+- pins : An array of strings. Each string contains the name of an IO pads. Valid
+	 values for these names are listed below.
+
+Optional subnode-properties:
+==========================
+-nvidia,power-source-voltage:	Integer. The voltage level of IO pads. The
+				valid values are 1.8V and 3.3V. Macros are
+				defined for these voltage levels in
+				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+				Use TEGRA_IO_PAD_POWER_SOURCE_1800000UV for 1.8V
+				Use TEGRA_IO_PAD_POWER_SOURCE_3300000UV for 3.3V
+
+				All IO pads do not support the 1.8V/3.3V
+				configurations. Valid values for "pins" are
+				audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv.
+
+Other than above, following properties are supported from generic pin
+configuration explained in <dt-bindings/pinctrl/pinctrl-binding.txt>.
+low-power-enable:		enable low power mode.
+low-power-disable:		disable low power mode.
+
+Valid values for pin for low power mode supports are:
+	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
+	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
+	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
+	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
+	usb1, usb2, usb3.
+
+Example:
+	#include <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+	pmc@7000e400 {
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tegra_io_pad_volt_default>;
+		tegra_io_pad_volt_default: common {
+			audio-hv {
+				pins = "audio-hv";
+				nvidia,power-source-voltage = <TEGRA_IO_PAD_POWER_SOURCE_3300000UV>;
+			};
+
+			gpio {
+				pins = "gpio";
+				invidia,power-source-voltage = <TEGRA_IO_PAD_POWER_SOURCE_1800000UV>;
+			};
+
+			audio {
+				pins = "audio", "dmic", "sdmmc1", "sdmmc3";
+				low-power-enable;
+			};
+		};
+	};
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h b/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
new file mode 100644
index 0000000..77fd448
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
@@ -0,0 +1,20 @@
+/*
+ * This header provides constants for Tegra210 IO pads pinctrl bindings.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA210_IO_PAD_H
+#define _DT_BINDINGS_PINCTRL_TEGRA210_IO_PAD_H
+
+/* Power source voltage for Tegra IO Pad. */
+#define TEGRA_IO_PAD_POWER_SOURCE_1800000UV		0
+#define TEGRA_IO_PAD_POWER_SOURCE_3300000UV		1
+
+#endif
-- 
2.1.4

[PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Laxman Dewangan]

NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also the IO pads can be configured
for power down state if it is not used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.

The voltage and power state configurations of pads are provided
through pin control frameworks. Add pin control driver for Tegra's
IO pads' voltage and power state configurations.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

---
Changes from V1:
- Use the generic pincontrol property for low power enable/disable.
- sync with latest and remove all MODULE* macros
- Use renamed APIs form PMC
---
 drivers/pinctrl/tegra/Makefile                  |   1 +
 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c | 301 ++++++++++++++++++++++++
 2 files changed, 302 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c

diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile
index a927379..8c4519f 100644
--- a/drivers/pinctrl/tegra/Makefile
+++ b/drivers/pinctrl/tegra/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_PINCTRL_TEGRA30)		+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_TEGRA114)		+= pinctrl-tegra114.o
 obj-$(CONFIG_PINCTRL_TEGRA124)		+= pinctrl-tegra124.o
 obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
+obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210-io-pad.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
new file mode 100644
index 0000000..ab06c71
--- /dev/null
+++ b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
@@ -0,0 +1,301 @@
+/*
+ * Generic ADC thermal driver
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <soc/tegra/pmc.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+
+enum tegra_io_rail_pads_params {
+	TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE = PIN_CONFIG_END + 1,
+};
+
+static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
+	{
+		.property = "nvidia,power-source-voltage",
+		.param = TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE,
+	},
+};
+
+struct tegra_io_pads_cfg_info {
+	const char *name;
+	const unsigned int pins[1];
+	int pad_id;
+	bool voltage_can_change;
+	bool support_low_power_state;
+};
+
+#define TEGRA210_PAD_INFO_TABLE(_entry_)			\
+	_entry_(0, "audio", AUDIO, true, false),		\
+	_entry_(1, "audio-hv", AUDIO_HV, true, true),		\
+	_entry_(2, "cam", CAM, true, false),			\
+	_entry_(3, "csia", CSIA, true, false),			\
+	_entry_(4, "csib", CSIB, true, false),			\
+	_entry_(5, "csic", CSIC, true, false),			\
+	_entry_(6, "csid", CSID, true, false),			\
+	_entry_(7, "csie", CSIE, true, false),			\
+	_entry_(8, "csif", CSIF, true, false),			\
+	_entry_(9, "dbg", DBG, true, false),			\
+	_entry_(10, "debug-nonao", DEBUG_NONAO, true, false),	\
+	_entry_(11, "dmic", DMIC, true, false),			\
+	_entry_(12, "dp", DP, true, false),			\
+	_entry_(13, "dsi", DSI, true, false),			\
+	_entry_(14, "dsib", DSIB, true, false),			\
+	_entry_(15, "dsic", DSIC, true, false),			\
+	_entry_(16, "dsid", DSID, true, false),			\
+	_entry_(17, "emmc", SDMMC4, true, false),		\
+	_entry_(18, "emmc2", EMMC2, true, false),		\
+	_entry_(19, "gpio", GPIO, true, true),			\
+	_entry_(20, "hdmi", HDMI, true, false),			\
+	_entry_(21, "hsic", HSIC, true, false),			\
+	_entry_(22, "lvds", LVDS, true, false),			\
+	_entry_(23, "mipi-bias", MIPI_BIAS, true, false),	\
+	_entry_(24, "pex-bias", PEX_BIAS, true, false),		\
+	_entry_(25, "pex-clk1", PEX_CLK1, true, false),		\
+	_entry_(26, "pex-clk2", PEX_CLK2, true, false),		\
+	_entry_(27, "pex-ctrl", PEX_CNTRL, true, false),	\
+	_entry_(28, "sdmmc1", SDMMC1, true, true),		\
+	_entry_(29, "sdmmc3", SDMMC3, true, true),		\
+	_entry_(30, "spi", SPI, true, false),			\
+	_entry_(31, "spi-hv", SPI_HV, true, true),		\
+	_entry_(32, "uart", UART, true, false),			\
+	_entry_(33, "usb-bias", USB_BIAS, true, false),		\
+	_entry_(34, "usb0", USB0, true, false),			\
+	_entry_(35, "usb1", USB1, true, false),			\
+	_entry_(36, "usb2", USB2, true, false),			\
+	_entry_(37, "usb3", USB3, true, false)
+
+#define TEGRA_IO_PAD_INFO(_id, _name, _pad_id, _vchange, _lpstate)	\
+	{								\
+		.name = _name,						\
+		.pins = {(_id)},					\
+		.pad_id = TEGRA_IO_PAD_##_pad_id,			\
+		.voltage_can_change = (_vchange),			\
+		.support_low_power_state = (_lpstate),			\
+	}
+
+static struct tegra_io_pads_cfg_info tegra210_io_pads_cfg_info[] = {
+	TEGRA210_PAD_INFO_TABLE(TEGRA_IO_PAD_INFO),
+};
+
+#define TEGRA_IO_PAD_DESC(_id, _name, _pad_id,  _vchange, _lpstate)	\
+	PINCTRL_PIN(_id, _name)
+
+static const struct pinctrl_pin_desc tegra210_io_pads_pinctrl_desc[] = {
+	TEGRA210_PAD_INFO_TABLE(TEGRA_IO_PAD_DESC),
+};
+
+struct tegra_io_pads_info {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+	struct tegra_io_pads_cfg_info *pads_cfg;
+	unsigned int num_pads_cfg;
+};
+
+static int tegra_iop_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	return tiopi->num_pads_cfg;
+}
+
+static const char *tegra_iop_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+						    unsigned int group)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	return tiopi->pads_cfg[group].name;
+}
+
+static int tegra_iop_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+					    unsigned int group,
+					    const unsigned int **pins,
+					    unsigned int *num_pins)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	*pins = tiopi->pads_cfg[group].pins;
+	*num_pins = 1;
+
+	return 0;
+}
+
+static const struct pinctrl_ops tegra_iop_pinctrl_ops = {
+	.get_groups_count = tegra_iop_pinctrl_get_groups_count,
+	.get_group_name = tegra_iop_pinctrl_get_group_name,
+	.get_group_pins = tegra_iop_pinctrl_get_group_pins,
+	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+	.dt_free_map = pinctrl_utils_free_map,
+};
+
+static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctldev,
+				    unsigned int pin, unsigned long *config)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+	int param = pinconf_to_config_param(*config);
+	struct tegra_io_pads_cfg_info *pad_cfg = &tiopi->pads_cfg[pin];
+	int pad_id = pad_cfg->pad_id;
+	int arg = 0;
+	int ret;
+
+	switch (param) {
+	case TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE:
+		ret = tegra_io_pads_get_configured_voltage(pad_id);
+		if (ret < 0)
+			return ret;
+		arg = (ret =  3300000) ? 1 : 0;
+		break;
+
+	case PIN_CONFIG_LOW_POWER_MODE:
+		ret = tegra_io_pads_power_is_enabled(pad_id);
+		if (ret < 0)
+			return ret;
+		arg = !ret;
+		break;
+
+	default:
+		dev_err(tiopi->dev, "The parameter %d not supported\n", param);
+		return -EINVAL;
+	}
+
+	*config = pinconf_to_config_packed(param, (u16)arg);
+	return 0;
+}
+
+static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctldev,
+				    unsigned int pin, unsigned long *configs,
+				    unsigned int num_configs)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+	struct tegra_io_pads_cfg_info *pad_cfg = &tiopi->pads_cfg[pin];
+	u16 param_val;
+	int pad_id = pad_cfg->pad_id;
+	int volt;
+	int param;
+	int ret;
+	int i;
+
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		param_val = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+		case TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE:
+			volt = (param_val) ? 3300000 : 1800000;
+			ret = tegra_io_pads_configure_voltage(pad_id, volt);
+			if (ret < 0) {
+				dev_err(tiopi->dev,
+					"Failed to configure pad %s for voltage %d: %d\n",
+					pad_cfg->name, param_val, ret);
+				return ret;
+			}
+			break;
+
+		case PIN_CONFIG_LOW_POWER_MODE:
+			if (param_val)
+				ret = tegra_io_pads_power_disable(pad_id);
+			else
+				ret = tegra_io_pads_power_enable(pad_id);
+			if (ret < 0) {
+				dev_err(tiopi->dev,
+					"Failed to set low power %s of pad %s: %d\n",
+					param_val ? "enable" : "disable",
+					pad_cfg->name, ret);
+				return ret;
+			}
+			break;
+
+		default:
+			dev_err(tiopi->dev, "The parameter %d not supported\n",
+				param);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
+	.pin_config_get = tegra_io_pad_pinconf_get,
+	.pin_config_set = tegra_io_pad_pinconf_set,
+};
+
+static struct pinctrl_desc tegra_iop_pinctrl_desc = {
+	.name = "pinctrl-tegra-io-pads",
+	.pctlops = &tegra_iop_pinctrl_ops,
+	.confops = &tegra_io_pad_pinconf_ops,
+	.pins = tegra210_io_pads_pinctrl_desc,
+	.npins = ARRAY_SIZE(tegra210_io_pads_pinctrl_desc),
+	.custom_params = tegra_io_pads_cfg_params,
+	.num_custom_params = ARRAY_SIZE(tegra_io_pads_cfg_params),
+};
+
+static int tegra_iop_pinctrl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np_parent = pdev->dev.parent->of_node;
+	struct tegra_io_pads_info *tiopi;
+
+	if (!np_parent) {
+		dev_err(&pdev->dev, "PMC should be register from DT\n");
+		return -ENODEV;
+	}
+
+	pdev->dev.of_node = np_parent;
+
+	tiopi = devm_kzalloc(&pdev->dev, sizeof(*tiopi), GFP_KERNEL);
+	if (!tiopi)
+		return -ENOMEM;
+
+	tiopi->dev = &pdev->dev;
+	tiopi->dev->of_node = pdev->dev.of_node;
+	tiopi->pads_cfg = tegra210_io_pads_cfg_info;
+	tiopi->num_pads_cfg = ARRAY_SIZE(tegra210_io_pads_cfg_info);
+
+	platform_set_drvdata(pdev, tiopi);
+
+	tiopi->pctl = pinctrl_register(&tegra_iop_pinctrl_desc, dev, tiopi);
+	if (IS_ERR(tiopi->pctl)) {
+		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+		return PTR_ERR(tiopi->pctl);
+	}
+
+	return 0;
+}
+
+static int tegra_iop_pinctrl_remove(struct platform_device *pdev)
+{
+	struct tegra_io_pads_info *tiopi = platform_get_drvdata(pdev);
+
+	pinctrl_unregister(tiopi->pctl);
+
+	return 0;
+}
+
+static struct platform_driver tegra_iop_pinctrl_driver = {
+	.driver = {
+		.name = "pinctrl-tegra210-io-pad",
+	},
+	.probe = tegra_iop_pinctrl_probe,
+	.remove = tegra_iop_pinctrl_remove,
+};
+
+builtin_platform_driver(tegra_iop_pinctrl_driver);
-- 
2.1.4

Re: [PATCH 0/6] soc/tegra: Add support for IO pads control via pinctrl interface

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The 
> power state and voltage control of IO pins can be done at IO pads
> level.
> 
> Before Tegra210, the voltage level of IO rails are auto detected and
> configure IO pads accordingly but on T210, it is require to set
> explicitly by SW.
> 
> This series:
> - add public APIs from Tegra PMC interface for io pads control
>   for power state and voltage levels.
> - Add pincontrol driver to use these APIs to configure the IO
>   pads voltage and power state.
> 
> ---
> Changes from V1: 
> - Use pinconfig generic property for power enable/disable.
> - Rename power-source-voltage properties.
> - Make all register read/write value to u32.
> - Add IO pads macros and APIs which is nearest definiton of HW blocks.

Nit ... if this is a V2 it should be stated in the subject.

Jon

Re: [PATCH 2/6] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> The function tegra_pmc_readl() returns the u32 type data and hence
> change the data type of variable where this data is stored to u32
> type.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> -This is new in series as per discussion on V1 series to use u32 for
> tegra_pmc_readl.
> ---
>  drivers/soc/tegra/pmc.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 2c3f1f9..fc4f7b2 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -878,7 +878,7 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
>  static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
>  			      unsigned long val, unsigned long timeout)
>  {
> -	unsigned long value;
> +	u32 value;

You also need to make mask and val a u32.

Jon

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Laxman Dewangan]

On Tuesday 03 May 2016 06:04 PM, Jon Hunter wrote:
> On 02/05/16 13:17, Laxman Dewangan wrote:
>> +
>> +	return tegra_io_rail_power_on(dpd_bit);
>  From a readability standpoint the above seems weird because
> tegra_io_pads_power_enable() takes an ID as the argument, translates it
> to a bit value and passes it to tegra_io_rail_power_on() which also
> takes an ID for the argument.

Yaah, I did not want to duplicate the implementation and hence it is there.
We will get rid of the older APIs once this is IN and new mechanism there.



>> +
>> +	bval = (io_volt_uv == 3300000) ? BIT(pwr_bit) : 0;
>> +
>> +	mutex_lock(&pmc->powergates_lock);
>> +	tegra_pmc_read_modify_write(PMC_PWR_DET, BIT(pwr_bit), BIT(pwr_bit));
>> +	tegra_pmc_read_modify_write(PMC_PWR_DET_VAL, BIT(pwr_bit), bval);
>> +	mutex_unlock(&pmc->powergates_lock);
> There are 4 instances of BIT(pwr_bit). May be we should do this once or
> have tegra_io_pads_to_power_val() return the bit?

OK, will re-write this part.


>
>> +int tegra_io_pads_power_disable(int io_pad_id);
>> +int tegra_io_pads_power_is_enabled(int io_pad_id);
> What I don't like here, is now we have two public APIs to do the same
> job because tegra_io_pads_power_enable/disable() calls
> tegra_io_rail_power_off/on() internally. Furthermore, the two APIs use
> different ID definitions to accomplish the same job. This shouldn't be
> necessary.

Currently SOR driver is using the tegra_io_rail_power_off/on() APIs. 
Once the proper interface available then I will move sor driver to use 
new method and then we can full get rid of older APIs and macros.

Till that, we need to have this.

>

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> The IO pins of Tegra SoCs are grouped for common control of IO
> interface like setting voltage signal levels and power state of
> the interface. The group is generally referred as IO pads. The
> power state and voltage control of IO pins can be done at IO pads
> level.
> 
> Tegra generation SoC supports the power down of IO pads when it
> is not used even in the active state of system. This saves power
> from that IO interface.
> 
> Tegra generation SoC supports multiple voltage level in IO pins for
> interfacing on some of pads. Till Tegra124, the IO rail voltage was
> detected automatically and IO pads power voltage level sets accordingly.
> But from Tegra210, it is required to program by SW explicitly.
> 
> Add support to set the power states and voltage level of the IO pads
> from client driver. The implementation for the APIs are in generic
> which is applicable for all generation os Tegra SoC.
> 
> IO pads ID and information of bit field for power state and voltage
> level controls are added for Tegra210.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> This is reworked on earlier path to have separation between IO rails and
> io pads and add power state and voltage control APIs in single call.
> ---
>  drivers/soc/tegra/pmc.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++-
>  include/soc/tegra/pmc.h |  87 +++++++++++++++++++++++
>  2 files changed, 268 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index fc4f7b2..b3be4b9 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -76,6 +76,10 @@
>  
>  #define PMC_SCRATCH41			0x140
>  
> +/* Power detect for pad voltage */
> +#define PMC_PWR_DET			0x48
> +#define PMC_PWR_DET_VAL			0xe4
> +
>  #define PMC_SENSOR_CTRL			0x1b0
>  #define PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>  #define PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
> @@ -115,12 +119,19 @@ struct tegra_powergate {
>  	unsigned int num_resets;
>  };
>  
> +struct tegra_io_pads_control {
> +	int pad_id;
> +	int dpd_bit_pos;
> +	int pwr_val_pos;
> +};
> +
>  struct tegra_pmc_soc {
>  	unsigned int num_powergates;
>  	const char *const *powergates;
>  	unsigned int num_cpu_powergates;
>  	const u8 *cpu_powergates;
> -
> +	const struct tegra_io_pads_control *io_pads_control;
> +	unsigned int num_io_pads;
>  	bool has_tsense_reset;
>  	bool has_gpu_clamps;
>  };
> @@ -196,6 +207,14 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
>  	writel(value, pmc->base + offset);
>  }
>  
> +static void tegra_pmc_read_modify_write(unsigned long offset, u32 mask, u32 val)
> +{
> +	u32 pmc_reg = tegra_pmc_readl(offset);
> +
> +	pmc_reg = (pmc_reg & ~mask) | (val & mask);
> +	tegra_pmc_writel(pmc_reg, offset);
> +}
> +
>  static inline bool tegra_powergate_state(int id)
>  {
>  	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
> @@ -970,6 +989,165 @@ error:
>  }
>  EXPORT_SYMBOL(tegra_io_rail_power_off);
>  
> +#define TEGRA_IO_PADS_CONTROL(_pad, _dpd, _pwr)		\
> +{							\
> +	.pad_id = (TEGRA_IO_PAD_##_pad),		\
> +	.dpd_bit_pos = (_dpd),				\
> +	.pwr_val_pos = (_pwr),				\
> +}
> +
> +struct tegra_io_pads_control tegra210_io_pads_control[] = {
> +	TEGRA_IO_PADS_CONTROL(CSIA, 0, -1),
> +	TEGRA_IO_PADS_CONTROL(CSIB, 1, -1),
> +	TEGRA_IO_PADS_CONTROL(DSI, 2, -1),
> +	TEGRA_IO_PADS_CONTROL(MIPI_BIAS, 3, -1),
> +	TEGRA_IO_PADS_CONTROL(PEX_BIAS, 4, -1),
> +	TEGRA_IO_PADS_CONTROL(PEX_CLK1, 5, -1),
> +	TEGRA_IO_PADS_CONTROL(PEX_CLK2, 6, -1),
> +	TEGRA_IO_PADS_CONTROL(USB0, 9, -1),
> +	TEGRA_IO_PADS_CONTROL(USB1, 10, -1),
> +	TEGRA_IO_PADS_CONTROL(USB2, 11, -1),
> +	TEGRA_IO_PADS_CONTROL(USB_BIAS, 12, -1),
> +	TEGRA_IO_PADS_CONTROL(UART, 14, -1),
> +	TEGRA_IO_PADS_CONTROL(AUDIO, 17, -1),
> +	TEGRA_IO_PADS_CONTROL(USB3, 18, -1),
> +	TEGRA_IO_PADS_CONTROL(HSIC, 19, -1),
> +	TEGRA_IO_PADS_CONTROL(DBG, 25, -1),
> +	TEGRA_IO_PADS_CONTROL(DEBUG_NONAO, 26, -1),
> +	TEGRA_IO_PADS_CONTROL(GPIO, 27, 21),
> +	TEGRA_IO_PADS_CONTROL(HDMI, 28, -1),
> +	TEGRA_IO_PADS_CONTROL(SDMMC1, 33, 12),
> +	TEGRA_IO_PADS_CONTROL(SDMMC3, 34, 13),
> +	TEGRA_IO_PADS_CONTROL(EMMC, 35, -1),
> +	TEGRA_IO_PADS_CONTROL(CAM, 36, -1),
> +	TEGRA_IO_PADS_CONTROL(EMMC2, 37, -1),
> +	TEGRA_IO_PADS_CONTROL(DSIB, 39, -1),
> +	TEGRA_IO_PADS_CONTROL(DSIC, 40, -1),
> +	TEGRA_IO_PADS_CONTROL(DSID, 41, -1),
> +	TEGRA_IO_PADS_CONTROL(CSIC, 42, -1),
> +	TEGRA_IO_PADS_CONTROL(CSID, 43, -1),
> +	TEGRA_IO_PADS_CONTROL(CSIE, 44, -1),
> +	TEGRA_IO_PADS_CONTROL(CSIF, 45, -1),
> +	TEGRA_IO_PADS_CONTROL(SPI, 46, -1),
> +	TEGRA_IO_PADS_CONTROL(SPI_HV, 47, 23),
> +	TEGRA_IO_PADS_CONTROL(DMIC, 50, -1),
> +	TEGRA_IO_PADS_CONTROL(DP, 51, -1),
> +	TEGRA_IO_PADS_CONTROL(LVDS, 57, -1),
> +	TEGRA_IO_PADS_CONTROL(AUDIO_HV, 61, 18),
> +};
> +
> +static int tegra_io_pads_to_dpd(const struct tegra_pmc_soc *soc, int pad_id)
> +{
> +	int i;
> +
> +	if (!soc || !soc->num_io_pads)
> +		return -EINVAL;
> +
> +	for (i = 0; i < soc->num_io_pads; ++i) {
> +		if (soc->io_pads_control[i].pad_id == pad_id)
> +			return soc->io_pads_control[i].dpd_bit_pos;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +static int tegra_io_pads_to_power_val(const struct tegra_pmc_soc *soc,
> +				      int pad_id)
> +{
> +	int i;
> +
> +	if (!soc || !soc->num_io_pads)
> +		return -EINVAL;
> +
> +	for (i = 0; i < soc->num_io_pads; ++i) {
> +		if (soc->io_pads_control[i].pad_id == pad_id)
> +			return soc->io_pads_control[i].pwr_val_pos;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +int tegra_io_pads_power_enable(int io_pad_id)
> +{
> +	int dpd_bit;
> +
> +	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
> +	if (dpd_bit < 0)
> +		return dpd_bit;
> +
> +	return tegra_io_rail_power_on(dpd_bit);

>From a readability standpoint the above seems weird because
tegra_io_pads_power_enable() takes an ID as the argument, translates it
to a bit value and passes it to tegra_io_rail_power_on() which also
takes an ID for the argument.

> +}
> +EXPORT_SYMBOL(tegra_io_pads_power_enable);
> +
> +int tegra_io_pads_power_disable(int io_pad_id)
> +{
> +	int dpd_bit;
> +
> +	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
> +	if (dpd_bit < 0)
> +		return dpd_bit;
> +
> +	return tegra_io_rail_power_off(dpd_bit);
> +}
> +EXPORT_SYMBOL(tegra_io_pads_power_disable);
> +
> +int tegra_io_pads_power_is_enabled(int io_pad_id)
> +{
> +	unsigned long status_reg;
> +	u32 status;
> +	int dpd_bit;
> +
> +	dpd_bit = tegra_io_pads_to_dpd(pmc->soc, io_pad_id);
> +	if (dpd_bit < 0)
> +		return dpd_bit;
> +
> +	status_reg = (dpd_bit < 32) ? IO_DPD_STATUS : IO_DPD2_STATUS;
> +	status = tegra_pmc_readl(status_reg);
> +
> +	return !!(status & BIT(dpd_bit % 32));
> +}
> +EXPORT_SYMBOL(tegra_io_pads_power_is_enabled);
> +
> +int tegra_io_pads_configure_voltage(int io_pad_id, int io_volt_uv)
> +{
> +	int pwr_bit;
> +	u32 bval;
> +
> +	if ((io_volt_uv != 3300000) && (io_volt_uv != 1800000))
> +		return -EINVAL;
> +
> +	pwr_bit = tegra_io_pads_to_power_val(pmc->soc, io_pad_id);
> +	if (pwr_bit < 0)
> +		return pwr_bit;
> +
> +	bval = (io_volt_uv == 3300000) ? BIT(pwr_bit) : 0;
> +
> +	mutex_lock(&pmc->powergates_lock);
> +	tegra_pmc_read_modify_write(PMC_PWR_DET, BIT(pwr_bit), BIT(pwr_bit));
> +	tegra_pmc_read_modify_write(PMC_PWR_DET_VAL, BIT(pwr_bit), bval);
> +	mutex_unlock(&pmc->powergates_lock);

There are 4 instances of BIT(pwr_bit). May be we should do this once or
have tegra_io_pads_to_power_val() return the bit?

> +	usleep_range(100, 250);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(tegra_io_pads_configure_voltage);
> +
> +int tegra_io_pads_get_configured_voltage(int io_pad_id)
> +{
> +	int pwr_bit;
> +	u32 pwr_det_val;
> +
> +	pwr_bit = tegra_io_pads_to_power_val(pmc->soc, io_pad_id);
> +	if (pwr_bit < 0)
> +		return pwr_bit;
> +
> +	pwr_det_val = tegra_pmc_readl(PMC_PWR_DET_VAL);
> +
> +	return (pwr_det_val & BIT(pwr_bit)) ? 3300000 : 1800000;
> +}
> +EXPORT_SYMBOL(tegra_io_pads_get_configured_voltage);
> +
>  #ifdef CONFIG_PM_SLEEP
>  enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
>  {
> @@ -1443,6 +1621,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
>  	.powergates = tegra210_powergates,
>  	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
>  	.cpu_powergates = tegra210_cpu_powergates,
> +	.io_pads_control = tegra210_io_pads_control,
> +	.num_io_pads = ARRAY_SIZE(tegra210_io_pads_control),
>  	.has_tsense_reset = true,
>  	.has_gpu_clamps = true,
>  };
> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
> index e9e5347..79e38f5 100644
> --- a/include/soc/tegra/pmc.h
> +++ b/include/soc/tegra/pmc.h
> @@ -108,6 +108,58 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
>  #define TEGRA_IO_RAIL_LVDS	57
>  #define TEGRA_IO_RAIL_SYS_DDC	58
>  
> +/* TEGRA_IO_PAD: The IO pins of Tegra SoCs are grouped for common control
> + * of IO interface like setting voltage signal levels, power state of the
> + * interface. The group is generally referred as io-pads. The power and
> + * voltage control of IO pins are available at io-pads level.
> + * The following macros make the super list all IO pads found on Tegra SoC
> + * generations.
> + */
> +#define TEGRA_IO_PAD_AUDIO		0
> +#define TEGRA_IO_PAD_AUDIO_HV		1
> +#define TEGRA_IO_PAD_BB			2
> +#define TEGRA_IO_PAD_CAM		3
> +#define TEGRA_IO_PAD_COMP		4
> +#define TEGRA_IO_PAD_CSIA		5
> +#define TEGRA_IO_PAD_CSIB		6
> +#define TEGRA_IO_PAD_CSIC		7
> +#define TEGRA_IO_PAD_CSID		8
> +#define TEGRA_IO_PAD_CSIE		9
> +#define TEGRA_IO_PAD_CSIF		10
> +#define TEGRA_IO_PAD_DBG		11
> +#define TEGRA_IO_PAD_DEBUG_NONAO	12
> +#define TEGRA_IO_PAD_DMIC		13
> +#define TEGRA_IO_PAD_DP			14
> +#define TEGRA_IO_PAD_DSI		15
> +#define TEGRA_IO_PAD_DSIB		16
> +#define TEGRA_IO_PAD_DSIC		17
> +#define TEGRA_IO_PAD_DSID		18
> +#define TEGRA_IO_PAD_EMMC		19
> +#define TEGRA_IO_PAD_EMMC2		20
> +#define TEGRA_IO_PAD_GPIO		21
> +#define TEGRA_IO_PAD_HDMI		22
> +#define TEGRA_IO_PAD_HSIC		23
> +#define TEGRA_IO_PAD_HV			24
> +#define TEGRA_IO_PAD_LVDS		25
> +#define TEGRA_IO_PAD_MIPI_BIAS		26
> +#define TEGRA_IO_PAD_NAND		27
> +#define TEGRA_IO_PAD_PEX_BIAS		28
> +#define TEGRA_IO_PAD_PEX_CLK1		29
> +#define TEGRA_IO_PAD_PEX_CLK2		30
> +#define TEGRA_IO_PAD_PEX_CNTRL		31
> +#define TEGRA_IO_PAD_SDMMC1		32
> +#define TEGRA_IO_PAD_SDMMC3		33
> +#define TEGRA_IO_PAD_SDMMC4		34
> +#define TEGRA_IO_PAD_SPI		35
> +#define TEGRA_IO_PAD_SPI_HV		36
> +#define TEGRA_IO_PAD_SYS_DDC		37
> +#define TEGRA_IO_PAD_UART		38
> +#define TEGRA_IO_PAD_USB0		39
> +#define TEGRA_IO_PAD_USB1		40
> +#define TEGRA_IO_PAD_USB2		41
> +#define TEGRA_IO_PAD_USB3		42
> +#define TEGRA_IO_PAD_USB_BIAS		43
> +
>  #ifdef CONFIG_ARCH_TEGRA
>  int tegra_powergate_is_powered(unsigned int id);
>  int tegra_powergate_power_on(unsigned int id);
> @@ -120,6 +172,16 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
>  
>  int tegra_io_rail_power_on(unsigned int id);
>  int tegra_io_rail_power_off(unsigned int id);
> +
> +/* Power enable/disable of the IO pads */
> +int tegra_io_pads_power_enable(int io_pad_id);
> +int tegra_io_pads_power_disable(int io_pad_id);
> +int tegra_io_pads_power_is_enabled(int io_pad_id);

What I don't like here, is now we have two public APIs to do the same
job because tegra_io_pads_power_enable/disable() calls
tegra_io_rail_power_off/on() internally. Furthermore, the two APIs use
different ID definitions to accomplish the same job. This shouldn't be
necessary.

Jon

Re: [PATCH 4/6] soc/tegra: pmc: Register PMC child devices as platform device

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> Power Management Controller(PMC) of Tegra does the multiple chip
> power related functionality for internal and IO interfacing.
> Some of the functionalities are power gating of IP blocks, IO pads
> voltage and power state configuration, system power state configurations,
> wakeup controls etc.
> 
> Different functionalities of the PMC are provided through different
> framework like IO pads control can be provided through pinctrl framework,
> IO power control is via misc driver etc. All sub functionalities are
> represented as PMC child devices.
> 
> Register the PMC child devices as platform device and fill the child
> devices table for Tegra210.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> Reworked on DT for having flat entry and register all child devices
> as simple platform device instead of of_populate_device().
> ---
>  drivers/soc/tegra/pmc.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index b3be4b9..625167e 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -132,6 +132,8 @@ struct tegra_pmc_soc {
>  	const u8 *cpu_powergates;
>  	const struct tegra_io_pads_control *io_pads_control;
>  	unsigned int num_io_pads;
> +	const char **sub_devs_name;
> +	unsigned int num_sub_devs;
>  	bool has_tsense_reset;
>  	bool has_gpu_clamps;
>  };
> @@ -158,6 +160,8 @@ struct tegra_pmc_soc {
>   * @lp0_vec_size: size of the LP0 warm boot code
>   * @powergates_available: Bitmap of available power gates
>   * @powergates_lock: mutex for power gate register access
> + * @pdevs: Platform device for PMC child devices.
> + * @num_pdevs: Number of platform devices.
>   */
>  struct tegra_pmc {
>  	struct device *dev;
> @@ -184,6 +188,9 @@ struct tegra_pmc {
>  	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
>  
>  	struct mutex powergates_lock;
> +
> +	struct platform_device **pdevs;
> +	unsigned int num_pdevs;
>  };
>  
>  static struct tegra_pmc *pmc = &(struct tegra_pmc) {
> @@ -1379,6 +1386,43 @@ out:
>  	of_node_put(np);
>  }
>  
> +static int  tegra_pmc_init_sub_devs(struct tegra_pmc *pmc)
> +{
> +	int ret, i;
> +
> +	if (!pmc->soc->num_sub_devs)
> +		return 0;
> +
> +	pmc->pdevs = devm_kzalloc(pmc->dev, sizeof(**pmc->pdevs), GFP_KERNEL);
> +	if (!pmc->pdevs)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < pmc->soc->num_sub_devs; ++i) {
> +		pmc->pdevs[i] = platform_device_register_data(pmc->dev,
> +						pmc->soc->sub_devs_name[i],
> +						0, NULL, 0);
> +		if (IS_ERR(pmc->pdevs[i])) {
> +			ret = PTR_ERR(pmc->pdevs[i]);
> +			dev_err(pmc->dev,
> +				"Failed to register platform device for %s: %d\n",
> +				pmc->soc->sub_devs_name[i], ret);
> +			goto pdev_cleanups;
> +		}
> +		pmc->num_pdevs++;
> +	}
> +
> +	return 0;
> +
> +pdev_cleanups:
> +	for (i = pmc->num_pdevs; i > 0; i--) {
> +		platform_device_unregister(pmc->pdevs[i - 1]);
> +		pmc->pdevs[i - 1] = NULL;
> +	}
> +	pmc->num_pdevs = 0;
> +
> +	return ret;
> +}
> +
>  static int tegra_pmc_probe(struct platform_device *pdev)
>  {
>  	void __iomem *base;
> @@ -1408,6 +1452,10 @@ static int tegra_pmc_probe(struct platform_device *pdev)
>  
>  	tegra_pmc_init_tsense_reset(pmc);
>  
> +	err = tegra_pmc_init_sub_devs(pmc);
> +	if (err < 0)
> +		dev_warn(pmc->dev, "Failed to register sub devices: %d\n", err);
> +
>  	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
>  		err = tegra_powergate_debugfs_init();
>  		if (err < 0)

If tegra_powergate_debugfs_init() fails (or any other subsequent call
for that matter), you don't remove the child devices you added. You need
to handle that in any failure path.

Jon

Re: [PATCH 5/6] pinctrl: tegra: Add DT binding for io pads control

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also IO pads can be configured for
> power down state if it is not in used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
> 
> Add DT binding document for detailing the DT properties for
> configuring IO pads voltage levels and its power state.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> - Reworked on DT properties to use generic pinconf DT. Also add macros
> for voltage support. Now all DT properties are in flat DT instead of
> sub node based.
> ---
>  .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 88 ++++++++++++++++++++++
>  .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  | 20 +++++
>  2 files changed, 108 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
>  create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
> new file mode 100644
> index 0000000..7616380
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
> @@ -0,0 +1,88 @@
> +NVIDIA Tegra210 PMC IO pad controller
> +
> +NVIDIA Tegra210 supports IO pads which can operate at 1.8V or 3.3V I/O
> +power rail source. SW needs to configure the voltage level of IO pads
> +based on platform specific power tree.
> +
> +The voltage configurations of IO pads should be done in boot if it is not
> +going to change other wise dynamically based on IO rail voltage on that
> +IO pads.
> +
> +The DT property of the io pads must be under the node of pmc i.e.
> +pmc@7000e400 for Tegra210.
> +
> +Please refer to <pinctrl-bindings.txt> in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +Tegra's pin configuration nodes act as a container for an arbitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for an
> +IO pads, or a list of IO pads. This configuration can include the voltage and
> +power enable/disable control
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content. Each subnode only affects those
> +parameters that are explicitly listed. Unspecified is represented as an absent
> +property,
> +
> +See the TRM to determine which properties and values apply to each IO pads.
> +Macro values for property values are defined in
> +<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +
> +The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
> +	For 1.8V, use TEGRA_IO_PAD_POWER_SOURCE_1800000UV
> +	For 3.3V, use TEGRA_IO_PAD_POWER_SOURCE_3300000UV

Are these still necessary now that the driver is using uV? Can't we just
use integer values for 1800000 and 3300000 in the DTS directly?

> +Required subnode-properties:
> +==========================
> +- pins : An array of strings. Each string contains the name of an IO pads. Valid
> +	 values for these names are listed below.

Please see my previous comments.

> +Optional subnode-properties:
> +==========================
> +-nvidia,power-source-voltage:	Integer. The voltage level of IO pads. The

I think I prefer nvidia,io-voltage or something. You can describe what
this means in this doc. In fact, the current description here does not
explicitly state that this voltage, is the voltage the pad is configured
to operate at versus the voltage of the IO rail.

> +				valid values are 1.8V and 3.3V. Macros are
> +				defined for these voltage levels in
> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +				Use TEGRA_IO_PAD_POWER_SOURCE_1800000UV for 1.8V
> +				Use TEGRA_IO_PAD_POWER_SOURCE_3300000UV for 3.3V
> +
> +				All IO pads do not support the 1.8V/3.3V
> +				configurations. Valid values for "pins" are
> +				audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv.
> +
> +Other than above, following properties are supported from generic pin
> +configuration explained in <dt-bindings/pinctrl/pinctrl-binding.txt>.
> +low-power-enable:		enable low power mode.
> +low-power-disable:		disable low power mode.
> +
> +Valid values for pin for low power mode supports are:
> +	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
> +	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
> +	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
> +	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
> +	usb1, usb2, usb3.
> +
> +Example:
> +	#include <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +	pmc@7000e400 {
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&tegra_io_pad_volt_default>;
> +		tegra_io_pad_volt_default: common {
> +			audio-hv {
> +				pins = "audio-hv";
> +				nvidia,power-source-voltage = <TEGRA_IO_PAD_POWER_SOURCE_3300000UV>;
> +			};
> +
> +			gpio {
> +				pins = "gpio";
> +				invidia,power-source-voltage = <TEGRA_IO_PAD_POWER_SOURCE_1800000UV>;

Typo. "invidia,power-source-voltage".

Jon

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Laxman Dewangan]

On Tuesday 03 May 2016 06:25 PM, Jon Hunter wrote:
>
>>
>> Currently SOR driver is using the tegra_io_rail_power_off/on() APIs.
>> Once the proper interface available then I will move sor driver to use
>> new method and then we can full get rid of older APIs and macros.
>>
>> Till that, we need to have this.
> I prefer it is done before this series. In other words, if we need a
> proper enum for the rail/pad IDs then add one and convert any existing
> drivers over to use any new APIs first.

But the converting to new API can be done after this patch only.

I need to implement new APIs and then move driver to use new APIs and 
then remove older one.

Otherwise, I need to have single patch for the new API + converting 
existing user to use new APIs.
If this is allowed in subsystem level then this is best method.

We already did for max77686 RTC + mfd change together.

So will it be fine to make such changes?

Re: [PATCH 5/6] pinctrl: tegra: Add DT binding for io pads control

[Laxman Dewangan]

On Tuesday 03 May 2016 06:14 PM, Jon Hunter wrote:
> On 02/05/16 13:17, Laxman Dewangan wrote:
>> +
>> +The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
>> +	For 1.8V, use TEGRA_IO_PAD_POWER_SOURCE_1800000UV
>> +	For 3.3V, use TEGRA_IO_PAD_POWER_SOURCE_3300000UV
> Are these still necessary now that the driver is using uV? Can't we just
> use integer values for 1800000 and 3300000 in the DTS directly?
>
The config param and value are packed in u32 with 16bit each So we can 
not make uV in 16bit until we do conversion of uV->mV.
Hence suggestion came from Stephen that we can have enum for Nvidia 
specific and what actually it supports by HW. HW does not support any 
other voltage.


>> +Required subnode-properties:
>> +==========================
>> +- pins : An array of strings. Each string contains the name of an IO pads. Valid
>> +	 values for these names are listed below.
> Please see my previous comments.

This is taken from other dt binding docs for description. We can have 
array of string.
As all value of pins are not supporting all property and hence I 
explicitly wrote under properties.

>
>> +Optional subnode-properties:
>> +==========================
>> +-nvidia,power-source-voltage:	Integer. The voltage level of IO pads. The
> I think I prefer nvidia,io-voltage or something. You can describe what
> this means in this doc. In fact, the current description here does not
> explicitly state that this voltage, is the voltage the pad is configured
> to operate at versus the voltage of the IO rail.

Linus suggested this dt property name to make more readable and generic 
and meaningful with other property :power-source.

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Jon Hunter]

On 03/05/16 13:31, Laxman Dewangan wrote:
> 
> On Tuesday 03 May 2016 06:04 PM, Jon Hunter wrote:
>> On 02/05/16 13:17, Laxman Dewangan wrote:
>>> +
>>> +    return tegra_io_rail_power_on(dpd_bit);
>>  From a readability standpoint the above seems weird because
>> tegra_io_pads_power_enable() takes an ID as the argument, translates it
>> to a bit value and passes it to tegra_io_rail_power_on() which also
>> takes an ID for the argument.
> 
> Yaah, I did not want to duplicate the implementation and hence it is there.
> We will get rid of the older APIs once this is IN and new mechanism there.
> 
> 
> 
>>> +
>>> +    bval = (io_volt_uv == 3300000) ? BIT(pwr_bit) : 0;
>>> +
>>> +    mutex_lock(&pmc->powergates_lock);
>>> +    tegra_pmc_read_modify_write(PMC_PWR_DET, BIT(pwr_bit),
>>> BIT(pwr_bit));
>>> +    tegra_pmc_read_modify_write(PMC_PWR_DET_VAL, BIT(pwr_bit), bval);
>>> +    mutex_unlock(&pmc->powergates_lock);
>> There are 4 instances of BIT(pwr_bit). May be we should do this once or
>> have tegra_io_pads_to_power_val() return the bit?
> 
> OK, will re-write this part.
> 
> 
>>
>>> +int tegra_io_pads_power_disable(int io_pad_id);
>>> +int tegra_io_pads_power_is_enabled(int io_pad_id);
>> What I don't like here, is now we have two public APIs to do the same
>> job because tegra_io_pads_power_enable/disable() calls
>> tegra_io_rail_power_off/on() internally. Furthermore, the two APIs use
>> different ID definitions to accomplish the same job. This shouldn't be
>> necessary.
> 
> Currently SOR driver is using the tegra_io_rail_power_off/on() APIs.
> Once the proper interface available then I will move sor driver to use
> new method and then we can full get rid of older APIs and macros.
> 
> Till that, we need to have this.

I prefer it is done before this series. In other words, if we need a
proper enum for the rail/pad IDs then add one and convert any existing
drivers over to use any new APIs first. The other option is to live with
the existing API names.

Jon

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Laxman Dewangan]

On Tuesday 03 May 2016 06:42 PM, Jon Hunter wrote:
> On 03/05/16 13:48, Laxman Dewangan wrote:
>> On Tuesday 03 May 2016 06:25 PM, Jon Hunter wrote:
>>>> Currently SOR driver is using the tegra_io_rail_power_off/on() APIs.
>>>> Once the proper interface available then I will move sor driver to use
>>>> new method and then we can full get rid of older APIs and macros.
>>>>
>>>> Till that, we need to have this.
>>> I prefer it is done before this series. In other words, if we need a
>>> proper enum for the rail/pad IDs then add one and convert any existing
>>> drivers over to use any new APIs first.
>> But the converting to new API can be done after this patch only.
> Yes but before you add the pinctrl driver. May be you should separate
> the two.
>
> My point is that any follow-up series to this, would have to touch the
> pmc and the sor driver. So why not make the changes for the pmc and sor
> now, and once in place then add the pinctrl driver?

I will be happy on this approach also. I added pincontrol driver for 
following purpose:
- To show how new APIs used. This will help on understanding of need and 
whole as a design.
- To get reviewed the whole design/method.
- To get accepted the pmc changes on this cycle so that if possible, we 
can have pincntrl driver in next cycle to avoid cross subsystem approach.

Re: [PATCH 3/6] soc/tegra: pmc: Add support for IO pads power state and voltage

[Jon Hunter]

On 03/05/16 13:48, Laxman Dewangan wrote:
> 
> On Tuesday 03 May 2016 06:25 PM, Jon Hunter wrote:
>>
>>>
>>> Currently SOR driver is using the tegra_io_rail_power_off/on() APIs.
>>> Once the proper interface available then I will move sor driver to use
>>> new method and then we can full get rid of older APIs and macros.
>>>
>>> Till that, we need to have this.
>> I prefer it is done before this series. In other words, if we need a
>> proper enum for the rail/pad IDs then add one and convert any existing
>> drivers over to use any new APIs first.
> 
> But the converting to new API can be done after this patch only.

Yes but before you add the pinctrl driver. May be you should separate
the two.

My point is that any follow-up series to this, would have to touch the
pmc and the sor driver. So why not make the changes for the pmc and sor
now, and once in place then add the pinctrl driver?

Jon

Re: [PATCH 5/6] pinctrl: tegra: Add DT binding for io pads control

[Jon Hunter]

On 03/05/16 13:54, Laxman Dewangan wrote:
> 
> On Tuesday 03 May 2016 06:14 PM, Jon Hunter wrote:
>> On 02/05/16 13:17, Laxman Dewangan wrote:
>>> +
>>> +The voltage supported on the pads are 1.8V and 3.3V. The enums are
>>> defined as:
>>> +    For 1.8V, use TEGRA_IO_PAD_POWER_SOURCE_1800000UV
>>> +    For 3.3V, use TEGRA_IO_PAD_POWER_SOURCE_3300000UV
>> Are these still necessary now that the driver is using uV? Can't we just
>> use integer values for 1800000 and 3300000 in the DTS directly?
>>
> The config param and value are packed in u32 with 16bit each So we can
> not make uV in 16bit until we do conversion of uV->mV.
> Hence suggestion came from Stephen that we can have enum for Nvidia
> specific and what actually it supports by HW. HW does not support any
> other voltage.

Ah yes I see.

> 
>>> +Required subnode-properties:
>>> +==========================
>>> +- pins : An array of strings. Each string contains the name of an IO
>>> pads. Valid
>>> +     values for these names are listed below.
>> Please see my previous comments.
> 
> This is taken from other dt binding docs for description. We can have
> array of string.

OK.

> As all value of pins are not supporting all property and hence I
> explicitly wrote under properties.

I don't find it very clear. I thought all pins support the low power
modes so I think it is clearer to list all the pin names under the pins
description.

>>> +Optional subnode-properties:
>>> +==========================
>>> +-nvidia,power-source-voltage:    Integer. The voltage level of IO
>>> pads. The
>> I think I prefer nvidia,io-voltage or something. You can describe what
>> this means in this doc. In fact, the current description here does not
>> explicitly state that this voltage, is the voltage the pad is configured
>> to operate at versus the voltage of the IO rail.
> 
> Linus suggested this dt property name to make more readable and generic
> and meaningful with other property :power-source.

OK.

Jon

Re: [PATCH 4/6] soc/tegra: pmc: Register PMC child devices as platform device

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> Power Management Controller(PMC) of Tegra does the multiple chip
> power related functionality for internal and IO interfacing.
> Some of the functionalities are power gating of IP blocks, IO pads
> voltage and power state configuration, system power state configurations,
> wakeup controls etc.
> 
> Different functionalities of the PMC are provided through different
> framework like IO pads control can be provided through pinctrl framework,
> IO power control is via misc driver etc. All sub functionalities are
> represented as PMC child devices.
> 
> Register the PMC child devices as platform device and fill the child
> devices table for Tegra210.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> Reworked on DT for having flat entry and register all child devices
> as simple platform device instead of of_populate_device().
> ---
>  drivers/soc/tegra/pmc.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index b3be4b9..625167e 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -132,6 +132,8 @@ struct tegra_pmc_soc {
>  	const u8 *cpu_powergates;
>  	const struct tegra_io_pads_control *io_pads_control;
>  	unsigned int num_io_pads;
> +	const char **sub_devs_name;
> +	unsigned int num_sub_devs;
>  	bool has_tsense_reset;
>  	bool has_gpu_clamps;
>  };
> @@ -158,6 +160,8 @@ struct tegra_pmc_soc {
>   * @lp0_vec_size: size of the LP0 warm boot code
>   * @powergates_available: Bitmap of available power gates
>   * @powergates_lock: mutex for power gate register access
> + * @pdevs: Platform device for PMC child devices.
> + * @num_pdevs: Number of platform devices.
>   */
>  struct tegra_pmc {
>  	struct device *dev;
> @@ -184,6 +188,9 @@ struct tegra_pmc {
>  	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
>  
>  	struct mutex powergates_lock;
> +
> +	struct platform_device **pdevs;
> +	unsigned int num_pdevs;

We already have num_sub_devs in the soc data, do we really need this?

>  };
>  
>  static struct tegra_pmc *pmc = &(struct tegra_pmc) {
> @@ -1379,6 +1386,43 @@ out:
>  	of_node_put(np);
>  }
>  
> +static int  tegra_pmc_init_sub_devs(struct tegra_pmc *pmc)
> +{
> +	int ret, i;
> +
> +	if (!pmc->soc->num_sub_devs)
> +		return 0;
> +
> +	pmc->pdevs = devm_kzalloc(pmc->dev, sizeof(**pmc->pdevs), GFP_KERNEL);
> +	if (!pmc->pdevs)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < pmc->soc->num_sub_devs; ++i) {
> +		pmc->pdevs[i] = platform_device_register_data(pmc->dev,
> +						pmc->soc->sub_devs_name[i],
> +						0, NULL, 0);
> +		if (IS_ERR(pmc->pdevs[i])) {
> +			ret = PTR_ERR(pmc->pdevs[i]);
> +			dev_err(pmc->dev,
> +				"Failed to register platform device for %s: %d\n",
> +				pmc->soc->sub_devs_name[i], ret);
> +			goto pdev_cleanups;
> +		}
> +		pmc->num_pdevs++;

I would get rid of pmc->num_pdevs because isn't this always equal to i here?

> +	}
> +
> +	return 0;
> +
> +pdev_cleanups:
> +	for (i = pmc->num_pdevs; i > 0; i--) {

Here I think this could be ...

	while (--i) {

> +		platform_device_unregister(pmc->pdevs[i - 1]);
> +		pmc->pdevs[i - 1] = NULL;
> +	}
> +	pmc->num_pdevs = 0;
> +
> +	return ret;
> +}

Cheers
Jon

Re: [PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Linus Walleij]

On Mon, May 2, 2016 at 2:17 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:

> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also the IO pads can be configured
> for power down state if it is not used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
>
> The voltage and power state configurations of pads are provided
> through pin control frameworks. Add pin control driver for Tegra's
> IO pads' voltage and power state configurations.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>
> ---
> Changes from V1:
> - Use the generic pincontrol property for low power enable/disable.
> - sync with latest and remove all MODULE* macros
> - Use renamed APIs form PMC

Looks OK to me, need Stephen's ACK though!

Yours,
Linus Walleij

Re: [PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Stephen Warren]

On 05/11/2016 03:19 AM, Linus Walleij wrote:
> On Mon, May 2, 2016 at 2:17 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
>
>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>> or 3.3V I/O voltage levels. Also the IO pads can be configured
>> for power down state if it is not used. SW needs to configure the
>> voltage level of IO pads based on IO rail voltage and its power
>> state based on platform usage.
>>
>> The voltage and power state configurations of pads are provided
>> through pin control frameworks. Add pin control driver for Tegra's
>> IO pads' voltage and power state configurations.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>
>> ---
>> Changes from V1:
>> - Use the generic pincontrol property for low power enable/disable.
>> - sync with latest and remove all MODULE* macros
>> - Use renamed APIs form PMC
>
> Looks OK to me, need Stephen's ACK though!

This driver is for HW that's separate from the main Tegra pinmux module. 
Thierry Reding and Jon Hunter are more appropriate reviewers for this one.

Re: [PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Jon Hunter]

On 11/05/16 17:07, Stephen Warren wrote:
> On 05/11/2016 03:19 AM, Linus Walleij wrote:
>> On Mon, May 2, 2016 at 2:17 PM, Laxman Dewangan <ldewangan@nvidia.com>
>> wrote:
>>
>>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>>> or 3.3V I/O voltage levels. Also the IO pads can be configured
>>> for power down state if it is not used. SW needs to configure the
>>> voltage level of IO pads based on IO rail voltage and its power
>>> state based on platform usage.
>>>
>>> The voltage and power state configurations of pads are provided
>>> through pin control frameworks. Add pin control driver for Tegra's
>>> IO pads' voltage and power state configurations.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>>
>>> ---
>>> Changes from V1:
>>> - Use the generic pincontrol property for low power enable/disable.
>>> - sync with latest and remove all MODULE* macros
>>> - Use renamed APIs form PMC
>>
>> Looks OK to me, need Stephen's ACK though!
> 
> This driver is for HW that's separate from the main Tegra pinmux module.
> Thierry Reding and Jon Hunter are more appropriate reviewers for this one.

There will be another spin of this, so let's wait for the V2.

Cheers
Jon

Re: [PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Javier Martinez Canillas]

Hello Laxman,

On Mon, May 2, 2016 at 8:17 AM, Laxman Dewangan <ldewangan@nvidia.com> wrote:

[snip]

> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
> new file mode 100644
> index 0000000..ab06c71
> --- /dev/null
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
> @@ -0,0 +1,301 @@
> +/*
> + * Generic ADC thermal driver
> + *

This seems to be a copy and paste error from
drivers/thermal/thermal-generic-adc.c since this is a pinctrl driver.

Best regards,
Javier

Re: [PATCH 6/6] pinctrl: tegra: Add driver to configure voltage and power state of io pads

[Jon Hunter]

On 02/05/16 13:17, Laxman Dewangan wrote:
> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also the IO pads can be configured
> for power down state if it is not used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
> 
> The voltage and power state configurations of pads are provided
> through pin control frameworks. Add pin control driver for Tegra's
> IO pads' voltage and power state configurations.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> 
> ---
> Changes from V1:
> - Use the generic pincontrol property for low power enable/disable.
> - sync with latest and remove all MODULE* macros
> - Use renamed APIs form PMC
> ---
>  drivers/pinctrl/tegra/Makefile                  |   1 +
>  drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c | 301 ++++++++++++++++++++++++
>  2 files changed, 302 insertions(+)
>  create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c

[snip]

> +static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctldev,
> +				    unsigned int pin, unsigned long *config)
> +{
> +	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
> +	int param = pinconf_to_config_param(*config);
> +	struct tegra_io_pads_cfg_info *pad_cfg = &tiopi->pads_cfg[pin];
> +	int pad_id = pad_cfg->pad_id;
> +	int arg = 0;
> +	int ret;
> +
> +	switch (param) {
> +	case TEGRA_IO_PAD_POWER_SOURCE_VOLTAGE:
> +		ret = tegra_io_pads_get_configured_voltage(pad_id);
> +		if (ret < 0)
> +			return ret;
> +		arg = (ret =  3300000) ? 1 : 0;

This should be (ret == 3300000).

Cheers
Jon