* [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical
@ 2016-05-13 18:42 Brian Norris
2016-05-13 18:42 ` [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src Brian Norris
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Brian Norris @ 2016-05-13 18:42 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, Heiko Stuebner, linux-kernel, linux-arm-kernel,
linux-rockchip, Doug Anderson, Brian Norris, Xing Zheng,
Brian Norris
We never want to kill the GIC.
Noticed when making other clock fixups, and seeing the newly-constructed
clock tree try to disable cpll, where we had this parent structure:
aclk_gic <------\
|--- aclk_gic_pre <-- cpll <-- pll_cpll
aclk_gic_noc <--/
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/clk/rockchip/clk-rk3399.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 291543f52caa..145756c4f3c8 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1466,6 +1466,8 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
static const char *const rk3399_cru_critical_clocks[] __initconst = {
"aclk_cci_pre",
+ "aclk_gic",
+ "aclk_gic_noc",
"pclk_perilp0",
"pclk_perilp0",
"hclk_perilp0",
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
2016-05-13 18:42 [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Brian Norris
@ 2016-05-13 18:42 ` Brian Norris
2016-05-13 20:10 ` Doug Anderson
2016-05-13 19:43 ` [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Doug Anderson
2016-05-17 21:10 ` Heiko Stuebner
2 siblings, 1 reply; 8+ messages in thread
From: Brian Norris @ 2016-05-13 18:42 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, Heiko Stuebner, linux-kernel, linux-arm-kernel,
linux-rockchip, Doug Anderson, Brian Norris, Xing Zheng,
Brian Norris
From: Xing Zheng <zhengxing@rock-chips.com>
There was a typo, swapping 'c' <--> 'g'.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 145756c4f3c8..9f86bfef70f7 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(13), 1, GFLAGS),
/* perihp */
- GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 0, GFLAGS),
- GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+ GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical
2016-05-13 18:42 [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Brian Norris
2016-05-13 18:42 ` [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src Brian Norris
@ 2016-05-13 19:43 ` Doug Anderson
2016-05-17 21:10 ` Heiko Stuebner
2 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2016-05-13 19:43 UTC (permalink / raw)
To: Brian Norris
Cc: Michael Turquette, Stephen Boyd, linux-clk, Heiko Stuebner,
linux-kernel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
Brian Norris, Xing Zheng
Brian,
On Fri, May 13, 2016 at 11:42 AM, Brian Norris <briannorris@chromium.org> wrote:
> We never want to kill the GIC.
>
> Noticed when making other clock fixups, and seeing the newly-constructed
> clock tree try to disable cpll, where we had this parent structure:
>
> aclk_gic <------\
> |--- aclk_gic_pre <-- cpll <-- pll_cpll
> aclk_gic_noc <--/
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
> drivers/clk/rockchip/clk-rk3399.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
2016-05-13 18:42 ` [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src Brian Norris
@ 2016-05-13 20:10 ` Doug Anderson
2016-05-14 3:36 ` Xing Zheng
0 siblings, 1 reply; 8+ messages in thread
From: Doug Anderson @ 2016-05-13 20:10 UTC (permalink / raw)
To: Brian Norris
Cc: Michael Turquette, Stephen Boyd, linux-clk, Heiko Stuebner,
linux-kernel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
Brian Norris, Xing Zheng
Hi,
On Fri, May 13, 2016 at 11:42 AM, Brian Norris <briannorris@chromium.org> wrote:
> From: Xing Zheng <zhengxing@rock-chips.com>
>
> There was a typo, swapping 'c' <--> 'g'.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 145756c4f3c8..9f86bfef70f7 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>
> /* perihp */
> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 0, GFLAGS),
> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 1, GFLAGS),
> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
Definitely there was a bug since this table itself was inconsistent.
...and I _think_ this fix is correct, but I'll note that the TRM has
more inconsistency here.
In the big clock table 'CRU Clock Architecture Diagram', I see:
CLK 4 is CPLL
CLK 5 is GPLL
CLK 125 is aclk_perihp_cpll_src and has 4 (CPLL) as source, with
g5[0] as the bit
CLK 126 is aclk_perihp_gpll_src and has 5 (GPLL) as source, with
g5[1] as the bit
In the definition of CRU_CLKGATE_CON5:
bit 0 shows aclk_perihp_gpll_src_en
bit 1 shows aclk_perihp_cpll_src_en
Thus the table shows CPLL as gate5[0] and GPLL as gate5[1]. The
register definition shows the opposite. I'll tend to believe the
table over the register definition, but I figured I'd bring it up
anyway.
Xing Zheng: can you confirm that the table is correct and ask
documentation folks to fix the register definition for
CRU_CLKGATE_CON5?
Thanks!
-Doug
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
2016-05-13 20:10 ` Doug Anderson
@ 2016-05-14 3:36 ` Xing Zheng
2016-05-16 15:49 ` Doug Anderson
0 siblings, 1 reply; 8+ messages in thread
From: Xing Zheng @ 2016-05-14 3:36 UTC (permalink / raw)
To: Doug Anderson, Brian Norris
Cc: Michael Turquette, Stephen Boyd, linux-clk, Heiko Stuebner,
linux-kernel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
Brian Norris
Hi Doug,
On 2016年05月14日 04:10, Doug Anderson wrote:
> Hi,
>
> On Fri, May 13, 2016 at 11:42 AM, Brian Norris <briannorris@chromium.org> wrote:
>> From: Xing Zheng <zhengxing@rock-chips.com>
>>
>> There was a typo, swapping 'c' <--> 'g'.
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> Signed-off-by: Brian Norris <briannorris@chromium.org>
>> ---
>> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
>> index 145756c4f3c8..9f86bfef70f7 100644
>> --- a/drivers/clk/rockchip/clk-rk3399.c
>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>>
>> /* perihp */
>> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>> RK3399_CLKGATE_CON(5), 0, GFLAGS),
>> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>> RK3399_CLKGATE_CON(5), 1, GFLAGS),
>> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
> Definitely there was a bug since this table itself was inconsistent.
> ...and I _think_ this fix is correct, but I'll note that the TRM has
> more inconsistency here.
>
> In the big clock table 'CRU Clock Architecture Diagram', I see:
> CLK 4 is CPLL
> CLK 5 is GPLL
> CLK 125 is aclk_perihp_cpll_src and has 4 (CPLL) as source, with
> g5[0] as the bit
> CLK 126 is aclk_perihp_gpll_src and has 5 (GPLL) as source, with
> g5[1] as the bit
>
> In the definition of CRU_CLKGATE_CON5:
> bit 0 shows aclk_perihp_gpll_src_en
> bit 1 shows aclk_perihp_cpll_src_en
>
>
> Thus the table shows CPLL as gate5[0] and GPLL as gate5[1]. The
> register definition shows the opposite. I'll tend to believe the
> table over the register definition, but I figured I'd bring it up
> anyway.
>
>
> Xing Zheng: can you confirm that the table is correct and ask
> documentation folks to fix the register definition for
> CRU_CLKGATE_CON5?
Yes, previously, our IC & DOC partner confirmed that the definition of
CRU_CLKGATE_CON5 should be:
bit 0 shows aclk_perihp_cpll_src_en
bit 1 shows aclk_perihp_gpll_src_en
Sorry to the incorrect register definition, we will fix them and review
the TRM again.
Thanks.
--
- Xing Zheng
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
2016-05-14 3:36 ` Xing Zheng
@ 2016-05-16 15:49 ` Doug Anderson
2016-08-01 10:08 ` Xing Zheng
0 siblings, 1 reply; 8+ messages in thread
From: Doug Anderson @ 2016-05-16 15:49 UTC (permalink / raw)
To: Xing Zheng
Cc: Brian Norris, Michael Turquette, Stephen Boyd, linux-clk,
Heiko Stuebner, linux-kernel, linux-arm-kernel,
open list:ARM/Rockchip SoC...,
Brian Norris
Hi,
On Fri, May 13, 2016 at 8:36 PM, Xing Zheng <zhengxing@rock-chips.com> wrote:
> Hi Doug,
>
>
> On 2016年05月14日 04:10, Doug Anderson wrote:
>>
>> Hi,
>>
>> On Fri, May 13, 2016 at 11:42 AM, Brian Norris <briannorris@chromium.org>
>> wrote:
>>>
>>> From: Xing Zheng <zhengxing@rock-chips.com>
>>>
>>> There was a typo, swapping 'c' <--> 'g'.
>>>
>>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>>> Signed-off-by: Brian Norris <briannorris@chromium.org>
>>> ---
>>> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/rockchip/clk-rk3399.c
>>> b/drivers/clk/rockchip/clk-rk3399.c
>>> index 145756c4f3c8..9f86bfef70f7 100644
>>> --- a/drivers/clk/rockchip/clk-rk3399.c
>>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>>> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch
>>> rk3399_clk_branches[] __initdata = {
>>> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>>>
>>> /* perihp */
>>> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>> RK3399_CLKGATE_CON(5), 0, GFLAGS),
>>> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>> RK3399_CLKGATE_CON(5), 1, GFLAGS),
>>> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
>>> CLK_IGNORE_UNUSED,
>>> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5,
>>> DFLAGS,
>>
>> Definitely there was a bug since this table itself was inconsistent.
>> ...and I _think_ this fix is correct, but I'll note that the TRM has
>> more inconsistency here.
>>
>> In the big clock table 'CRU Clock Architecture Diagram', I see:
>> CLK 4 is CPLL
>> CLK 5 is GPLL
>> CLK 125 is aclk_perihp_cpll_src and has 4 (CPLL) as source, with
>> g5[0] as the bit
>> CLK 126 is aclk_perihp_gpll_src and has 5 (GPLL) as source, with
>> g5[1] as the bit
>>
>> In the definition of CRU_CLKGATE_CON5:
>> bit 0 shows aclk_perihp_gpll_src_en
>> bit 1 shows aclk_perihp_cpll_src_en
>>
>>
>> Thus the table shows CPLL as gate5[0] and GPLL as gate5[1]. The
>> register definition shows the opposite. I'll tend to believe the
>> table over the register definition, but I figured I'd bring it up
>> anyway.
>>
>>
>> Xing Zheng: can you confirm that the table is correct and ask
>> documentation folks to fix the register definition for
>> CRU_CLKGATE_CON5?
>
> Yes, previously, our IC & DOC partner confirmed that the definition of
> CRU_CLKGATE_CON5 should be:
> bit 0 shows aclk_perihp_cpll_src_en
> bit 1 shows aclk_perihp_gpll_src_en
>
> Sorry to the incorrect register definition, we will fix them and review the
> TRM again.
Great!
Since we now have extra confirmation that Brian's patch is indeed correct:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical
2016-05-13 18:42 [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Brian Norris
2016-05-13 18:42 ` [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src Brian Norris
2016-05-13 19:43 ` [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Doug Anderson
@ 2016-05-17 21:10 ` Heiko Stuebner
2 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2016-05-17 21:10 UTC (permalink / raw)
To: Brian Norris
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-kernel,
linux-arm-kernel, linux-rockchip, Doug Anderson, Brian Norris,
Xing Zheng
Am Freitag, 13. Mai 2016, 11:42:16 schrieb Brian Norris:
> We never want to kill the GIC.
>
> Noticed when making other clock fixups, and seeing the newly-constructed
> clock tree try to disable cpll, where we had this parent structure:
>
> aclk_gic <------\
>
> |--- aclk_gic_pre <-- cpll <-- pll_cpll
>
> aclk_gic_noc <--/
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
applied both patches to my clk-fixes branch with Dougs review-tags.
Thanks
Heiko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
2016-05-16 15:49 ` Doug Anderson
@ 2016-08-01 10:08 ` Xing Zheng
0 siblings, 0 replies; 8+ messages in thread
From: Xing Zheng @ 2016-08-01 10:08 UTC (permalink / raw)
To: Doug Anderson, Brian Norris
Cc: Michael Turquette, Stephen Boyd, linux-clk, Heiko Stuebner,
linux-kernel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
Brian Norris
Hi Doug,
It is so sorry that our IC folks re-correct these bits, they need
to be recovered like these:
----
In the definition of CRU_CLKGATE_CON5:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
----
And the new TRM will be updated.
FYI.
Thanks.
On 2016年05月16日 23:49, Doug Anderson wrote:
> Hi,
>
> On Fri, May 13, 2016 at 8:36 PM, Xing Zheng <zhengxing@rock-chips.com> wrote:
>> Hi Doug,
>>
>>
>> On 2016年05月14日 04:10, Doug Anderson wrote:
>>> Hi,
>>>
>>> On Fri, May 13, 2016 at 11:42 AM, Brian Norris <briannorris@chromium.org>
>>> wrote:
>>>> From: Xing Zheng <zhengxing@rock-chips.com>
>>>>
>>>> There was a typo, swapping 'c' <--> 'g'.
>>>>
>>>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>>>> Signed-off-by: Brian Norris <briannorris@chromium.org>
>>>> ---
>>>> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/rockchip/clk-rk3399.c
>>>> b/drivers/clk/rockchip/clk-rk3399.c
>>>> index 145756c4f3c8..9f86bfef70f7 100644
>>>> --- a/drivers/clk/rockchip/clk-rk3399.c
>>>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>>>> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch
>>>> rk3399_clk_branches[] __initdata = {
>>>> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>>>>
>>>> /* perihp */
>>>> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>>> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>>> RK3399_CLKGATE_CON(5), 0, GFLAGS),
>>>> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>>> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>>> RK3399_CLKGATE_CON(5), 1, GFLAGS),
>>>> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
>>>> CLK_IGNORE_UNUSED,
>>>> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5,
>>>> DFLAGS,
>>> Definitely there was a bug since this table itself was inconsistent.
>>> ...and I _think_ this fix is correct, but I'll note that the TRM has
>>> more inconsistency here.
>>>
>>> In the big clock table 'CRU Clock Architecture Diagram', I see:
>>> CLK 4 is CPLL
>>> CLK 5 is GPLL
>>> CLK 125 is aclk_perihp_cpll_src and has 4 (CPLL) as source, with
>>> g5[0] as the bit
>>> CLK 126 is aclk_perihp_gpll_src and has 5 (GPLL) as source, with
>>> g5[1] as the bit
>>>
>>> In the definition of CRU_CLKGATE_CON5:
>>> bit 0 shows aclk_perihp_gpll_src_en
>>> bit 1 shows aclk_perihp_cpll_src_en
>>>
>>>
>>> Thus the table shows CPLL as gate5[0] and GPLL as gate5[1]. The
>>> register definition shows the opposite. I'll tend to believe the
>>> table over the register definition, but I figured I'd bring it up
>>> anyway.
>>>
>>>
>>> Xing Zheng: can you confirm that the table is correct and ask
>>> documentation folks to fix the register definition for
>>> CRU_CLKGATE_CON5?
>> Yes, previously, our IC & DOC partner confirmed that the definition of
>> CRU_CLKGATE_CON5 should be:
>> bit 0 shows aclk_perihp_cpll_src_en
>> bit 1 shows aclk_perihp_gpll_src_en
>>
>> Sorry to the incorrect register definition, we will fix them and review the
>> TRM again.
> Great!
>
> Since we now have extra confirmation that Brian's patch is indeed correct:
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>
>
>
--
- Xing Zheng
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-08-01 10:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-13 18:42 [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Brian Norris
2016-05-13 18:42 ` [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src Brian Norris
2016-05-13 20:10 ` Doug Anderson
2016-05-14 3:36 ` Xing Zheng
2016-05-16 15:49 ` Doug Anderson
2016-08-01 10:08 ` Xing Zheng
2016-05-13 19:43 ` [PATCH 1/2] clk: rockchip: mark rk3399 GIC clocks as critical Doug Anderson
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