* [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
@ 2016-06-08 7:25 Shawn Lin
2016-06-08 20:29 ` Rob Herring
2016-06-10 4:01 ` Doug Anderson
0 siblings, 2 replies; 5+ messages in thread
From: Shawn Lin @ 2016-06-08 7:25 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-kernel, linux-rockchip, Heiko Stuebner, Doug Anderson,
Wenrui Li, Rob Herring, devicetree, Shawn Lin
This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..ba8c406
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,22 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+
+Example:
+
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie_phy: phy@e220 {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ };
+};
+
--
2.3.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
2016-06-08 7:25 [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin
@ 2016-06-08 20:29 ` Rob Herring
2016-06-08 20:40 ` Heiko Stübner
2016-06-10 4:01 ` Doug Anderson
1 sibling, 1 reply; 5+ messages in thread
From: Rob Herring @ 2016-06-08 20:29 UTC (permalink / raw)
To: Shawn Lin
Cc: Kishon Vijay Abraham I, linux-kernel, linux-rockchip,
Heiko Stuebner, Doug Anderson, Wenrui Li, devicetree
gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
> +
> +Example:
> +
> +grf: syscon@ff770000 {
> + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ...
> +
> + pcie_phy: phy@e220 {
unit-address needs a reg property or drop the unit address. I'd do the
former if there's a register range you can describe here.
> + compatible = "rockchip,rk3399-pcie-phy";
> + #phy-cells = <0>;
> + };
> +};
> +
> --
> 2.3.7
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
2016-06-08 20:29 ` Rob Herring
@ 2016-06-08 20:40 ` Heiko Stübner
2016-06-12 7:38 ` Shawn Lin
0 siblings, 1 reply; 5+ messages in thread
From: Heiko Stübner @ 2016-06-08 20:40 UTC (permalink / raw)
To: Rob Herring
Cc: Shawn Lin, Kishon Vijay Abraham I, linux-kernel, linux-rockchip,
Doug Anderson, Wenrui Li, devicetree
Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring:
> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> > This patch adds a binding that describes the Rockchip PCIe PHY
> > found on Rockchip SoCs PCIe interface.
> >
> > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> > ---
> >
> > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22
> > ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt>
> > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
> > mode 100644
> > index 0000000..ba8c406
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > @@ -0,0 +1,22 @@
> > +Rockchip PCIE PHY
> > +-----------------------
> > +
> > +Required properties:
> > + - compatible: rockchip,rk3399-pcie-phy
> > + - #phy-cells: must be 0
> > +
> > +Example:
> > +
> > +grf: syscon@ff770000 {
> > + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + ...
> > +
> > + pcie_phy: phy@e220 {
>
> unit-address needs a reg property or drop the unit address. I'd do the
> former if there's a register range you can describe here.
Hmm, I think I'd suggest going the other way - call the node pcie-phy .
While the General Register Files do contain some specific address ranges (like
for the emmc phy, or some performance monitor things), the register at 0xe220
is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting
bits.
Specifying register ranges suggests some form of exclusivity to me - which is
just great for things like the emmc phy that has an actual range, but for a
device being controlled from some shared register.
Heiko
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
2016-06-08 7:25 [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin
2016-06-08 20:29 ` Rob Herring
@ 2016-06-10 4:01 ` Doug Anderson
1 sibling, 0 replies; 5+ messages in thread
From: Doug Anderson @ 2016-06-10 4:01 UTC (permalink / raw)
To: Shawn Lin
Cc: Kishon Vijay Abraham I, linux-kernel,
open list:ARM/Rockchip SoC...,
Heiko Stuebner, Wenrui Li, Rob Herring, devicetree
Shawn,
On Wed, Jun 8, 2016 at 12:25 AM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
Code also requires reset and clock.
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
2016-06-08 20:40 ` Heiko Stübner
@ 2016-06-12 7:38 ` Shawn Lin
0 siblings, 0 replies; 5+ messages in thread
From: Shawn Lin @ 2016-06-12 7:38 UTC (permalink / raw)
To: Heiko Stübner, Rob Herring
Cc: shawn.lin, devicetree, Wenrui Li, Doug Anderson, linux-kernel,
linux-rockchip, Kishon Vijay Abraham I
On 2016/6/9 4:40, Heiko Stübner wrote:
> Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring:
>> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
>>> This patch adds a binding that describes the Rockchip PCIe PHY
>>> found on Rockchip SoCs PCIe interface.
>>>
>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>> ---
>>>
>>> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22
>>> ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt>
>>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>>> b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
>>> mode 100644
>>> index 0000000..ba8c406
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>>> @@ -0,0 +1,22 @@
>>> +Rockchip PCIE PHY
>>> +-----------------------
>>> +
>>> +Required properties:
>>> + - compatible: rockchip,rk3399-pcie-phy
>>> + - #phy-cells: must be 0
>>> +
>>> +Example:
>>> +
>>> +grf: syscon@ff770000 {
>>> + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + ...
>>> +
>>> + pcie_phy: phy@e220 {
>>
>> unit-address needs a reg property or drop the unit address. I'd do the
>> former if there's a register range you can describe here.
>
> Hmm, I think I'd suggest going the other way - call the node pcie-phy .
pcie phy does not cantain a reg range, so I will drop the unit-address.
>
> While the General Register Files do contain some specific address ranges (like
> for the emmc phy, or some performance monitor things), the register at 0xe220
> is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting
> bits.
yes, we only need two bits: test_addr(for pcie phy's internal configure
address) and test_i(corresponding value for the address given) whthin
GRF_SOC_CON8 to W/R the phy.
>
> Specifying register ranges suggests some form of exclusivity to me - which is
> just great for things like the emmc phy that has an actual range, but for a
> device being controlled from some shared register.
>
>
> Heiko
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
--
Best Regards
Shawn Lin
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-06-08 7:25 [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin
2016-06-08 20:29 ` Rob Herring
2016-06-08 20:40 ` Heiko Stübner
2016-06-12 7:38 ` Shawn Lin
2016-06-10 4:01 ` Doug Anderson
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