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From: dbasehore@chromium.org
To: linux-kernel@vger.kernel.org
Cc: dbasehore@chromium.org, linux-pm@vger.kernel.org,
	rjw@rjwysocki.net, pavel@ucw.cz, len.brown@intel.com,
	tglx@linutronix.de, gnomes@lxorguk.ukuu.org.uk,
	peterz@infradead.org
Subject: [PATCH v3 1/5] x86: stub out pmc function
Date: Wed,  8 Jun 2016 20:08:54 -0700	[thread overview]
Message-ID: <1465441738-7972-2-git-send-email-dbasehore@chromium.org> (raw)
In-Reply-To: <1465441738-7972-1-git-send-email-dbasehore@chromium.org>

From: Derek Basehore <dbasehore@chromium.org>

This creates an inline function of intel_pmc_slp_s0_counter_read for
!CONFIG_INTEL_PMC_CORE.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
---
 arch/x86/include/asm/pmc_core.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/pmc_core.h b/arch/x86/include/asm/pmc_core.h
index d4855f1..786e526 100644
--- a/arch/x86/include/asm/pmc_core.h
+++ b/arch/x86/include/asm/pmc_core.h
@@ -22,6 +22,10 @@
 #define _ASM_PMC_CORE_H
 
 /* API to read SLP_S0_RESIDENCY counter */
-int intel_pmc_slp_s0_counter_read(u32 *data);
+#ifdef CONFIG_INTEL_PMC_CORE
+extern int intel_pmc_slp_s0_counter_read(u32 *data);
+#else
+static inline int intel_pmc_slp_s0_counter_read(u32 *data) { return -ENOSYS; }
+#endif
 
 #endif /* _ASM_PMC_CORE_H */
-- 
2.8.0.rc3.226.g39d4020

  reply	other threads:[~2016-06-09  3:09 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-09  3:08 [PATCH v3 0/5] Add suspend-to-idle validation for Intel SoCs dbasehore
2016-06-09  3:08 ` dbasehore [this message]
2016-06-09  3:08 ` [PATCH v3 2/5] clockevents: Add timed freeze dbasehore
2016-06-09  3:08 ` [PATCH v3 3/5] x86, apic: Add timed freeze support dbasehore
2016-06-09  3:08 ` [PATCH v3 4/5] freeze: Add error reporting dbasehore
2016-06-09  4:14   ` kbuild test robot
2016-06-09  3:08 ` [PATCH v3 5/5] intel_idle: Add S0ix validation dbasehore

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