From: Dong Aisheng <aisheng.dong@nxp.com>
To: <linux-clk@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <sboyd@codeaurora.org>,
<mturquette@baylibre.com>, <shawnguo@kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <aisheng.dong@nxp.com>,
<anson.huang@nxp.com>
Subject: [PATCH V2 1/1] clk: imx6ul: fix gpt2 clock names
Date: Mon, 13 Jun 2016 15:38:30 +0800 [thread overview]
Message-ID: <1465803510-31944-1-git-send-email-aisheng.dong@nxp.com> (raw)
In-Reply-To: <1465396420-27064-6-git-send-email-aisheng.dong@nxp.com>
fix gpt2 clock names
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/clk/imx/clk-imx6ul.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 38da5a522d58..d1d7787ce211 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -305,8 +305,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
- clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24);
- clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26);
+ clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt2_bus", "perclk", base + 0x68, 24);
+ clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26);
clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
--
1.9.1
next prev parent reply other threads:[~2016-06-13 7:44 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 14:33 [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng
2016-06-08 14:33 ` [PATCH 02/11] clk: imx: correct AV PLL rate formula Dong Aisheng
2016-06-12 11:30 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 03/11] clk: imx7d: correct dram root clk parent select Dong Aisheng
2016-06-12 11:31 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 04/11] clk: imx: correct dram pll type Dong Aisheng
2016-06-12 11:33 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Dong Aisheng
2016-06-09 7:43 ` Lothar Waßmann
2016-06-12 11:56 ` Dong Aisheng
2016-06-12 11:36 ` Shawn Guo
2016-06-12 11:51 ` Dong Aisheng
2016-06-12 12:13 ` Dong Aisheng
2016-06-12 13:29 ` Shawn Guo
2016-06-12 14:51 ` Dong Aisheng
2016-06-13 7:37 ` [PATCH V2 1/1] clk: imx: refine the powerdown " Dong Aisheng
2016-06-13 11:42 ` kbuild test robot
2016-06-13 12:24 ` [PATCH V3 " Dong Aisheng
2016-06-16 1:05 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 06/11] clk: imx6ul: fix gpt2 clock names Dong Aisheng
2016-06-12 11:41 ` Shawn Guo
2016-06-12 11:52 ` Dong Aisheng
2016-06-13 7:38 ` Dong Aisheng [this message]
2016-06-16 1:06 ` [PATCH V2 1/1] " Shawn Guo
2016-06-08 14:33 ` [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng
2016-06-12 11:43 ` Shawn Guo
2016-06-12 11:52 ` Dong Aisheng
2016-06-12 12:19 ` Dong Aisheng
2016-06-12 13:22 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 08/11] clk: imx6q: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 09/11] clk: imx6sx: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 10/11] clk: imx6sl: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 11/11] clk: imx7d: " Dong Aisheng
2016-06-12 14:56 ` [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng
2016-06-13 2:54 ` Shawn Guo
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