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* [PATCH v3 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
@ 2016-06-16  1:22 Shawn Lin
  2016-06-19 14:39 ` Rob Herring
  0 siblings, 1 reply; 2+ messages in thread
From: Shawn Lin @ 2016-06-16  1:22 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: linux-kernel, linux-rockchip, Heiko Stuebner, Doug Anderson,
	Wenrui Li, Rob Herring, devicetree, Shawn Lin

This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

---

Changes in v3:
- rename the node to pcie_phy: pcie-phy suggested by Doug

Changes in v2:
- add clk and reset description
- remove unit-address

 .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..aedca29
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,32 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+ - clocks: Must contain an entry in clock-names.
+	See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "refclk"
+ - resets: Must contain an entry in reset-names.
+	See ../reset/reset.txt for details.
+ - reset-names: Must be "phy"
+
+Example:
+
+grf: syscon@ff770000 {
+	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	...
+
+	pcie_phy: pcie-phy {
+		compatible = "rockchip,rk3399-pcie-phy";
+		#phy-cells = <0>;
+		clocks = <&cru SCLK_PCIEPHY_REF>;
+		clock-names = "refclk";
+		resets = <&cru SRST_PCIEPHY>;
+		reset-names = "phy";
+	};
+};
+
-- 
2.3.7

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH v3 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
  2016-06-16  1:22 [PATCH v3 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin
@ 2016-06-19 14:39 ` Rob Herring
  0 siblings, 0 replies; 2+ messages in thread
From: Rob Herring @ 2016-06-19 14:39 UTC (permalink / raw)
  To: Shawn Lin
  Cc: Kishon Vijay Abraham I, linux-kernel, linux-rockchip,
	Heiko Stuebner, Doug Anderson, Wenrui Li, devicetree

On Thu, Jun 16, 2016 at 09:22:46AM +0800, Shawn Lin wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> ---
> 
> Changes in v3:
> - rename the node to pcie_phy: pcie-phy suggested by Doug
> 
> Changes in v2:
> - add clk and reset description
> - remove unit-address
> 
>  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 2+ messages in thread

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