[PATCH 0/7] Add SATA3 support for Broadcom NSP SoC

[PATCH 0/7] Add SATA3 support for Broadcom NSP SoC

[Yendapally Reddy Dhananjaya Reddy]

This patch set adds support for SATA3 interface available in Broadcom
NSP SoC.

The first patch removes the "stb" references in the ahci documentation
to make it generic for Broadcom SoC's. The second patch adds NSP support
to the ahci documentation. The third patch adds the NSP SATA phy
documentation.

The fourth patch renames the Broadcom stb ahci driver to common Broadcom
ahci driver and fifth patch supports NSP ahci. The sixth patch adds
support for NSP SATA3 phy.

The seventh patch contains the device tree changes for NSP SoC.

This patch set has been tested on NSP bcm958625HR board.
This patch set is based on v4.7.0-rc1 and is available from github
repo: https://github.com/Broadcom/cygnus-linux.git
branch: nsp-sata-v1

Yendapally Reddy Dhananjaya Reddy (7):
  dt-bindings: ata: rename brcm,sata-brcmstb.txt to brcm,sata-brcm.txt
  dt-bindings: ata: add support for Broadcom NSP SoC ahci
  dt-bindings: phy: Add documentation for NSP SATA PHY
  ata: ahci_brcmstb: rename to support across Broadcom SoC's
  ata: ahci_brcm: Add support for Broadcom NSP SoC
  phy: Add SATA3 PHY support for Broadcom NSP SoC
  ARM: dts: nsp: Add sata device tree entry

 .../{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt}  |  9 +--
 .../devicetree/bindings/phy/brcm-sata-phy.txt      |  4 +-
 arch/arm/boot/dts/bcm-nsp.dtsi                     | 42 +++++++++++
 arch/arm/boot/dts/bcm958625k.dts                   | 12 ++++
 drivers/ata/Kconfig                                |  8 +--
 drivers/ata/Makefile                               |  2 +-
 drivers/ata/{ahci_brcmstb.c => ahci_brcm.c}        | 46 +++++++++---
 drivers/phy/phy-brcm-sata.c                        | 81 ++++++++++++++++++++++
 8 files changed, 184 insertions(+), 20 deletions(-)
 rename Documentation/devicetree/bindings/ata/{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt} (81%)
 rename drivers/ata/{ahci_brcmstb.c => ahci_brcm.c} (91%)

-- 
2.1.0

[PATCH 1/7] dt-bindings: ata: rename brcm,sata-brcmstb.txt to brcm,sata-brcm.txt

[Yendapally Reddy Dhananjaya Reddy]

Renames the dt bindings document of Broadcom STB ahci driver to
common Broadcom ahci driver bindings document

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 .../bindings/ata/{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt}    | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
 rename Documentation/devicetree/bindings/ata/{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt} (81%)

diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
similarity index 81%
rename from Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
rename to Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
index 6087283..126ee13 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
@@ -1,13 +1,13 @@
-* Broadcom SATA3 AHCI Controller for STB
+* Broadcom SATA3 AHCI Controller
 
 SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
 - compatible         : should be one or more of
-                       "brcm,bcm7425-ahci"
-                       "brcm,bcm7445-ahci"
-                       "brcm,sata3-ahci"
+			"brcm,bcm7425-ahci"
+			"brcm,bcm7445-ahci"
+			"brcm,sata3-ahci"
 - reg                : register mappings for AHCI and SATA_TOP_CTRL
 - reg-names          : "ahci" and "top-ctrl"
 - interrupts         : interrupt mapping for SATA IRQ
-- 
2.1.0

Re: [PATCH 1/7] dt-bindings: ata: rename brcm,sata-brcmstb.txt to brcm,sata-brcm.txt

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Renames the dt bindings document of Broadcom STB ahci driver to
> common Broadcom ahci driver bindings document
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 1/7] dt-bindings: ata: rename brcm,sata-brcmstb.txt to brcm,sata-brcm.txt

[Rob Herring]

On Thu, Jun 16, 2016 at 09:53:29AM -0400, Yendapally Reddy Dhananjaya Reddy wrote:
> Renames the dt bindings document of Broadcom STB ahci driver to
> common Broadcom ahci driver bindings document
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
> ---
>  .../bindings/ata/{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt}    | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>  rename Documentation/devicetree/bindings/ata/{brcm,sata-brcmstb.txt => brcm,sata-brcm.txt} (81%)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 2/7] dt-bindings: ata: add support for Broadcom NSP SoC ahci

[Yendapally Reddy Dhananjaya Reddy]

Add support for Broadcom NSP SoC ahci

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
index 126ee13..0a5b3b4 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible         : should be one or more of
 			"brcm,bcm7425-ahci"
 			"brcm,bcm7445-ahci"
+			"brcm,bcm-nsp-ahci"
 			"brcm,sata3-ahci"
 - reg                : register mappings for AHCI and SATA_TOP_CTRL
 - reg-names          : "ahci" and "top-ctrl"
-- 
2.1.0

Re: [PATCH 2/7] dt-bindings: ata: add support for Broadcom NSP SoC ahci

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Add support for Broadcom NSP SoC ahci
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 2/7] dt-bindings: ata: add support for Broadcom NSP SoC ahci

[Rob Herring]

On Thu, Jun 16, 2016 at 09:53:30AM -0400, Yendapally Reddy Dhananjaya Reddy wrote:
> Add support for Broadcom NSP SoC ahci
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
> ---
>  Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 3/7] dt-bindings: phy: Add documentation for NSP SATA PHY

[Yendapally Reddy Dhananjaya Reddy]

Add documentation for SATA PHY available in Broadcom's
NSP SoC.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
index d023120..6ccce09 100644
--- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
@@ -5,6 +5,7 @@ Required properties:
      "brcm,bcm7425-sata-phy"
      "brcm,bcm7445-sata-phy"
      "brcm,iproc-ns2-sata-phy"
+     "brcm,iproc-nsp-sata-phy"
      "brcm,phy-sata3"
 - address-cells: should be 1
 - size-cells: should be 0
@@ -22,7 +23,8 @@ Sub-nodes required properties:
 
 Sub-nodes optional properties:
 - brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
-     This property is not applicable for "brcm,iproc-ns2-sata-phy".
+     This property is not applicable for "brcm,iproc-ns2-sata-phy" and
+     "brcm,iproc-nsp-sata-phy".
 
 Example:
 	sata-phy@f0458100 {
-- 
2.1.0

Re: [PATCH 3/7] dt-bindings: phy: Add documentation for NSP SATA PHY

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Add documentation for SATA PHY available in Broadcom's
> NSP SoC.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 3/7] dt-bindings: phy: Add documentation for NSP SATA PHY

[Kishon Vijay Abraham I]

On Thursday 16 June 2016 07:23 PM, Yendapally Reddy Dhananjaya Reddy wrote:
> Add documentation for SATA PHY available in Broadcom's
> NSP SoC.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
> index d023120..6ccce09 100644
> --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
> @@ -5,6 +5,7 @@ Required properties:
>       "brcm,bcm7425-sata-phy"
>       "brcm,bcm7445-sata-phy"
>       "brcm,iproc-ns2-sata-phy"
> +     "brcm,iproc-nsp-sata-phy"
>       "brcm,phy-sata3"
>  - address-cells: should be 1
>  - size-cells: should be 0
> @@ -22,7 +23,8 @@ Sub-nodes required properties:
>  
>  Sub-nodes optional properties:
>  - brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
> -     This property is not applicable for "brcm,iproc-ns2-sata-phy".
> +     This property is not applicable for "brcm,iproc-ns2-sata-phy" and
> +     "brcm,iproc-nsp-sata-phy".
>  
>  Example:
>  	sata-phy@f0458100 {
> 

Re: [PATCH 3/7] dt-bindings: phy: Add documentation for NSP SATA PHY

[Rob Herring]

On Thu, Jun 16, 2016 at 09:53:31AM -0400, Yendapally Reddy Dhananjaya Reddy wrote:
> Add documentation for SATA PHY available in Broadcom's
> NSP SoC.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
> ---
>  Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 4/7] ata: ahci_brcmstb: rename to support across Broadcom SoC's

[Yendapally Reddy Dhananjaya Reddy]

Rename the existing Broadcom STB ahci driver to common
Broadcom SATA3 driver to share this across Broadcom SoCs.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 drivers/ata/Kconfig                         | 6 +++---
 drivers/ata/Makefile                        | 2 +-
 drivers/ata/{ahci_brcmstb.c => ahci_brcm.c} | 0
 3 files changed, 4 insertions(+), 4 deletions(-)
 rename drivers/ata/{ahci_brcmstb.c => ahci_brcm.c} (100%)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index e2dc4c0..8fe06e6 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -98,12 +98,12 @@ config SATA_AHCI_PLATFORM
 
 	  If unsure, say N.
 
-config AHCI_BRCMSTB
-	tristate "Broadcom STB AHCI SATA support"
+config AHCI_BRCM
+	tristate "Broadcom AHCI SATA support"
 	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	help
 	  This option enables support for the AHCI SATA3 controller found on
-	  STB SoC's.
+	  Broadcom SoC's.
 
 	  If unsure, say N.
 
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 0b2afb7..a46e6b7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
 obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
-obj-$(CONFIG_AHCI_BRCMSTB)	+= ahci_brcmstb.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_BRCM)		+= ahci_brcm.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_CEVA)		+= ahci_ceva.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DA850)	+= ahci_da850.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_IMX)		+= ahci_imx.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcm.c
similarity index 100%
rename from drivers/ata/ahci_brcmstb.c
rename to drivers/ata/ahci_brcm.c
-- 
2.1.0

Re: [PATCH 4/7] ata: ahci_brcmstb: rename to support across Broadcom SoC's

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Rename the existing Broadcom STB ahci driver to common
> Broadcom SATA3 driver to share this across Broadcom SoCs.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

There is currently nothing referencing AHCI_BRCMSTB in the in-tree
defconfigs, but we should coordinate this change with this patch:

https://patchwork.kernel.org/patch/9130007/

which I have queued locally to send for 4.8, if we know this is going to
be accepted for 4.8, then I can update the patch above.

Other than that:

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH 5/7] ata: ahci_brcm: Add support for Broadcom NSP SoC

[Yendapally Reddy Dhananjaya Reddy]

Add SATA3 support for Broadcom NSP SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 drivers/ata/Kconfig     |  2 +-
 drivers/ata/ahci_brcm.c | 46 ++++++++++++++++++++++++++++++++++++----------
 2 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 8fe06e6..2c8be74 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM
 
 config AHCI_BRCM
 	tristate "Broadcom AHCI SATA support"
-	depends on ARCH_BRCMSTB || BMIPS_GENERIC
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP
 	help
 	  This option enables support for the AHCI SATA3 controller found on
 	  Broadcom SoC's.
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index e87bcec..6f8a734 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -71,6 +71,12 @@
 	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\
 	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
 
+enum brcm_ahci_version {
+	BRCM_SATA_BCM7425 = 1,
+	BRCM_SATA_BCM7445,
+	BRCM_SATA_NSP,
+};
+
 enum brcm_ahci_quirks {
 	BRCM_AHCI_QUIRK_NO_NCQ		= BIT(0),
 	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE	= BIT(1),
@@ -81,6 +87,7 @@ struct brcm_ahci_priv {
 	void __iomem *top_ctrl;
 	u32 port_mask;
 	u32 quirks;
+	enum brcm_ahci_version version;
 };
 
 static const struct ata_port_info ahci_brcm_port_info = {
@@ -247,9 +254,19 @@ static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
 
 static void brcm_sata_init(struct brcm_ahci_priv *priv)
 {
+	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
+
 	/* Configure endianness */
-	brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
-			   priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+	if (priv->version ==  BRCM_SATA_NSP) {
+		u32 data = brcm_sata_readreg(ctrl);
+
+		data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) |
+			(0x03 << DMADESC_ENDIAN_SHIFT));
+		data |= (0x02 << DMADATA_ENDIAN_SHIFT) |
+			(0x02 << DMADESC_ENDIAN_SHIFT);
+		brcm_sata_writereg(data, ctrl);
+	} else
+		brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -282,8 +299,17 @@ static struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
+static const struct of_device_id ahci_of_match[] = {
+	{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
+	{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
+	{},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
 static int brcm_ahci_probe(struct platform_device *pdev)
 {
+	const struct of_device_id *of_id;
 	struct device *dev = &pdev->dev;
 	struct brcm_ahci_priv *priv;
 	struct ahci_host_priv *hpriv;
@@ -293,6 +319,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
+
+	of_id = of_match_node(ahci_of_match, pdev->dev.of_node);
+	if (!of_id)
+		return -ENODEV;
+
+	priv->version = (enum brcm_ahci_version)of_id->data;
 	priv->dev = dev;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
@@ -300,7 +332,8 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->top_ctrl))
 		return PTR_ERR(priv->top_ctrl);
 
-	if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
+	if ((priv->version == BRCM_SATA_BCM7425) ||
+		(priv->version == BRCM_SATA_NSP)) {
 		priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
 		priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
 	}
@@ -354,13 +387,6 @@ static int brcm_ahci_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id ahci_of_match[] = {
-	{.compatible = "brcm,bcm7425-ahci"},
-	{.compatible = "brcm,bcm7445-ahci"},
-	{},
-};
-MODULE_DEVICE_TABLE(of, ahci_of_match);
-
 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
 
 static struct platform_driver brcm_ahci_driver = {
-- 
2.1.0

Re: [PATCH 5/7] ata: ahci_brcm: Add support for Broadcom NSP SoC

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Add SATA3 support for Broadcom NSP SoC
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH 6/7] phy: Add SATA3 PHY support for Broadcom NSP SoC

[Yendapally Reddy Dhananjaya Reddy]

This patch adds support for Broadcom NSP SATA3 PHY in existing
Broadcom SATA PHY driver.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 drivers/phy/phy-brcm-sata.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/drivers/phy/phy-brcm-sata.c b/drivers/phy/phy-brcm-sata.c
index 6c4c5cb..18d6626 100644
--- a/drivers/phy/phy-brcm-sata.c
+++ b/drivers/phy/phy-brcm-sata.c
@@ -45,6 +45,7 @@ enum brcm_sata_phy_version {
 	BRCM_SATA_PHY_STB_28NM,
 	BRCM_SATA_PHY_STB_40NM,
 	BRCM_SATA_PHY_IPROC_NS2,
+	BRCM_SATA_PHY_IPROC_NSP,
 };
 
 struct brcm_sata_port {
@@ -73,6 +74,13 @@ enum sata_phy_regs {
 
 	PLL_REG_BANK_0				= 0x050,
 	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,
+	PLLCONTROL_0_FREQ_DET_RESTART		= BIT(13),
+	PLLCONTROL_0_FREQ_MONITOR		= BIT(12),
+	PLLCONTROL_0_SEQ_START			= BIT(15),
+	PLL_CAP_CONTROL				= 0x85,
+	PLL_ACTRL2				= 0x8b,
+	PLL_ACTRL2_SELDIV_MASK			= 0x1f,
+	PLL_ACTRL2_SELDIV_SHIFT			= 9,
 
 	PLL1_REG_BANK				= 0x060,
 	PLL1_ACTRL2				= 0x82,
@@ -80,6 +88,7 @@ enum sata_phy_regs {
 	PLL1_ACTRL4				= 0x84,
 
 	OOB_REG_BANK				= 0x150,
+	OOB1_REG_BANK				= 0x160,
 	OOB_CTRL1				= 0x80,
 	OOB_CTRL1_BURST_MAX_MASK		= 0xf,
 	OOB_CTRL1_BURST_MAX_SHIFT		= 12,
@@ -271,6 +280,73 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
 	return 0;
 }
 
+static int brcm_nsp_sata_init(struct brcm_sata_port *port)
+{
+	struct brcm_sata_phy *priv = port->phy_priv;
+	struct device *dev = port->phy_priv->dev;
+	void __iomem *base = priv->phy_base;
+	unsigned int oob_bank;
+	unsigned int val, try;
+
+	/* Configure OOB control */
+	if (port->portnum == 0)
+		oob_bank = OOB_REG_BANK;
+	else if (port->portnum == 1)
+		oob_bank = OOB1_REG_BANK;
+	else
+		return -EINVAL;
+
+	val = 0x0;
+	val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
+	val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
+	val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
+	val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
+	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
+
+	val = 0x0;
+	val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
+	val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
+	val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
+	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
+
+
+	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
+		~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
+		0x0c << PLL_ACTRL2_SELDIV_SHIFT);
+
+	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
+						0xff0, 0x4f0);
+
+	val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
+	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+								~val, val);
+	val = PLLCONTROL_0_SEQ_START;
+	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+								~val, 0);
+	mdelay(10);
+	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+								~val, val);
+
+	/* Wait for pll_seq_done bit */
+	try = 50;
+	while (try--) {
+		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+					BLOCK0_XGXSSTATUS);
+		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
+			break;
+		msleep(20);
+	}
+	if (!try) {
+		/* PLL did not lock; give up */
+		dev_err(dev, "port%d PLL did not lock\n", port->portnum);
+		return -ETIMEDOUT;
+	}
+
+	dev_dbg(dev, "port%d initialized\n", port->portnum);
+
+	return 0;
+}
+
 static int brcm_sata_phy_init(struct phy *phy)
 {
 	int rc;
@@ -284,6 +360,9 @@ static int brcm_sata_phy_init(struct phy *phy)
 	case BRCM_SATA_PHY_IPROC_NS2:
 		rc = brcm_ns2_sata_init(port);
 		break;
+	case BRCM_SATA_PHY_IPROC_NSP:
+		rc = brcm_nsp_sata_init(port);
+		break;
 	default:
 		rc = -ENODEV;
 	};
@@ -303,6 +382,8 @@ static const struct of_device_id brcm_sata_phy_of_match[] = {
 	  .data = (void *)BRCM_SATA_PHY_STB_40NM },
 	{ .compatible	= "brcm,iproc-ns2-sata-phy",
 	  .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
+	{ .compatible = "brcm,iproc-nsp-sata-phy",
+	  .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
-- 
2.1.0

Re: [PATCH 6/7] phy: Add SATA3 PHY support for Broadcom NSP SoC

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> This patch adds support for Broadcom NSP SATA3 PHY in existing
> Broadcom SATA PHY driver.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 6/7] phy: Add SATA3 PHY support for Broadcom NSP SoC

[Kishon Vijay Abraham I]

On Thursday 16 June 2016 07:23 PM, Yendapally Reddy Dhananjaya Reddy wrote:
> This patch adds support for Broadcom NSP SATA3 PHY in existing
> Broadcom SATA PHY driver.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/phy/phy-brcm-sata.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
> 
> diff --git a/drivers/phy/phy-brcm-sata.c b/drivers/phy/phy-brcm-sata.c
> index 6c4c5cb..18d6626 100644
> --- a/drivers/phy/phy-brcm-sata.c
> +++ b/drivers/phy/phy-brcm-sata.c
> @@ -45,6 +45,7 @@ enum brcm_sata_phy_version {
>  	BRCM_SATA_PHY_STB_28NM,
>  	BRCM_SATA_PHY_STB_40NM,
>  	BRCM_SATA_PHY_IPROC_NS2,
> +	BRCM_SATA_PHY_IPROC_NSP,
>  };
>  
>  struct brcm_sata_port {
> @@ -73,6 +74,13 @@ enum sata_phy_regs {
>  
>  	PLL_REG_BANK_0				= 0x050,
>  	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,
> +	PLLCONTROL_0_FREQ_DET_RESTART		= BIT(13),
> +	PLLCONTROL_0_FREQ_MONITOR		= BIT(12),
> +	PLLCONTROL_0_SEQ_START			= BIT(15),
> +	PLL_CAP_CONTROL				= 0x85,
> +	PLL_ACTRL2				= 0x8b,
> +	PLL_ACTRL2_SELDIV_MASK			= 0x1f,
> +	PLL_ACTRL2_SELDIV_SHIFT			= 9,
>  
>  	PLL1_REG_BANK				= 0x060,
>  	PLL1_ACTRL2				= 0x82,
> @@ -80,6 +88,7 @@ enum sata_phy_regs {
>  	PLL1_ACTRL4				= 0x84,
>  
>  	OOB_REG_BANK				= 0x150,
> +	OOB1_REG_BANK				= 0x160,
>  	OOB_CTRL1				= 0x80,
>  	OOB_CTRL1_BURST_MAX_MASK		= 0xf,
>  	OOB_CTRL1_BURST_MAX_SHIFT		= 12,
> @@ -271,6 +280,73 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
>  	return 0;
>  }
>  
> +static int brcm_nsp_sata_init(struct brcm_sata_port *port)
> +{
> +	struct brcm_sata_phy *priv = port->phy_priv;
> +	struct device *dev = port->phy_priv->dev;
> +	void __iomem *base = priv->phy_base;
> +	unsigned int oob_bank;
> +	unsigned int val, try;
> +
> +	/* Configure OOB control */
> +	if (port->portnum == 0)
> +		oob_bank = OOB_REG_BANK;
> +	else if (port->portnum == 1)
> +		oob_bank = OOB1_REG_BANK;
> +	else
> +		return -EINVAL;
> +
> +	val = 0x0;
> +	val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
> +	val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
> +	val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
> +	val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
> +	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
> +
> +	val = 0x0;
> +	val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
> +	val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
> +	val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
> +	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
> +
> +
> +	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
> +		~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
> +		0x0c << PLL_ACTRL2_SELDIV_SHIFT);
> +
> +	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
> +						0xff0, 0x4f0);
> +
> +	val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
> +	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
> +								~val, val);
> +	val = PLLCONTROL_0_SEQ_START;
> +	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
> +								~val, 0);
> +	mdelay(10);
> +	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
> +								~val, val);
> +
> +	/* Wait for pll_seq_done bit */
> +	try = 50;
> +	while (try--) {
> +		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
> +					BLOCK0_XGXSSTATUS);
> +		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
> +			break;
> +		msleep(20);
> +	}
> +	if (!try) {
> +		/* PLL did not lock; give up */
> +		dev_err(dev, "port%d PLL did not lock\n", port->portnum);
> +		return -ETIMEDOUT;
> +	}
> +
> +	dev_dbg(dev, "port%d initialized\n", port->portnum);
> +
> +	return 0;
> +}
> +
>  static int brcm_sata_phy_init(struct phy *phy)
>  {
>  	int rc;
> @@ -284,6 +360,9 @@ static int brcm_sata_phy_init(struct phy *phy)
>  	case BRCM_SATA_PHY_IPROC_NS2:
>  		rc = brcm_ns2_sata_init(port);
>  		break;
> +	case BRCM_SATA_PHY_IPROC_NSP:
> +		rc = brcm_nsp_sata_init(port);
> +		break;
>  	default:
>  		rc = -ENODEV;
>  	};
> @@ -303,6 +382,8 @@ static const struct of_device_id brcm_sata_phy_of_match[] = {
>  	  .data = (void *)BRCM_SATA_PHY_STB_40NM },
>  	{ .compatible	= "brcm,iproc-ns2-sata-phy",
>  	  .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
> +	{ .compatible = "brcm,iproc-nsp-sata-phy",
> +	  .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> 

[PATCH 7/7] ARM: dts: nsp: Add sata device tree entry

[Yendapally Reddy Dhananjaya Reddy]

Add sata support to the Northstar Plus SoC device tree.

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi   | 42 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm958625k.dts | 12 ++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index def9e78..71ececf 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -266,6 +266,48 @@
 			      <0x30028 0x04>,
 			      <0x3f408 0x04>;
 		};
+
+		sata_phy: sata_phy@40100 {
+			compatible = "brcm,iproc-nsp-sata-phy";
+			reg = <0x40100 0x340>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		sata: ahci@41000 {
+			compatible = "brcm,bcm-nsp-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x41000 0x1000>, <0x40020 0x1c>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+				phy-names = "sata-phy";
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+				phy-names = "sata-phy";
+			};
+		};
 	};
 
 	pcie0: pcie@18012000 {
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index e298450..2d84226 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -68,6 +68,18 @@
 	status = "okay";
 };
 
+&sata_phy0 {
+	status = "okay";
+};
+
+&sata_phy1 {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
 &nand {
 	nandcs@0 {
 		compatible = "brcm,nandcs";
-- 
2.1.0

Re: [PATCH 7/7] ARM: dts: nsp: Add sata device tree entry

[Florian Fainelli]

On 06/16/2016 06:53 AM, Yendapally Reddy Dhananjaya Reddy wrote:
> Add sata support to the Northstar Plus SoC device tree.
> 
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 0/7] Add SATA3 support for Broadcom NSP SoC

[Tejun Heo]

On Thu, Jun 16, 2016 at 09:53:28AM -0400, Yendapally Reddy Dhananjaya Reddy wrote:
> This patch set adds support for SATA3 interface available in Broadcom
> NSP SoC.

Applied 1-7 to libata/for-4.8.  If any should be routed differently,
please let me know.

Thanks.

-- 
tejun