From: <tthayer@opensource.altera.com>
To: <bp@alien8.de>, <dougthompson@xmission.com>,
<m.chehab@samsung.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux@arm.linux.org.uk>, <dinguyen@opensource.altera.com>,
<grant.likely@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <tthayer.linux@gmail.com>,
<tthayer@opensource.altera.com>
Subject: [PATCHv5 2/8] EDAC, altera: Add panic flag check to A10 IRQ
Date: Wed, 22 Jun 2016 08:58:53 -0500 [thread overview]
Message-ID: <1466603939-7526-3-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1466603939-7526-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peripheral FIFO buffers will not cause a kernel panic
on DBERRs because the packet can be retried and therefore
recovered.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 New patch. Add panic flag to IRQ function.
v3 No change
v4 Add reasons to panic on DBERR in OCRAM.
v5 No change
---
drivers/edac/altera_edac.c | 9 ++++++++-
drivers/edac/altera_edac.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 0101dd0..75451bc 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -897,7 +897,8 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
writel(ALTR_A10_ECC_DERRPENA,
base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
- panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+ if (dci->data->panic)
+ panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
return IRQ_HANDLED;
}
@@ -936,6 +937,12 @@ const struct edac_device_prv_data a10_ocramecc_data = {
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject_fops,
+ /*
+ * OCRAM panic on uncorrectable error because sleep/resume
+ * functions and FPGA contents are stored in OCRAM. Prefer
+ * a kernel panic over executing/loading corrupted data.
+ */
+ .panic = true,
};
#endif /* CONFIG_EDAC_ALTERA_OCRAM */
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 62b0fa0..cf4e8cb 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -298,6 +298,7 @@ struct edac_device_prv_data {
irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
int trig_alloc_sz;
const struct file_operations *inject_fops;
+ bool panic;
};
struct altr_edac_device_dev {
--
1.7.9.5
next prev parent reply other threads:[~2016-06-22 13:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-22 13:58 [PATCHv5 0/8] Add Ethernet EDAC & peripheral init functions tthayer
2016-06-22 13:58 ` [PATCHv5 1/8] EDAC, altera: Check parent status for Arria10 EDAC block tthayer
2016-06-22 13:58 ` tthayer [this message]
2016-06-22 13:58 ` [PATCHv5 3/8] EDAC, altera: Make all private data structures static const tthayer
2016-06-22 13:58 ` [PATCHv5 4/8] EDAC, altera: Share Arria10 check_deps & IRQ functions tthayer
2016-06-22 13:58 ` [PATCHv5 5/8] Documentation: dt: socfpga: Add Arria10 Ethernet binding tthayer
2016-06-24 17:07 ` Rob Herring
2016-06-22 13:58 ` [PATCHv5 6/8] EDAC, altera: Add Arria10 ECC memory init functions tthayer
2016-06-22 13:58 ` [PATCHv5 7/8] EDAC, altera: Add Arria10 Ethernet EDAC support tthayer
2016-06-22 13:58 ` [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry tthayer
2016-06-27 15:31 ` Dinh Nguyen
2016-06-27 16:18 ` Borislav Petkov
2016-06-27 16:13 ` Dinh Nguyen
2016-06-27 17:54 ` Borislav Petkov
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