From: <tthayer@opensource.altera.com>
To: <bp@alien8.de>, <dougthompson@xmission.com>,
<m.chehab@samsung.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux@arm.linux.org.uk>, <dinguyen@opensource.altera.com>,
<grant.likely@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <tthayer.linux@gmail.com>,
<tthayer@opensource.altera.com>
Subject: [PATCHv5 5/8] Documentation: dt: socfpga: Add Arria10 Ethernet binding
Date: Wed, 22 Jun 2016 08:58:56 -0500 [thread overview]
Message-ID: <1466603939-7526-6-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1466603939-7526-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent node.
v5 Change parent phandle name to altr,ecc-parent
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 15eb0df..b545856 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -82,6 +82,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+Ethernet FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-eth-mac-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent Ethernet node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -108,4 +116,20 @@ Example:
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH> ;
};
+
+ emac0-rx-ecc@ff8c0800 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0800 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+ <36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@ff8c0c00 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0c00 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+ <37 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
--
1.7.9.5
next prev parent reply other threads:[~2016-06-22 13:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-22 13:58 [PATCHv5 0/8] Add Ethernet EDAC & peripheral init functions tthayer
2016-06-22 13:58 ` [PATCHv5 1/8] EDAC, altera: Check parent status for Arria10 EDAC block tthayer
2016-06-22 13:58 ` [PATCHv5 2/8] EDAC, altera: Add panic flag check to A10 IRQ tthayer
2016-06-22 13:58 ` [PATCHv5 3/8] EDAC, altera: Make all private data structures static const tthayer
2016-06-22 13:58 ` [PATCHv5 4/8] EDAC, altera: Share Arria10 check_deps & IRQ functions tthayer
2016-06-22 13:58 ` tthayer [this message]
2016-06-24 17:07 ` [PATCHv5 5/8] Documentation: dt: socfpga: Add Arria10 Ethernet binding Rob Herring
2016-06-22 13:58 ` [PATCHv5 6/8] EDAC, altera: Add Arria10 ECC memory init functions tthayer
2016-06-22 13:58 ` [PATCHv5 7/8] EDAC, altera: Add Arria10 Ethernet EDAC support tthayer
2016-06-22 13:58 ` [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry tthayer
2016-06-27 15:31 ` Dinh Nguyen
2016-06-27 16:18 ` Borislav Petkov
2016-06-27 16:13 ` Dinh Nguyen
2016-06-27 17:54 ` Borislav Petkov
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