From: Jianxin Pan <jianxin.pan@amlogic.com>
To: Yixun Lan <dlan@gentoo.org>, Jerome Brunet <jbrunet@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
Rob Herring <robh@kernel.org>,
Hanjie Lin <hanjie.lin@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Yixun Lan <yixun.lan@amlogic.com>, <linux-kernel@vger.kernel.org>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Liang Yang <liang.yang@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Carlo Caione <carlo@caione.org>,
<linux-amlogic@lists.infradead.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Qiufang Dai <qiufang.dai@amlogic.com>
Subject: Re: [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller
Date: Thu, 25 Oct 2018 19:50:11 +0800 [thread overview]
Message-ID: <146f13c1-f309-d619-602b-b14535ab5f79@amlogic.com> (raw)
In-Reply-To: <20181024145513.GA6647@ofant>
On 2018/10/25 15:29, Yixun Lan wrote:
> Hi Jerome, Jianxin:
>
> see my comments
>
> On 10:58 Wed 24 Oct , Jerome Brunet wrote:
>> On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
>>> From: Yixun Lan <yixun.lan@amlogic.com>
>>>
>>> Document the MMC sub clock controller driver, the potential consumer
>>> of this driver is MMC or NAND. Also add four clock bindings IDs which
>>> provided by this driver.
>>>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>> ---
>>> .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 31 ++++++++++++++++++++++
>>> include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++++++++++++
>>> 2 files changed, 48 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>> create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>> new file mode 100644
>>> index 0000000..9e6d343
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
>>> @@ -0,0 +1,31 @@
>>> +* Amlogic MMC Sub Clock Controller Driver
>>> +
>>> +The Amlogic MMC clock controller generates and supplies clock to support
>>> +MMC and NAND controller
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: should be:
>>> + "amlogic,gx-mmc-clkc"
>>> + "amlogic,axg-mmc-clkc"
>>> +
>>> +- #clock-cells: should be 1.
>>> +- clocks: phandles to clocks corresponding to the clock-names property
>>> +- clock-names: list of parent clock names
>>> + - "clkin0", "clkin1"
>>> +
>>> +Parent node should have the following properties :
>>> +- compatible: "amlogic,axg-mmc-clkc", "syscon".
>>> +- reg: base address and size of the MMC control register space.
>>
>> I get why Stephen is confused by your description, I am too. The example
>> contradict the documentation.
>>
>> The documentation above says that the parent node should be a syscon with the
>> mmc register space.
>>
>> But your example shows this in the node itself.
>>
>
> yes, I think the documentation need to be fixed
ok, Thankyou. I will fix it in the next version.
>
> for the final solution, we decide to make 'mmc-clkc' an independent node
> instead of being a sub-node of 'mmc', so both of them may exist in parallel..
>
> the DT part may like this:
>
> sd_emmc_c_clkc: clock-controller@7000 {
> compatible = "amlogic,axg-mmc-clkc", "syscon";
> reg = <0x0 0x7000 0x0 0x4>;
> ...
> };
>
> sd_emmc_c: mmc@7000 {
> compatible = "amlogic,axg-mmc";
> reg = <0x0 0x7000 0x0 0x800>;
> ...
> };
>
>
>>> +
>>> +Example: Clock controller node:
>>> +
>>> +sd_mmc_c_clkc: clock-controller@7000 {
>>> + compatible = "amlogic,axg-mmc-clkc", "syscon";
>>> + reg = <0x0 0x7000 0x0 0x4>;
>>> + #clock-cells = <1>;
>>> +
>>> + clock-names = "clkin0", "clkin1";
>>> + clocks = <&clkc CLKID_SD_MMC_C_CLK0>,
>>> + <&clkc CLKID_FCLK_DIV2>;
>>> +};
>>> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>>> new file mode 100644
>>> index 0000000..162b949
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>>> @@ -0,0 +1,17 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> +/*
>>> + * Meson MMC sub clock tree IDs
>>> + *
>>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>>> + * Author: Yixun Lan <yixun.lan@amlogic.com>
>>> + */
>>> +
>>> +#ifndef __MMC_CLKC_H
>>> +#define __MMC_CLKC_H
>>> +
>>> +#define CLKID_MMC_DIV 1
>>> +#define CLKID_MMC_PHASE_CORE 2
>>> +#define CLKID_MMC_PHASE_TX 3
>>> +#define CLKID_MMC_PHASE_RX 4
>>> +
>>> +#endif
>>
>>
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
next prev parent reply other threads:[~2018-10-25 11:50 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 5:07 [PATCH v5 0/3] clk: meson: add a sub EMMC clock controller support Jianxin Pan
2018-10-18 5:07 ` [PATCH v5 1/3] clk: meson: add emmc sub clock phase delay driver Jianxin Pan
2018-10-18 17:14 ` Stephen Boyd
2018-10-24 8:58 ` Jerome Brunet
2018-10-24 10:57 ` Jianxin Pan
2018-10-18 5:07 ` [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller Jianxin Pan
2018-10-18 17:08 ` Stephen Boyd
2018-10-19 15:50 ` Jianxin Pan
2018-10-19 18:04 ` Stephen Boyd
2018-10-22 6:05 ` Jianxin Pan
2018-10-24 8:58 ` Jerome Brunet
2018-10-25 7:29 ` Yixun Lan
2018-10-25 11:50 ` Jianxin Pan [this message]
2018-11-04 3:04 ` Stephen Boyd
2018-11-04 15:39 ` Jianxin Pan
2018-10-18 5:07 ` [PATCH v5 3/3] clk: meson: add sub MMC clock controller driver Jianxin Pan
2018-10-18 17:13 ` Stephen Boyd
2018-10-19 16:12 ` Jianxin Pan
2018-10-19 18:03 ` Stephen Boyd
2018-10-22 5:59 ` Jianxin Pan
2018-10-24 9:00 ` Jerome Brunet
2018-10-24 6:29 ` Jianxin Pan
2018-10-24 8:47 ` Stephen Boyd
2018-10-24 8:51 ` Jianxin Pan
2018-10-24 9:01 ` Jerome Brunet
2018-10-25 11:48 ` Jianxin Pan
2018-10-25 12:54 ` Jerome Brunet
2018-10-25 20:58 ` Martin Blumenstingl
2018-10-28 19:16 ` Jerome Brunet
2018-10-29 19:45 ` Martin Blumenstingl
2018-10-30 13:41 ` Jianxin Pan
2018-11-03 18:01 ` Jianxin Pan
2018-11-05 9:46 ` jbrunet
2018-11-05 11:29 ` Jianxin Pan
2018-10-28 15:12 ` Jianxin Pan
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