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From: Stephen Boyd <sboyd@kernel.org>
To: Jerome Brunet <jbrunet@baylibre.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	Neil Armstrong <narmstrong@baylibre.com>
Cc: Yixun Lan <yixun.lan@amlogic.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Carlo Caione <carlo@caione.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Boris Brezillon <boris.brezillon@bootlin.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Liang Yang <liang.yang@amlogic.com>,
	Jian Hu <jian.hu@amlogic.com>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	Hanjie Lin <hanjie.lin@amlogic.com>,
	Victor Wan <victor.wan@amlogic.com>,
	linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 3/3] clk: meson: add sub MMC clock controller driver
Date: Fri, 19 Oct 2018 11:03:29 -0700	[thread overview]
Message-ID: <153997220960.53599.2059896905852359614@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <01d07c83-b17e-70b5-6e9b-8150ee3aedf2@amlogic.com>

Quoting Jianxin Pan (2018-10-19 09:12:53)
> On 2018/10/19 1:13, Stephen Boyd wrote:
> > Quoting Jianxin Pan (2018-10-17 22:07:25)
> >> diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
> >> index 305ee30..f96314d 100644
> >> --- a/drivers/clk/meson/clk-regmap.c
> >> +++ b/drivers/clk/meson/clk-regmap.c
> >> @@ -113,8 +113,25 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
> >>                                   clk_div_mask(div->width) << div->shift, val);
> >>  };
> >>  
> >> -/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
> >> +static void clk_regmap_div_init(struct clk_hw *hw)
> >> +{
> >> +       struct clk_regmap *clk = to_clk_regmap(hw);
> >> +       struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> >> +       unsigned int val;
> >> +       int ret;
> >> +
> >> +       ret = regmap_read(clk->map, div->offset, &val);
> >> +       if (ret)
> >> +               return;
> >>  
> >> +       val &= (clk_div_mask(div->width) << div->shift);
> >> +       if (!val)
> >> +               regmap_update_bits(clk->map, div->offset,
> >> +                                  clk_div_mask(div->width) << div->shift,
> >> +                                  clk_div_mask(div->width));
> >> +}
> >> +
> >> +/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
> > 
> > We should add a patch to rename the symbol for qcom, i.e.
> > qcom_clk_regmap_div_ro_ops, and then any symbols in this directory
> > should be meson_clk_regmap_div_ro_ops.
> "/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */"
> This comment is not introduced in this patch.
> I followed the naming style in this file and add clk_regmap_divider_with_init_ops.
> 
> @Jerome, What's your suggestion about this?

Yes you don't need to fix anything in this series. Just saying that in
the future we should work on cleaning this up.


  reply	other threads:[~2018-10-19 18:03 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-18  5:07 [PATCH v5 0/3] clk: meson: add a sub EMMC clock controller support Jianxin Pan
2018-10-18  5:07 ` [PATCH v5 1/3] clk: meson: add emmc sub clock phase delay driver Jianxin Pan
2018-10-18 17:14   ` Stephen Boyd
2018-10-24  8:58   ` Jerome Brunet
2018-10-24 10:57     ` Jianxin Pan
2018-10-18  5:07 ` [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller Jianxin Pan
2018-10-18 17:08   ` Stephen Boyd
2018-10-19 15:50     ` Jianxin Pan
2018-10-19 18:04       ` Stephen Boyd
2018-10-22  6:05         ` Jianxin Pan
2018-10-24  8:58   ` Jerome Brunet
2018-10-25  7:29     ` Yixun Lan
2018-10-25 11:50       ` Jianxin Pan
2018-11-04  3:04       ` Stephen Boyd
2018-11-04 15:39         ` Jianxin Pan
2018-10-18  5:07 ` [PATCH v5 3/3] clk: meson: add sub MMC clock controller driver Jianxin Pan
2018-10-18 17:13   ` Stephen Boyd
2018-10-19 16:12     ` Jianxin Pan
2018-10-19 18:03       ` Stephen Boyd [this message]
2018-10-22  5:59         ` Jianxin Pan
2018-10-24  9:00         ` Jerome Brunet
2018-10-24  6:29     ` Jianxin Pan
2018-10-24  8:47       ` Stephen Boyd
2018-10-24  8:51         ` Jianxin Pan
2018-10-24  9:01   ` Jerome Brunet
2018-10-25 11:48     ` Jianxin Pan
2018-10-25 12:54       ` Jerome Brunet
2018-10-25 20:58         ` Martin Blumenstingl
2018-10-28 19:16           ` Jerome Brunet
2018-10-29 19:45             ` Martin Blumenstingl
2018-10-30 13:41             ` Jianxin Pan
2018-11-03 18:01             ` Jianxin Pan
2018-11-05  9:46               ` jbrunet
2018-11-05 11:29                 ` Jianxin Pan
2018-10-28 15:12         ` Jianxin Pan

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