* arm64: Implement IPI based TLB invalidation
@ 2016-08-04 9:15 Matthias Brugger
2016-08-04 9:15 ` [PATCH 1/4] arm64: insn: Do not disable irqs during patching Matthias Brugger
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Matthias Brugger @ 2016-08-04 9:15 UTC (permalink / raw)
To: pbonzini, rkrcmar, christoffer.dall, marc.zyngier, linux,
catalin.marinas, will.deacon
Cc: suzuki.poulose, james.morse, david.daney, rrichter, agraf,
mbrugger, mark.rutland, lorenzo.pieralisi, dave.long,
ard.biesheuvel, zlim.lnx, kvm, linux-arm-kernel, kvmarm,
linux-kernel
This patch set adds a workaround for arm64 if the hardware didn't
implement the TLB invalidation via broadcast TLBI properly.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/4] arm64: insn: Do not disable irqs during patching
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
@ 2016-08-04 9:15 ` Matthias Brugger
2016-08-04 9:15 ` [PATCH 2/4] arm64: Implement IPI based TLB invalidation Matthias Brugger
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Matthias Brugger @ 2016-08-04 9:15 UTC (permalink / raw)
To: pbonzini, rkrcmar, christoffer.dall, marc.zyngier, linux,
catalin.marinas, will.deacon
Cc: suzuki.poulose, james.morse, david.daney, rrichter, agraf,
mbrugger, mark.rutland, lorenzo.pieralisi, dave.long,
ard.biesheuvel, zlim.lnx, kvm, linux-arm-kernel, kvmarm,
linux-kernel
From: Robert Richter <rrichter@cavium.com>
__aarch64_insn_write() is always called with interrupts enabled. Thus,
there is no need to use an irqsave variant for the spin lock.
This change should also address the fix of:
commit abffa6f3b157 ("arm64: convert patch_lock to raw lock")
We need to enable interrupts to allow cpu sync for code patching
using smp_call_function*().
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm64/kernel/insn.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 63f9432..138bd8a 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -86,7 +86,7 @@ bool aarch64_insn_is_branch_imm(u32 insn)
aarch64_insn_is_bcond(insn));
}
-static DEFINE_RAW_SPINLOCK(patch_lock);
+static DEFINE_SPINLOCK(patch_lock);
static void __kprobes *patch_map(void *addr, int fixmap)
{
@@ -129,16 +129,15 @@ int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
static int __kprobes __aarch64_insn_write(void *addr, u32 insn)
{
void *waddr = addr;
- unsigned long flags = 0;
int ret;
- raw_spin_lock_irqsave(&patch_lock, flags);
+ spin_lock(&patch_lock);
waddr = patch_map(addr, FIX_TEXT_POKE0);
ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
patch_unmap(FIX_TEXT_POKE0);
- raw_spin_unlock_irqrestore(&patch_lock, flags);
+ spin_unlock(&patch_lock);
return ret;
}
--
2.6.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] arm64: Implement IPI based TLB invalidation
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
2016-08-04 9:15 ` [PATCH 1/4] arm64: insn: Do not disable irqs during patching Matthias Brugger
@ 2016-08-04 9:15 ` Matthias Brugger
2016-08-04 9:15 ` [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support Matthias Brugger
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Matthias Brugger @ 2016-08-04 9:15 UTC (permalink / raw)
To: pbonzini, rkrcmar, christoffer.dall, marc.zyngier, linux,
catalin.marinas, will.deacon
Cc: suzuki.poulose, james.morse, david.daney, rrichter, agraf,
mbrugger, mark.rutland, lorenzo.pieralisi, dave.long,
ard.biesheuvel, zlim.lnx, kvm, linux-arm-kernel, kvmarm,
linux-kernel
Hardware may lack a sane implementation of TLB invalidation
using broadcast TLBI command. Add a capability to enable TLB
invalidation using IPI.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm64/include/asm/cpufeature.h | 3 +-
arch/arm64/include/asm/tlbflush.h | 94 ++++++++++++++++++++++++++++++++-----
arch/arm64/mm/flush.c | 46 ++++++++++++++++++
3 files changed, 129 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 49dd1bd..c4bf72b 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -36,8 +36,9 @@
#define ARM64_HAS_VIRT_HOST_EXTN 11
#define ARM64_WORKAROUND_CAVIUM_27456 12
#define ARM64_HAS_32BIT_EL0 13
+#define ARM64_HAS_NO_BCAST_TLBI 14
-#define ARM64_NCAPS 14
+#define ARM64_NCAPS 15
#ifndef __ASSEMBLY__
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index b460ae2..edc5495 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -71,7 +71,10 @@ static inline void local_flush_tlb_all(void)
isb();
}
-static inline void flush_tlb_all(void)
+void __flush_tlb_all_ipi(void);
+void __flush_tlb_mm_ipi(struct mm_struct *mm);
+
+static inline void __flush_tlb_all_tlbi(void)
{
dsb(ishst);
asm("tlbi vmalle1is");
@@ -79,7 +82,17 @@ static inline void flush_tlb_all(void)
isb();
}
-static inline void flush_tlb_mm(struct mm_struct *mm)
+static inline void flush_tlb_all(void)
+{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_all_ipi();
+ return;
+ }
+
+ __flush_tlb_all_tlbi();
+}
+
+static inline void __flush_tlb_mm_tlbi(struct mm_struct *mm)
{
unsigned long asid = ASID(mm) << 48;
@@ -88,8 +101,18 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
dsb(ish);
}
-static inline void flush_tlb_page(struct vm_area_struct *vma,
- unsigned long uaddr)
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_mm_ipi(mm);
+ return;
+ }
+
+ __flush_tlb_mm_tlbi(mm);
+}
+
+static inline void __flush_tlb_page_tlbi(struct vm_area_struct *vma,
+ unsigned long uaddr)
{
unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48);
@@ -98,15 +121,26 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
dsb(ish);
}
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long uaddr)
+{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_mm_ipi(vma->vm_mm);
+ return;
+ }
+
+ __flush_tlb_page_tlbi(vma, uaddr);
+}
+
/*
* This is meant to avoid soft lock-ups on large TLB flushing ranges and not
* necessarily a performance improvement.
*/
#define MAX_TLB_RANGE (1024UL << PAGE_SHIFT)
-static inline void __flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end,
- bool last_level)
+static inline void __flush_tlb_range_tlbi(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end,
+ bool last_level)
{
unsigned long asid = ASID(vma->vm_mm) << 48;
unsigned long addr;
@@ -129,13 +163,26 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
dsb(ish);
}
+static inline void __flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end,
+ bool last_level)
+{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_mm_ipi(vma->vm_mm);
+ return;
+ }
+
+ __flush_tlb_range_tlbi(vma, start, end, last_level);
+}
+
static inline void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
+ unsigned long start, unsigned long end)
{
__flush_tlb_range(vma, start, end, false);
}
-static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+static inline void __flush_tlb_kernel_range_tlbi(unsigned long start,
+ unsigned long end)
{
unsigned long addr;
@@ -154,17 +201,38 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
isb();
}
+static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_all_ipi();
+ return;
+ }
+
+ __flush_tlb_kernel_range_tlbi(start, end);
+}
+
+static inline void __flush_tlb_pgtable_tlbi(struct mm_struct *mm,
+ unsigned long uaddr)
+{
+ unsigned long addr = uaddr >> 12 | (ASID(mm) << 48);
+
+ asm("tlbi vae1is, %0" : : "r" (addr));
+ dsb(ish);
+}
+
/*
* Used to invalidate the TLB (walk caches) corresponding to intermediate page
* table levels (pgd/pud/pmd).
*/
static inline void __flush_tlb_pgtable(struct mm_struct *mm,
- unsigned long uaddr)
+ unsigned long uaddr)
{
- unsigned long addr = uaddr >> 12 | (ASID(mm) << 48);
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ __flush_tlb_mm_ipi(mm);
+ return;
+ }
- asm("tlbi vae1is, %0" : : "r" (addr));
- dsb(ish);
+ __flush_tlb_pgtable_tlbi(mm, uaddr);
}
#endif
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index 43a76b0..402036a 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -27,6 +27,24 @@
#include "mm.h"
+static void flush_tlb_local(void *info)
+{
+ local_flush_tlb_all();
+}
+
+static void flush_tlb_mm_local(void *info)
+{
+ unsigned long asid = (unsigned long)info;
+
+ asm volatile("\n"
+ " dsb nshst\n"
+ " tlbi aside1, %0\n"
+ " dsb nsh\n"
+ " isb sy"
+ : : "r" (asid)
+ );
+}
+
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
@@ -90,6 +108,34 @@ void flush_dcache_page(struct page *page)
}
EXPORT_SYMBOL(flush_dcache_page);
+void __flush_tlb_mm_ipi(struct mm_struct *mm)
+{
+ unsigned long asid;
+
+ if (!mm) {
+ flush_tlb_all();
+ } else {
+ asid = ASID(mm) << 48;
+ /* Make sure page table modifications are visible. */
+ dsb(ishst);
+ /* IPI to all CPUs to do local flush. */
+ on_each_cpu(flush_tlb_mm_local, (void *)asid, 1);
+ }
+}
+EXPORT_SYMBOL(__flush_tlb_mm_ipi);
+
+void __flush_tlb_all_ipi(void)
+{
+ /* Make sure page table modifications are visible. */
+ dsb(ishst);
+ if (num_online_cpus() <= 1)
+ local_flush_tlb_all();
+ else
+ /* IPI to all CPUs to do local flush. */
+ on_each_cpu(flush_tlb_local, NULL, 1);
+}
+EXPORT_SYMBOL(__flush_tlb_all_ipi);
+
/*
* Additional functions defined in assembly.
*/
--
2.6.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
2016-08-04 9:15 ` [PATCH 1/4] arm64: insn: Do not disable irqs during patching Matthias Brugger
2016-08-04 9:15 ` [PATCH 2/4] arm64: Implement IPI based TLB invalidation Matthias Brugger
@ 2016-08-04 9:15 ` Matthias Brugger
2016-08-06 7:22 ` kbuild test robot
2016-08-04 9:15 ` [PATCH 4/4] arm64: hibernate: " Matthias Brugger
2016-08-04 20:57 ` [PATCH] arm64: Add workaround for Cavium erratum 26026 Robert Richter
4 siblings, 1 reply; 11+ messages in thread
From: Matthias Brugger @ 2016-08-04 9:15 UTC (permalink / raw)
To: pbonzini, rkrcmar, christoffer.dall, marc.zyngier, linux,
catalin.marinas, will.deacon
Cc: suzuki.poulose, james.morse, david.daney, rrichter, agraf,
mbrugger, mark.rutland, lorenzo.pieralisi, dave.long,
ard.biesheuvel, zlim.lnx, kvm, linux-arm-kernel, kvmarm,
linux-kernel
KVM awaits a working broadcast TLBI implementation.
Error out early when this is not provided by the
hardware.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/kvm/arm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f1bde7c..e627fac 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -1376,6 +1376,11 @@ int kvm_arch_init(void *opaque)
int err;
int ret, cpu;
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ kvm_err("Missing broadcast TLBI support.\n");
+ return -ENODEV;
+ }
+
if (!is_hyp_mode_available()) {
kvm_err("HYP mode not available\n");
return -ENODEV;
--
2.6.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] arm64: hibernate: Check for broadcast TLBI support
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
` (2 preceding siblings ...)
2016-08-04 9:15 ` [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support Matthias Brugger
@ 2016-08-04 9:15 ` Matthias Brugger
2016-08-04 20:57 ` [PATCH] arm64: Add workaround for Cavium erratum 26026 Robert Richter
4 siblings, 0 replies; 11+ messages in thread
From: Matthias Brugger @ 2016-08-04 9:15 UTC (permalink / raw)
To: pbonzini, rkrcmar, christoffer.dall, marc.zyngier, linux,
catalin.marinas, will.deacon
Cc: suzuki.poulose, james.morse, david.daney, rrichter, agraf,
mbrugger, mark.rutland, lorenzo.pieralisi, dave.long,
ard.biesheuvel, zlim.lnx, kvm, linux-arm-kernel, kvmarm,
linux-kernel
Hibernation makes use of broadcast TLBI. Error out
early when this is not supported by the hardware.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm64/kernel/hibernate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index 21ab5df..7269642 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -481,6 +481,11 @@ static int check_boot_cpu_online_pm_callback(struct notifier_block *nb,
static int __init check_boot_cpu_online_init(void)
{
+ if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
+ pr_err("Can't hibernate: missing broadcast TLBI support.\n");
+ return -EINVAL;
+ }
+
/*
* Set this pm_notifier callback with a lower priority than
* cpu_hotplug_pm_callback, so that cpu_hotplug_pm_callback will be
--
2.6.6
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] arm64: Add workaround for Cavium erratum 26026
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
` (3 preceding siblings ...)
2016-08-04 9:15 ` [PATCH 4/4] arm64: hibernate: " Matthias Brugger
@ 2016-08-04 20:57 ` Robert Richter
2016-08-04 21:40 ` David Daney
2016-08-05 2:35 ` kbuild test robot
4 siblings, 2 replies; 11+ messages in thread
From: Robert Richter @ 2016-08-04 20:57 UTC (permalink / raw)
To: marc.zyngier, linux, catalin.marinas, will.deacon
Cc: pbonzini, rkrcmar, christoffer.dall, Matthias Brugger,
suzuki.poulose, james.morse, david.daney, agraf, mark.rutland,
lorenzo.pieralisi, dave.long, ard.biesheuvel, zlim.lnx, kvm,
linux-arm-kernel, kvmarm, linux-kernel
The patch below is on top of Matthias' patch series:
arm64: Implement IPI based TLB invalidation
The series is used to enable a workaround for Cavium ThunderX pass 1.x
systems.
-Robert
>From abb99ee83473d9ecffb4fdaae9c69435ca670bc8 Mon Sep 17 00:00:00 2001
From: Robert Richter <rrichter@cavium.com>
Date: Fri, 29 Jul 2016 09:40:04 +0200
Subject: [PATCH] arm64: Add workaround for Cavium erratum 26026
STX may return a wrong status value if the store was successful.
This may happen on ThunderX T88 pass 1.x cpus if a broadcast TLBI is
executed on another cpu in parallel to an STX. As a result atomic or
non-blocking implementations can behave incorrectly. Use IPIs that
call local TLBIs on other cpus to avoid this.
Applies to ThunderX T88 pass 1.x cpus.
Signed-off-by: Robert Richter <rrichter@cavium.com>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 14 ++++++++++++++
arch/arm64/kernel/cpu_errata.c | 8 ++++++++
3 files changed, 23 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4da60b463995..0d870d934528 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -58,5 +58,6 @@ stable kernels.
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
+| Cavium | ThunderX Core | #26026 | CAVIUM_ERRATUM_26026 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5a0a691d4220..8cbd9043ec6f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -457,6 +457,20 @@ config CAVIUM_ERRATUM_23154
If unsure, say Y.
+config CAVIUM_ERRATUM_26026
+ bool "Cavium erratum 26026: STX may return wrong status value"
+ default y
+ help
+ STX may return a wrong status value if the store was
+ successful. This may happen on ThunderX T88 pass 1.x cpus if
+ a broadcast TLBI is executed on another cpu in parallel to
+ an STX. As a result atomic or non-blocking implementations
+ can behave incorrectly. Use IPIs that call local TLBIs on
+ other cpus to avoid this.
+ Applies to ThunderX T88 pass 1.x cpus.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_27456
bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
default y
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index af716b65110d..1e1753a6408e 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -90,6 +90,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
},
#endif
+#ifdef CONFIG_CAVIUM_ERRATUM_26026
+ {
+ /* Cavium ThunderX, pass 1.x */
+ .desc = "Cavium erratum 26026",
+ .capability = ARM64_HAS_NO_BCAST_TLBI,
+ MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
+ },
+#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
{
/* Cavium ThunderX, T88 pass 1.x - 2.1 */
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] arm64: Add workaround for Cavium erratum 26026
2016-08-04 20:57 ` [PATCH] arm64: Add workaround for Cavium erratum 26026 Robert Richter
@ 2016-08-04 21:40 ` David Daney
2016-08-05 7:00 ` Robert Richter
2016-08-05 2:35 ` kbuild test robot
1 sibling, 1 reply; 11+ messages in thread
From: David Daney @ 2016-08-04 21:40 UTC (permalink / raw)
To: Robert Richter
Cc: marc.zyngier, linux, catalin.marinas, will.deacon, mark.rutland,
Matthias Brugger, kvm, suzuki.poulose, zlim.lnx, rkrcmar,
david.daney, agraf, linux-kernel, ard.biesheuvel,
lorenzo.pieralisi, james.morse, dave.long, pbonzini, kvmarm,
christoffer.dall, linux-arm-kernel
On 08/04/2016 01:57 PM, Robert Richter wrote:
> The patch below is on top of Matthias' patch series:
>
> arm64: Implement IPI based TLB invalidation
>
> The series is used to enable a workaround for Cavium ThunderX pass 1.x
> systems.
Where are the rest of the patches in the series? I would have expected
something like "[PATCH 1/X] arm64:..." with X being greater than one.
>
> -Robert
>
>
>
> From abb99ee83473d9ecffb4fdaae9c69435ca670bc8 Mon Sep 17 00:00:00 2001
> From: Robert Richter <rrichter@cavium.com>
> Date: Fri, 29 Jul 2016 09:40:04 +0200
> Subject: [PATCH] arm64: Add workaround for Cavium erratum 26026
>
> STX may return a wrong status value if the store was successful.
>
> This may happen on ThunderX T88 pass 1.x cpus if a broadcast TLBI is
> executed on another cpu in parallel to an STX. As a result atomic or
> non-blocking implementations can behave incorrectly. Use IPIs that
> call local TLBIs on other cpus to avoid this.
>
> Applies to ThunderX T88 pass 1.x cpus.
>
> Signed-off-by: Robert Richter <rrichter@cavium.com>
> ---
> Documentation/arm64/silicon-errata.txt | 1 +
> arch/arm64/Kconfig | 14 ++++++++++++++
> arch/arm64/kernel/cpu_errata.c | 8 ++++++++
> 3 files changed, 23 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 4da60b463995..0d870d934528 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -58,5 +58,6 @@ stable kernels.
> | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
> | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
> | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
> +| Cavium | ThunderX Core | #26026 | CAVIUM_ERRATUM_26026 |
> | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
> | Cavium | ThunderX SMMUv2 | #27704 | N/A |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 5a0a691d4220..8cbd9043ec6f 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -457,6 +457,20 @@ config CAVIUM_ERRATUM_23154
>
> If unsure, say Y.
>
> +config CAVIUM_ERRATUM_26026
> + bool "Cavium erratum 26026: STX may return wrong status value"
> + default y
> + help
> + STX may return a wrong status value if the store was
> + successful. This may happen on ThunderX T88 pass 1.x cpus if
> + a broadcast TLBI is executed on another cpu in parallel to
> + an STX. As a result atomic or non-blocking implementations
> + can behave incorrectly. Use IPIs that call local TLBIs on
> + other cpus to avoid this.
> + Applies to ThunderX T88 pass 1.x cpus.
> +
> + If unsure, say Y.
> +
> config CAVIUM_ERRATUM_27456
> bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
> default y
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index af716b65110d..1e1753a6408e 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -90,6 +90,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
> },
> #endif
> +#ifdef CONFIG_CAVIUM_ERRATUM_26026
> + {
> + /* Cavium ThunderX, pass 1.x */
> + .desc = "Cavium erratum 26026",
> + .capability = ARM64_HAS_NO_BCAST_TLBI,
> + MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
> + },
> +#endif
> #ifdef CONFIG_CAVIUM_ERRATUM_27456
> {
> /* Cavium ThunderX, T88 pass 1.x - 2.1 */
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] arm64: Add workaround for Cavium erratum 26026
2016-08-04 20:57 ` [PATCH] arm64: Add workaround for Cavium erratum 26026 Robert Richter
2016-08-04 21:40 ` David Daney
@ 2016-08-05 2:35 ` kbuild test robot
1 sibling, 0 replies; 11+ messages in thread
From: kbuild test robot @ 2016-08-05 2:35 UTC (permalink / raw)
To: Robert Richter
Cc: kbuild-all, marc.zyngier, linux, catalin.marinas, will.deacon,
pbonzini, rkrcmar, christoffer.dall, Matthias Brugger,
suzuki.poulose, james.morse, david.daney, agraf, mark.rutland,
lorenzo.pieralisi, dave.long, ard.biesheuvel, zlim.lnx, kvm,
linux-arm-kernel, kvmarm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1501 bytes --]
Hi Robert,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.7 next-20160804]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Robert-Richter/arm64-Add-workaround-for-Cavium-erratum-26026/20160805-083523
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> arch/arm64/kernel/cpu_errata.c:99:17: error: 'ARM64_HAS_NO_BCAST_TLBI' undeclared here (not in a function)
.capability = ARM64_HAS_NO_BCAST_TLBI,
^
vim +/ARM64_HAS_NO_BCAST_TLBI +99 arch/arm64/kernel/cpu_errata.c
93 },
94 #endif
95 #ifdef CONFIG_CAVIUM_ERRATUM_26026
96 {
97 /* Cavium ThunderX, pass 1.x */
98 .desc = "Cavium erratum 26026",
> 99 .capability = ARM64_HAS_NO_BCAST_TLBI,
100 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
101 },
102 #endif
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 28771 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] arm64: Add workaround for Cavium erratum 26026
2016-08-04 21:40 ` David Daney
@ 2016-08-05 7:00 ` Robert Richter
2016-08-05 16:37 ` David Daney
0 siblings, 1 reply; 11+ messages in thread
From: Robert Richter @ 2016-08-05 7:00 UTC (permalink / raw)
To: David Daney
Cc: marc.zyngier, linux, catalin.marinas, will.deacon, mark.rutland,
Matthias Brugger, kvm, suzuki.poulose, zlim.lnx, rkrcmar,
david.daney, agraf, linux-kernel, ard.biesheuvel,
lorenzo.pieralisi, james.morse, dave.long, pbonzini, kvmarm,
christoffer.dall, linux-arm-kernel
On 04.08.16 14:40:48, David Daney wrote:
> On 08/04/2016 01:57 PM, Robert Richter wrote:
> >The patch below is on top of Matthias' patch series:
> >
> > arm64: Implement IPI based TLB invalidation
> >
> >The series is used to enable a workaround for Cavium ThunderX pass 1.x
> >systems.
>
>
> Where are the rest of the patches in the series? I would have expected
> something like "[PATCH 1/X] arm64:..." with X being greater than one.
You are cc'ed here too:
https://lkml.org/lkml/2016/8/4/101
-Robert
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] arm64: Add workaround for Cavium erratum 26026
2016-08-05 7:00 ` Robert Richter
@ 2016-08-05 16:37 ` David Daney
0 siblings, 0 replies; 11+ messages in thread
From: David Daney @ 2016-08-05 16:37 UTC (permalink / raw)
To: Robert Richter
Cc: marc.zyngier, linux, catalin.marinas, will.deacon, mark.rutland,
Matthias Brugger, kvm, suzuki.poulose, zlim.lnx, rkrcmar,
david.daney, agraf, linux-kernel, ard.biesheuvel,
lorenzo.pieralisi, james.morse, dave.long, pbonzini, kvmarm,
christoffer.dall, linux-arm-kernel
On 08/05/2016 12:00 AM, Robert Richter wrote:
> On 04.08.16 14:40:48, David Daney wrote:
>> On 08/04/2016 01:57 PM, Robert Richter wrote:
>>> The patch below is on top of Matthias' patch series:
>>>
>>> arm64: Implement IPI based TLB invalidation
>>>
>>> The series is used to enable a workaround for Cavium ThunderX pass 1.x
>>> systems.
>>
>>
>> Where are the rest of the patches in the series? I would have expected
>> something like "[PATCH 1/X] arm64:..." with X being greater than one.
>
> You are cc'ed here too:
>
> https://lkml.org/lkml/2016/8/4/101
>
OK, I got confused by the fact that this patch was retroactively added
to the patch set and was missing the sequence numbering.
> -Robert
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support
2016-08-04 9:15 ` [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support Matthias Brugger
@ 2016-08-06 7:22 ` kbuild test robot
0 siblings, 0 replies; 11+ messages in thread
From: kbuild test robot @ 2016-08-06 7:22 UTC (permalink / raw)
To: Matthias Brugger
Cc: kbuild-all, pbonzini, rkrcmar, christoffer.dall, marc.zyngier,
linux, catalin.marinas, will.deacon, suzuki.poulose, james.morse,
david.daney, rrichter, agraf, mbrugger, mark.rutland,
lorenzo.pieralisi, dave.long, ard.biesheuvel, zlim.lnx, kvm,
linux-arm-kernel, kvmarm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1886 bytes --]
Hi Matthias,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.7]
[cannot apply to next-20160805]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Matthias-Brugger/arm64-insn-Do-not-disable-irqs-during-patching/20160804-172016
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm-axm55xx_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
arch/arm/kvm/arm.c: In function 'kvm_arch_init':
>> arch/arm/kvm/arm.c:1378:6: error: implicit declaration of function 'cpus_have_cap' [-Werror=implicit-function-declaration]
if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
^
>> arch/arm/kvm/arm.c:1378:20: error: 'ARM64_HAS_NO_BCAST_TLBI' undeclared (first use in this function)
if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
^
arch/arm/kvm/arm.c:1378:20: note: each undeclared identifier is reported only once for each function it appears in
cc1: some warnings being treated as errors
vim +/cpus_have_cap +1378 arch/arm/kvm/arm.c
1372 */
1373 int kvm_arch_init(void *opaque)
1374 {
1375 int err;
1376 int ret, cpu;
1377
> 1378 if (cpus_have_cap(ARM64_HAS_NO_BCAST_TLBI)) {
1379 kvm_err("Missing broadcast TLBI support.\n");
1380 return -ENODEV;
1381 }
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 19020 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-08-06 20:51 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-04 9:15 arm64: Implement IPI based TLB invalidation Matthias Brugger
2016-08-04 9:15 ` [PATCH 1/4] arm64: insn: Do not disable irqs during patching Matthias Brugger
2016-08-04 9:15 ` [PATCH 2/4] arm64: Implement IPI based TLB invalidation Matthias Brugger
2016-08-04 9:15 ` [PATCH 3/4] KVM: arm/arm64: Check for broadcast TLBI support Matthias Brugger
2016-08-06 7:22 ` kbuild test robot
2016-08-04 9:15 ` [PATCH 4/4] arm64: hibernate: " Matthias Brugger
2016-08-04 20:57 ` [PATCH] arm64: Add workaround for Cavium erratum 26026 Robert Richter
2016-08-04 21:40 ` David Daney
2016-08-05 7:00 ` Robert Richter
2016-08-05 16:37 ` David Daney
2016-08-05 2:35 ` kbuild test robot
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