[Patch v2 0/3] misc: pch_phub: Add quirks for MIPS Boston platform

[Patch v2 0/3] misc: pch_phub: Add quirks for MIPS Boston platform

[Zubair Lutfullah Kakakhel]

Hi,

These are a few patches for using the EG20T UART on the Imagination
Technologies Boston development platform

2 quirks needed
- Pass a specific value for the prefetch register from DT instead of using
the hard-coded default.
- Add a quirk for using the internal 25MHz clock source for the UART block

The patches for Boston platform are inflight.
https://patchwork.kernel.org/patch/8200941/

So pasting a DT node snippet here.

+                                       eg20t_pch@2,0,0 {
+                                               compatible = "pci8086,8801";
+                                               reg = <0x00020000 0 0 0 0>;
+
+                                               intel,eg20t-prefetch = <0>;
+                                       };
+                                       eg20t_uart0@02,10,1 {
+                                               compatible = "pci8086,8811";
+                                               reg = <0x00025100 0 0 0 0>;
+
+                                               clock-frequency = <25000000>;
+                                       };

Suggestions and feedback welcome.

Based on v4.8-rc1

Regards,
ZubairLK

Zubair Lutfullah Kakakhel (3):
  misc: pch_phub: Read prefetch value from device tree if passed
  misc: pch_phub: Add UART_CLK quirk for Boston platform
  serial: pch_uart: Add support for reading clock-frequency from DT

 drivers/misc/pch_phub.c       | 20 +++++++++++++++++++-
 drivers/tty/serial/Kconfig    |  2 +-
 drivers/tty/serial/pch_uart.c |  5 +++++
 3 files changed, 25 insertions(+), 2 deletions(-)

-- 
1.9.1

[Patch v2 1/3] misc: pch_phub: Read prefetch value from device tree if passed

[Zubair Lutfullah Kakakhel]

The default prefetch value for the eg20t device is hard coded to
0x000affaa.

Add support for an alternative to be read from DT if available

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>

---
V1 -> V2
added #include <linux/of.h>
---
 drivers/misc/pch_phub.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c
index 4810e03..1dd18f5 100644
--- a/drivers/misc/pch_phub.c
+++ b/drivers/misc/pch_phub.c
@@ -28,6 +28,7 @@
 #include <linux/if_ether.h>
 #include <linux/ctype.h>
 #include <linux/dmi.h>
+#include <linux/of.h>
 
 #define PHUB_STATUS 0x00		/* Status Register offset */
 #define PHUB_CONTROL 0x04		/* Control Register offset */
@@ -711,6 +712,12 @@ static int pch_phub_probe(struct pci_dev *pdev,
 
 	if (id->driver_data == 1) { /* EG20T PCH */
 		const char *board_name;
+		unsigned int prefetch = 0x000affaa;
+
+		if (pdev->dev.of_node)
+			of_property_read_u32(pdev->dev.of_node,
+						  "intel,eg20t-prefetch",
+						  &prefetch);
 
 		ret = sysfs_create_file(&pdev->dev.kobj,
 					&dev_attr_pch_mac.attr);
@@ -736,7 +743,7 @@ static int pch_phub_probe(struct pci_dev *pdev,
 						CLKCFG_UART_MASK);
 
 		/* set the prefech value */
-		iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
+		iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
 		/* set the interrupt delay value */
 		iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 		chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
-- 
1.9.1

[Patch v2 2/3] misc: pch_phub: Add UART_CLK quirk for Boston platform

[Zubair Lutfullah Kakakhel]

The EG20T has 4 UART blocks. The clock source for the UART block is
configured to receive a clock from an external pin by default.

An internal 25MHz clock in the EG20T can also be used as a clock source
for the clock.

The MIPS based Boston platform ties the external clock pin down and relies
on the internal clock source for the UART to function.

Boston is based on device tree.

Add a quirk to allow Boston to be detected via device tree and set the
correct clock source for UART.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>

---
V1 -> V2

no change
---
 drivers/misc/pch_phub.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c
index 1dd18f5..e42bdc9 100644
--- a/drivers/misc/pch_phub.c
+++ b/drivers/misc/pch_phub.c
@@ -58,6 +58,7 @@
 
 /* CM-iTC */
 #define CLKCFG_UART_48MHZ			(1 << 16)
+#define CLKCFG_UART_25MHZ			(2 << 16)
 #define CLKCFG_BAUDDIV				(2 << 20)
 #define CLKCFG_PLL2VCO				(8 << 9)
 #define CLKCFG_UARTCLKSEL			(1 << 18)
@@ -748,6 +749,16 @@ static int pch_phub_probe(struct pci_dev *pdev,
 		iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 		chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 		chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
+
+		/* quirk for MIPS Boston platform */
+		if (pdev->dev.of_node) {
+			if (of_machine_is_compatible("img,boston")) {
+				pch_phub_read_modify_write_reg(chip,
+					(unsigned int)CLKCFG_REG_OFFSET,
+					CLKCFG_UART_25MHZ,
+					CLKCFG_UART_MASK);
+			}
+		}
 	} else if (id->driver_data == 2) { /* ML7213 IOH */
 		ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 		if (ret)
-- 
1.9.1

[Patch v2 3/3] serial: pch_uart: Add support for reading clock-frequency from DT

[Zubair Lutfullah Kakakhel]

The MIPS based Boston platform provides a 25MHz clock to the UART.

Enable the driver for MIPS and add support in the driver to read
the frequency from device tree.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>

---
V1 -> V2

Added #include <linux/of.h>
---
 drivers/tty/serial/Kconfig    | 2 +-
 drivers/tty/serial/pch_uart.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 518db24a..c783140 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1380,7 +1380,7 @@ config SERIAL_IFX6X60
 
 config SERIAL_PCH_UART
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) UART"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS ||  COMPILE_TEST)
 	select SERIAL_CORE
 	help
 	  This driver is for PCH(Platform controller Hub) UART of Intel EG20T
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index ea4ffc2..23672f8 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -31,6 +31,7 @@
 #include <linux/dmi.h>
 #include <linux/nmi.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 
 #include <linux/debugfs.h>
 #include <linux/dmaengine.h>
@@ -1826,6 +1827,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
 	priv->trigger_level = 1;
 	priv->fcr = 0;
 
+	if (pdev->dev.of_node)
+		of_property_read_u32(pdev->dev.of_node, "clock-frequency"
+					 , &user_uartclk);
+
 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 	pch_uart_ports[board->line_no] = priv;
 #endif
-- 
1.9.1