* [PATCH V1 0/3] Refactor Loongson1 clock
@ 2016-09-19 4:38 Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Keguang Zhang @ 2016-09-19 4:38 UTC (permalink / raw)
To: linux-clk, linux-mips, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patchset is to refactor Loongson1 clock,
and update Loongson1B clocks.
This applies on top of clk-next.
Thanks!
Changelog:
v1:
Rebase the patch on clk: ls1x: Migrate to clk_hw based OF
and registration APIs.
Kelvin Cheung (3):
clk: Loongson1: Refactor Loongson1 clock
clk: Loongson1: Update clocks of Loongson1B
clk: Loongson1: Make use of GENMASK
drivers/clk/Makefile | 2 +-
drivers/clk/loongson1/Makefile | 2 +
.../clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} | 74 +++++-----------------
drivers/clk/loongson1/clk.c | 43 +++++++++++++
drivers/clk/loongson1/clk.h | 19 ++++++
5 files changed, 82 insertions(+), 58 deletions(-)
create mode 100644 drivers/clk/loongson1/Makefile
rename drivers/clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} (67%)
create mode 100644 drivers/clk/loongson1/clk.c
create mode 100644 drivers/clk/loongson1/clk.h
--
1.9.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V1 1/3] clk: Loongson1: Refactor Loongson1 clock
2016-09-19 4:38 [PATCH V1 0/3] Refactor Loongson1 clock Keguang Zhang
@ 2016-09-19 4:38 ` Keguang Zhang
2016-09-23 21:52 ` Stephen Boyd
2016-09-19 4:38 ` [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 3/3] clk: Loongson1: Make use of GENMASK Keguang Zhang
2 siblings, 1 reply; 5+ messages in thread
From: Keguang Zhang @ 2016-09-19 4:38 UTC (permalink / raw)
To: linux-clk, linux-mips, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
Factor out the common functions into loongson1/clk.c
to support both Loongson1B and Loongson1C. And, put
the rest into loongson1/clk-loongson1b.c.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
v1:
Rebase the patch on clk: ls1x: Migrate to clk_hw based OF
and registration APIs.
---
drivers/clk/Makefile | 2 +-
drivers/clk/loongson1/Makefile | 2 +
.../clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} | 51 ++--------------------
drivers/clk/loongson1/clk.c | 43 ++++++++++++++++++
drivers/clk/loongson1/clk.h | 19 ++++++++
5 files changed, 69 insertions(+), 48 deletions(-)
create mode 100644 drivers/clk/loongson1/Makefile
rename drivers/clk/{clk-ls1x.c => loongson1/clk-loongson1b.c} (78%)
create mode 100644 drivers/clk/loongson1/clk.c
create mode 100644 drivers/clk/loongson1/clk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8264d81..925081e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
-obj-$(CONFIG_MACH_LOONGSON32) += clk-ls1x.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
@@ -61,6 +60,7 @@ obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_MACH_INGENIC) += ingenic/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
+obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/
obj-$(CONFIG_MACH_PIC32) += microchip/
diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile
new file mode 100644
index 0000000..5a162a1
--- /dev/null
+++ b/drivers/clk/loongson1/Makefile
@@ -0,0 +1,2 @@
+obj-y += clk.o
+obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/loongson1/clk-loongson1b.c
similarity index 78%
rename from drivers/clk/clk-ls1x.c
rename to drivers/clk/loongson1/clk-loongson1b.c
index 8430e45..5b6817e 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/loongson1/clk-loongson1b.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
+ * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -10,25 +10,16 @@
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/slab.h>
#include <linux/err.h>
#include <loongson1.h>
+#include "clk.h"
#define OSC (33 * 1000000)
#define DIV_APB 2
static DEFINE_SPINLOCK(_lock);
-static int ls1x_pll_clk_enable(struct clk_hw *hw)
-{
- return 0;
-}
-
-static void ls1x_pll_clk_disable(struct clk_hw *hw)
-{
-}
-
static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -43,44 +34,9 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
}
static const struct clk_ops ls1x_pll_clk_ops = {
- .enable = ls1x_pll_clk_enable,
- .disable = ls1x_pll_clk_disable,
.recalc_rate = ls1x_pll_recalc_rate,
};
-static struct clk_hw *__init clk_hw_register_pll(struct device *dev,
- const char *name,
- const char *parent_name,
- unsigned long flags)
-{
- int ret;
- struct clk_hw *hw;
- struct clk_init_data init;
-
- /* allocate the divider */
- hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
- if (!hw) {
- pr_err("%s: could not allocate clk_hw\n", __func__);
- return ERR_PTR(-ENOMEM);
- }
-
- init.name = name;
- init.ops = &ls1x_pll_clk_ops;
- init.flags = flags | CLK_IS_BASIC;
- init.parent_names = (parent_name ? &parent_name : NULL);
- init.num_parents = (parent_name ? 1 : 0);
- hw->init = &init;
-
- /* register the clock */
- ret = clk_hw_register(dev, hw);
- if (ret) {
- kfree(hw);
- hw = ERR_PTR(ret);
- }
-
- return hw;
-}
-
static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
@@ -93,7 +49,8 @@ void __init ls1x_clk_init(void)
clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);
/* clock derived from 33 MHz OSC clk */
- hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
+ hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk",
+ &ls1x_pll_clk_ops, 0);
clk_hw_register_clkdev(hw, "pll_clk", NULL);
/* clock derived from PLL clk */
diff --git a/drivers/clk/loongson1/clk.c b/drivers/clk/loongson1/clk.c
new file mode 100644
index 0000000..cfcfd14
--- /dev/null
+++ b/drivers/clk/loongson1/clk.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+
+struct clk_hw *__init clk_hw_register_pll(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ const struct clk_ops *ops,
+ unsigned long flags)
+{
+ int ret;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+
+ /* allocate the divider */
+ hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+ if (!hw)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ hw->init = &init;
+
+ /* register the clock */
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(hw);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/loongson1/clk.h b/drivers/clk/loongson1/clk.h
new file mode 100644
index 0000000..085d74b
--- /dev/null
+++ b/drivers/clk/loongson1/clk.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LOONGSON1_CLK_H
+#define __LOONGSON1_CLK_H
+
+struct clk_hw *clk_hw_register_pll(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ const struct clk_ops *ops,
+ unsigned long flags);
+
+#endif /* __LOONGSON1_CLK_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B
2016-09-19 4:38 [PATCH V1 0/3] Refactor Loongson1 clock Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
@ 2016-09-19 4:38 ` Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 3/3] clk: Loongson1: Make use of GENMASK Keguang Zhang
2 siblings, 0 replies; 5+ messages in thread
From: Keguang Zhang @ 2016-09-19 4:38 UTC (permalink / raw)
To: linux-clk, linux-mips, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
This patch updates some clock names of Loongson1B,
and adds AC97, DMA and NAND clock.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
v1:
Rebase the patch on clk: ls1x: Migrate to clk_hw based OF
and registration APIs.
---
drivers/clk/loongson1/clk-loongson1b.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c
index 5b6817e..4b3d9d2 100644
--- a/drivers/clk/loongson1/clk-loongson1b.c
+++ b/drivers/clk/loongson1/clk-loongson1b.c
@@ -37,19 +37,19 @@ static const struct clk_ops ls1x_pll_clk_ops = {
.recalc_rate = ls1x_pll_recalc_rate,
};
-static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
-static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
-static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
+static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", };
+static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", };
+static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", };
void __init ls1x_clk_init(void)
{
struct clk_hw *hw;
- hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
- clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);
+ hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
+ clk_hw_register_clkdev(hw, "osc_clk", NULL);
/* clock derived from 33 MHz OSC clk */
- hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk",
+ hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
&ls1x_pll_clk_ops, 0);
clk_hw_register_clkdev(hw, "pll_clk", NULL);
@@ -104,6 +104,7 @@ void __init ls1x_clk_init(void)
CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
clk_hw_register_clkdev(hw, "ahb_clk", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
clk_hw_register_clkdev(hw, "stmmaceth", NULL);
/* clock derived from AHB clk */
@@ -111,9 +112,11 @@ void __init ls1x_clk_init(void)
hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
DIV_APB);
clk_hw_register_clkdev(hw, "apb_clk", NULL);
- clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);
- clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);
- clk_hw_register_clkdev(hw, "ls1x_spi", NULL);
- clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
clk_hw_register_clkdev(hw, "serial8250", NULL);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V1 3/3] clk: Loongson1: Make use of GENMASK
2016-09-19 4:38 [PATCH V1 0/3] Refactor Loongson1 clock Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B Keguang Zhang
@ 2016-09-19 4:38 ` Keguang Zhang
2 siblings, 0 replies; 5+ messages in thread
From: Keguang Zhang @ 2016-09-19 4:38 UTC (permalink / raw)
To: linux-clk, linux-mips, linux-kernel
Cc: Michael Turquette, Stephen Boyd, Kelvin Cheung
From: Kelvin Cheung <keguang.zhang@gmail.com>
Make use of GENMASK instead of open coding the equivalent operation,
and update the PLL formula.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
drivers/clk/loongson1/clk-loongson1b.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c
index 4b3d9d2..f36a97e 100644
--- a/drivers/clk/loongson1/clk-loongson1b.c
+++ b/drivers/clk/loongson1/clk-loongson1b.c
@@ -26,7 +26,7 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
u32 pll, rate;
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
- rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
+ rate = 12 + (pll & GENMASK(5, 0));
rate *= OSC;
rate >>= 1;
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V1 1/3] clk: Loongson1: Refactor Loongson1 clock
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
@ 2016-09-23 21:52 ` Stephen Boyd
0 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2016-09-23 21:52 UTC (permalink / raw)
To: Keguang Zhang; +Cc: linux-clk, linux-mips, linux-kernel, Michael Turquette
On 09/19, Keguang Zhang wrote:
> From: Kelvin Cheung <keguang.zhang@gmail.com>
>
> Factor out the common functions into loongson1/clk.c
> to support both Loongson1B and Loongson1C. And, put
> the rest into loongson1/clk-loongson1b.c.
>
> Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-09-23 21:53 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-19 4:38 [PATCH V1 0/3] Refactor Loongson1 clock Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
2016-09-23 21:52 ` Stephen Boyd
2016-09-19 4:38 ` [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 3/3] clk: Loongson1: Make use of GENMASK Keguang Zhang
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