* [PATCH v2 1/3] devicetree: bindings: scsi: hisi_sas add hip07 support
2016-10-04 11:11 [PATCH v2 0/3] hisi_sas add hip07 support John Garry
@ 2016-10-04 11:11 ` John Garry
2016-10-09 1:29 ` Rob Herring
2016-10-04 11:11 ` [PATCH v2 2/3] hisi_sas: add device tree support for hip07 John Garry
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: John Garry @ 2016-10-04 11:11 UTC (permalink / raw)
To: jejb, martin.petersen, robh+dt, mark.rutland
Cc: linuxarm, xuwei5, john.garry2, linux-scsi, linux-kernel,
devicetree, hare, John Garry, Xiang Chen
Add support for hip07 chipset to hisi_sas controller.
Chipset hip07 has v2 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
index bf2411f..2a42a32 100644
--- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -6,6 +6,7 @@ Main node required properties:
- compatible : value should be as follows:
(a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
(b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
+ (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
- sas-addr : array of 8 bytes for host SAS address
- reg : Address and length of the SAS register
- hisilicon,sas-syscon: phandle of syscon used for sas control
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/3] devicetree: bindings: scsi: hisi_sas add hip07 support
2016-10-04 11:11 ` [PATCH v2 1/3] devicetree: bindings: scsi: " John Garry
@ 2016-10-09 1:29 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2016-10-09 1:29 UTC (permalink / raw)
To: John Garry
Cc: jejb, martin.petersen, mark.rutland, linuxarm, xuwei5,
john.garry2, linux-scsi, linux-kernel, devicetree, hare,
Xiang Chen
On Tue, Oct 04, 2016 at 07:11:09PM +0800, John Garry wrote:
> Add support for hip07 chipset to hisi_sas controller.
>
> Chipset hip07 has v2 hw.
>
> Signed-off-by: John Garry <john.garry@huawei.com>
> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
> ---
> Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] hisi_sas: add device tree support for hip07
2016-10-04 11:11 [PATCH v2 0/3] hisi_sas add hip07 support John Garry
2016-10-04 11:11 ` [PATCH v2 1/3] devicetree: bindings: scsi: " John Garry
@ 2016-10-04 11:11 ` John Garry
2016-10-04 11:11 ` [PATCH v2 3/3] hisi_sas: add v2 hw support for different refclk John Garry
2016-10-11 20:34 ` [PATCH v2 0/3] hisi_sas add hip07 support Martin K. Petersen
3 siblings, 0 replies; 6+ messages in thread
From: John Garry @ 2016-10-04 11:11 UTC (permalink / raw)
To: jejb, martin.petersen, robh+dt, mark.rutland
Cc: linuxarm, xuwei5, john.garry2, linux-scsi, linux-kernel,
devicetree, hare, John Garry, Xiang Chen
Chipset hip07 incorporates v2 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 9825a3f..758e06f 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -2319,6 +2319,7 @@ static int hisi_sas_v2_remove(struct platform_device *pdev)
static const struct of_device_id sas_v2_of_match[] = {
{ .compatible = "hisilicon,hip06-sas-v2",},
+ { .compatible = "hisilicon,hip07-sas-v2",},
{},
};
MODULE_DEVICE_TABLE(of, sas_v2_of_match);
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] hisi_sas: add v2 hw support for different refclk
2016-10-04 11:11 [PATCH v2 0/3] hisi_sas add hip07 support John Garry
2016-10-04 11:11 ` [PATCH v2 1/3] devicetree: bindings: scsi: " John Garry
2016-10-04 11:11 ` [PATCH v2 2/3] hisi_sas: add device tree support for hip07 John Garry
@ 2016-10-04 11:11 ` John Garry
2016-10-11 20:34 ` [PATCH v2 0/3] hisi_sas add hip07 support Martin K. Petersen
3 siblings, 0 replies; 6+ messages in thread
From: John Garry @ 2016-10-04 11:11 UTC (permalink / raw)
To: jejb, martin.petersen, robh+dt, mark.rutland
Cc: linuxarm, xuwei5, john.garry2, linux-scsi, linux-kernel,
devicetree, hare, John Garry, Xiang Chen
The hip06 D03 and hip07 D05 boards have different
reference clock frequencies for the SAS controller.
Register PHY_CTRL needs to be programmed differently
according to this frequency, so add support for this.
The default register setting in PHY_CTRL is for 50MHz,
so only update this register when the refclk frequency
is 66MHz.
For ACPI we expect the _RST handler to set the correct
value for PHY_CTRL (we're forced to take different
approach for DT and ACPI as ACPI does not support
fixed-clock device).
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 7 +++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 4 +++-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 72c9852..64046c5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -13,6 +13,7 @@
#define _HISI_SAS_H_
#include <linux/acpi.h>
+#include <linux/clk.h>
#include <linux/dmapool.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
@@ -183,6 +184,7 @@ struct hisi_hba {
u32 ctrl_reset_reg;
u32 ctrl_reset_sts_reg;
u32 ctrl_clock_ena_reg;
+ u32 refclk_frequency_mhz;
u8 sas_addr[SAS_ADDR_SIZE];
int n_phy;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 2f872f7..9afc697 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -1396,6 +1396,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
struct hisi_hba *hisi_hba;
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
+ struct clk *refclk;
shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
if (!shost)
@@ -1432,6 +1433,12 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
goto err_out;
}
+ refclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(refclk))
+ dev_info(dev, "no ref clk property\n");
+ else
+ hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) / 1000000;
+
if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy))
goto err_out;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 758e06f..0763b47 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -836,7 +836,9 @@ static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
- hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
+ if (hisi_hba->refclk_frequency_mhz == 66)
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
+ /* else, do nothing -> leave it how you found it */
}
for (i = 0; i < hisi_hba->queue_count; i++) {
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/3] hisi_sas add hip07 support
2016-10-04 11:11 [PATCH v2 0/3] hisi_sas add hip07 support John Garry
` (2 preceding siblings ...)
2016-10-04 11:11 ` [PATCH v2 3/3] hisi_sas: add v2 hw support for different refclk John Garry
@ 2016-10-11 20:34 ` Martin K. Petersen
3 siblings, 0 replies; 6+ messages in thread
From: Martin K. Petersen @ 2016-10-11 20:34 UTC (permalink / raw)
To: John Garry
Cc: jejb, martin.petersen, robh+dt, mark.rutland, linuxarm, xuwei5,
john.garry2, linux-scsi, linux-kernel, devicetree, hare
>>>>> "John" == John Garry <john.garry@huawei.com> writes:
John> This patchset introduces support for hip07 SoC. The hip07 SoC has
John> the same v2 hw as in hip06.
John> Support for different reference clock is required as some SAS
John> registers need be programmed differently, depending on the
John> refclock rate.
Applied to 4.10/scsi-queue.
--
Martin K. Petersen Oracle Linux Engineering
^ permalink raw reply [flat|nested] 6+ messages in thread