* [PATCH v2 1/2] ls1043ardb: add qe node to ls1043ardb
@ 2016-10-09 2:12 Zhao Qiang
2016-10-09 2:12 ` [PATCH v2 2/2] ls1043ardb: add ds26522 node to dts Zhao Qiang
0 siblings, 1 reply; 5+ messages in thread
From: Zhao Qiang @ 2016-10-09 2:12 UTC (permalink / raw)
To: robh+dt
Cc: mark.rutland, catalin.marinas, devicetree, linux-arm-kernel,
linux-kernel, xiaobo.xie, Zhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
Changes for v2:
- use "fsl,ucc-hdlc" directly
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 66 +++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 4084631..a6a39fc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -124,6 +124,22 @@
};
};
+&uqe {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
+
&duart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd..f6b6775 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -388,6 +388,72 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 77 0x04 0 77 0x04>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] ls1043ardb: add ds26522 node to dts
2016-10-09 2:12 [PATCH v2 1/2] ls1043ardb: add qe node to ls1043ardb Zhao Qiang
@ 2016-10-09 2:12 ` Zhao Qiang
0 siblings, 0 replies; 5+ messages in thread
From: Zhao Qiang @ 2016-10-09 2:12 UTC (permalink / raw)
To: robh+dt
Cc: mark.rutland, catalin.marinas, devicetree, linux-arm-kernel,
linux-kernel, xiaobo.xie, Zhao Qiang
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
Changes for v2:
- na
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index a6a39fc..7f93bcc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -122,6 +122,22 @@
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
+
+ slic@2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic@3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
};
&uqe {
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
@ 2020-04-29 8:20 Qiang Zhao
2020-05-17 14:10 ` Shawn Guo
0 siblings, 1 reply; 5+ messages in thread
From: Qiang Zhao @ 2020-04-29 8:20 UTC (permalink / raw)
To: shawnguo; +Cc: leoyang.li, devicetree, linux-kernel, Zhao Qiang
From: Zhao Qiang <qiang.zhao@nxp.com>
Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
v2:
- add commit msg and drop a new blank line
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 65 +++++++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 4223a23..96e87ba 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -96,6 +96,22 @@
};
};
+&uqe {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
+
&duart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c084c7a4..674e671 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -525,6 +525,71 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 77 0x04 0 77 0x04>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
--
2.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
2020-04-29 8:20 [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb Qiang Zhao
@ 2020-05-17 14:10 ` Shawn Guo
2020-05-18 3:40 ` Qiang Zhao
0 siblings, 1 reply; 5+ messages in thread
From: Shawn Guo @ 2020-05-17 14:10 UTC (permalink / raw)
To: Qiang Zhao; +Cc: leoyang.li, devicetree, linux-kernel
On Wed, Apr 29, 2020 at 04:20:51PM +0800, Qiang Zhao wrote:
> From: Zhao Qiang <qiang.zhao@nxp.com>
>
> Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
>
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Subject prefix should be like 'arm64: dts: ...'
> ---
> v2:
> - add commit msg and drop a new blank line
>
> arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 65 +++++++++++++++++++++++
> 2 files changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> index 4223a23..96e87ba 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> @@ -96,6 +96,22 @@
> };
> };
>
> +&uqe {
Keep labeling node sort alphabetically.
> + ucc_hdlc: ucc@2000 {
> + compatible = "fsl,ucc-hdlc";
> + rx-clock-name = "clk8";
> + tx-clock-name = "clk9";
> + fsl,rx-sync-clock = "rsync_pin";
> + fsl,tx-sync-clock = "tsync_pin";
> + fsl,tx-timeslot-mask = <0xfffffffe>;
> + fsl,rx-timeslot-mask = <0xfffffffe>;
> + fsl,tdm-framer-type = "e1";
> + fsl,tdm-id = <0>;
> + fsl,siram-entry-id = <0>;
> + fsl,tdm-interface;
> + };
> +};
> +
> &duart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index c084c7a4..674e671 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -525,6 +525,71 @@
> #interrupt-cells = <2>;
> };
>
> + uqe: uqe@2400000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "qe";
Is this really needed? I can not find it in bindings doc qe.txt.
> + compatible = "fsl,qe", "simple-bus";
> + ranges = <0x0 0x0 0x2400000 0x40000>;
> + reg = <0x0 0x2400000 0x0 0x480>;
> + brg-frequency = <100000000>;
> + bus-frequency = <200000000>;
> + fsl,qe-num-riscs = <1>;
> + fsl,qe-num-snums = <28>;
> +
> + qeic: qeic@80 {
> + compatible = "fsl,qe-ic";
> + reg = <0x80 0x80>;
> + #address-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupts = <0 77 0x04 0 77 0x04>;
Two identical interrupts? Also, please use GIC_SPI and
IRQ_TYPE_LEVEL_HIGH defines.
Shawn
> + };
> +
> + si1: si@700 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,ls1043-qe-si",
> + "fsl,t1040-qe-si";
> + reg = <0x700 0x80>;
> + };
> +
> + siram1: siram@1000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,ls1043-qe-siram",
> + "fsl,t1040-qe-siram";
> + reg = <0x1000 0x800>;
> + };
> +
> + ucc@2000 {
> + cell-index = <1>;
> + reg = <0x2000 0x200>;
> + interrupts = <32>;
> + interrupt-parent = <&qeic>;
> + };
> +
> + ucc@2200 {
> + cell-index = <3>;
> + reg = <0x2200 0x200>;
> + interrupts = <34>;
> + interrupt-parent = <&qeic>;
> + };
> +
> + muram@10000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,qe-muram", "fsl,cpm-muram";
> + ranges = <0x0 0x10000 0x6000>;
> +
> + data-only@0 {
> + compatible = "fsl,qe-muram-data",
> + "fsl,cpm-muram-data";
> + reg = <0x0 0x6000>;
> + };
> + };
> + };
> +
> lpuart0: serial@2950000 {
> compatible = "fsl,ls1021a-lpuart";
> reg = <0x0 0x2950000 0x0 0x1000>;
> --
> 2.9.5
>
^ permalink raw reply [flat|nested] 5+ messages in thread* RE: [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
2020-05-17 14:10 ` Shawn Guo
@ 2020-05-18 3:40 ` Qiang Zhao
0 siblings, 0 replies; 5+ messages in thread
From: Qiang Zhao @ 2020-05-18 3:40 UTC (permalink / raw)
To: Shawn Guo; +Cc: Leo Li, devicetree, linux-kernel
On Wed, Apr 29, 2020 at 04:20:51PM +0800, Shawn Guo <shawnguo@kernel.org> wrote:
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: 2020年5月17日 22:10
> To: Qiang Zhao <qiang.zhao@nxp.com>
> Cc: Leo Li <leoyang.li@nxp.com>; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
>
> On Wed, Apr 29, 2020 at 04:20:51PM +0800, Qiang Zhao wrote:
> > From: Zhao Qiang <qiang.zhao@nxp.com>
> >
> > Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
> >
> > Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
>
> Subject prefix should be like 'arm64: dts: ...'
>
>
> > ---
> > v2:
> > - add commit msg and drop a new blank line
> >
> > arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++++++
> > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 65
> +++++++++++++++++++++++
> > 2 files changed, 81 insertions(+)
> >
> > + compatible = "fsl,qe", "simple-bus";
> > + ranges = <0x0 0x0 0x2400000 0x40000>;
> > + reg = <0x0 0x2400000 0x0 0x480>;
> > + brg-frequency = <100000000>;
> > + bus-frequency = <200000000>;
> > + fsl,qe-num-riscs = <1>;
> > + fsl,qe-num-snums = <28>;
> > +
> > + qeic: qeic@80 {
> > + compatible = "fsl,qe-ic";
> > + reg = <0x80 0x80>;
> > + #address-cells = <0>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupts = <0 77 0x04 0 77 0x04>;
>
> Two identical interrupts?
Thank you for comments.
On some boards for QE, There are two different interrupts.
And On others, there is only one interrupt.
In order to make it compatible, QE interrupts used to be wrote like this.
The driver also handle the situation like this.
Best Regards
Qiang Zhao
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-05-18 3:40 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2016-10-09 2:12 [PATCH v2 1/2] ls1043ardb: add qe node to ls1043ardb Zhao Qiang
2016-10-09 2:12 ` [PATCH v2 2/2] ls1043ardb: add ds26522 node to dts Zhao Qiang
2020-04-29 8:20 [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb Qiang Zhao
2020-05-17 14:10 ` Shawn Guo
2020-05-18 3:40 ` Qiang Zhao
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