From: Vikas Shivappa <vikas.shivappa@linux.intel.com>
To: vikas.shivappa@intel.com, linux-kernel@vger.kernel.org
Cc: x86@kernel.org, hpa@zytor.com, tglx@linutronix.de,
mingo@kernel.org, peterz@infradead.org, ravi.v.shankar@intel.com,
tony.luck@intel.com, fenghua.yu@intel.com,
h.peter.anvin@intel.com, vikas.shivappa@linux.intel.com
Subject: [PATCH 3/8] x86/intel_rdt/mba: Improvements to handle more RDT resources like MBA
Date: Tue, 10 Jan 2017 11:33:03 -0800 [thread overview]
Message-ID: <1484076788-25385-4-git-send-email-vikas.shivappa@linux.intel.com> (raw)
In-Reply-To: <1484076788-25385-1-git-send-email-vikas.shivappa@linux.intel.com>
This patch does some changes to get ready to handle more resources like
Memory b/w allocation(MBA).
-Update the control registers only when user changes the controls(cbm for
Cache resources and Mem b/w for memory). Hence not sending IPIs on all
domains when user updates the control vals.
-Introduce next_enabled_resource rather than looping through all
resources while parsing each schemata line. The order of resources
should be anyways the same as the root schemata.
-Return error as soon as we detect a resource not entering all domain
values in schemata rather than waiting till we parse all resources.
Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
---
arch/x86/include/asm/intel_rdt.h | 16 +++++++++++++
arch/x86/kernel/cpu/intel_rdt_schemata.c | 40 +++++++++++++++++---------------
2 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 9f66bf5..e1f8acb 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -156,6 +156,22 @@ enum {
r++) \
if (r->enabled)
+/*
+ * Parameter r must be NULL or pointing to
+ * a valid rdt_resource_all entry.
+ * Points r to the next enabled RDT resource at the end.
+ */
+#define next_enabled_rdt_resource(r) \
+do { \
+ if (!r) \
+ r = rdt_resources_all; \
+ else \
+ r++; \
+ for (; r < rdt_resources_all + RDT_NUM_RESOURCES; r++) \
+ if (r->enabled) \
+ break; \
+} while (0)
+
/* CPUID.(EAX=10H, ECX=ResID=1).EAX */
union cpuid_0x10_1_eax {
struct {
diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index c50f742..054d771 100644
--- a/arch/x86/kernel/cpu/intel_rdt_schemata.c
+++ b/arch/x86/kernel/cpu/intel_rdt_schemata.c
@@ -94,6 +94,10 @@ static int parse_line(char *line, struct rdt_resource *r)
return -EINVAL;
}
+ /* Incorrect number of domains in the line */
+ if (r->num_tmp_ctrl != r->num_domains)
+ return -EINVAL;
+
/* Any garbage at the end of the line? */
if (line && line[0])
return -EINVAL;
@@ -114,9 +118,16 @@ static int update_domains(struct rdt_resource *r, int closid)
msr_param.high = msr_param.low + 1;
msr_param.res = r;
+ /*
+ * Only update the domains that user has changed.
+ * There by avoiding unnecessary IPIs.
+ */
list_for_each_entry(d, &r->domains, list) {
- cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
- d->ctrl_val[msr_param.low] = r->tmp_ctrl[idx++];
+ if (d->ctrl_val[msr_param.low] != r->tmp_ctrl[idx]) {
+ cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
+ d->ctrl_val[msr_param.low] = r->tmp_ctrl[idx];
+ }
+ idx++;
}
cpu = get_cpu();
/* Update CBM on this cpu if it's in cpu_mask. */
@@ -164,30 +175,21 @@ ssize_t rdtgroup_schemata_write(struct kernfs_open_file *of,
r->num_tmp_ctrl = 0;
}
+ r = NULL;
while ((tok = strsep(&buf, "\n")) != NULL) {
resname = strsep(&tok, ":");
if (!tok) {
ret = -EINVAL;
goto out;
}
- for_each_enabled_rdt_resource(r) {
- if (!strcmp(resname, r->name) &&
- closid < r->num_closid) {
- ret = parse_line(tok, r);
- if (ret)
- goto out;
- break;
- }
- }
- if (!r->name) {
- ret = -EINVAL;
- goto out;
- }
- }
- /* Did the parser find all the masks we need? */
- for_each_enabled_rdt_resource(r) {
- if (r->num_tmp_ctrl != r->num_domains) {
+ next_enabled_rdt_resource(r);
+
+ if (!strcmp(resname, r->name)) {
+ ret = parse_line(tok, r);
+ if (ret)
+ goto out;
+ } else {
ret = -EINVAL;
goto out;
}
--
1.9.1
next prev parent reply other threads:[~2017-01-10 19:34 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-10 19:33 [PATCH 0/8 V1] x86/intel_rdt: Memory b/w Allocation support Vikas Shivappa
2017-01-10 19:33 ` [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Vikas Shivappa
2017-01-16 13:43 ` Thomas Gleixner
2017-01-18 0:51 ` Shivappa Vikas
2017-01-18 9:01 ` Thomas Gleixner
2017-01-23 18:57 ` Shivappa Vikas
2017-01-23 19:01 ` Thomas Gleixner
2017-01-24 22:10 ` Shivappa Vikas
2017-01-10 19:33 ` [PATCH 2/8] x86/intel_rdt/mba: Generalize the naming to get ready for MBA Vikas Shivappa
2017-01-16 13:45 ` Thomas Gleixner
2017-01-10 19:33 ` Vikas Shivappa [this message]
2017-01-16 13:54 ` [PATCH 3/8] x86/intel_rdt/mba: Improvements to handle more RDT resources like MBA Thomas Gleixner
2017-01-18 0:53 ` Shivappa Vikas
2017-01-18 9:05 ` Thomas Gleixner
2017-01-10 19:33 ` [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect Vikas Shivappa
2017-01-16 13:59 ` Thomas Gleixner
2017-01-16 14:41 ` Peter Zijlstra
2017-01-16 16:16 ` Thomas Gleixner
2017-01-10 19:33 ` [PATCH 5/8] x86/intel_rct/mba: Add MBA structures and initialize MBA Vikas Shivappa
2017-01-16 14:06 ` Thomas Gleixner
2017-01-18 0:56 ` Shivappa Vikas
2017-01-10 19:33 ` [PATCH 6/8] x86/intel_rdt/mba: Add info directory files for MBA Vikas Shivappa
2017-01-16 14:14 ` Thomas Gleixner
2017-01-18 1:02 ` Shivappa Vikas
2017-01-18 9:08 ` Thomas Gleixner
2017-01-23 19:45 ` Shivappa Vikas
2017-01-10 19:33 ` [PATCH 7/8] x86/intel_rdt/mba: Add schemata file support " Vikas Shivappa
2017-01-16 16:07 ` Thomas Gleixner
2017-01-18 1:03 ` Shivappa Vikas
2017-01-10 19:33 ` [PATCH 8/8] x86/intel_rdt: rmdir,umount and hotcpu updates " Vikas Shivappa
2017-01-16 16:13 ` Thomas Gleixner
2017-01-23 20:18 ` Shivappa Vikas
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