* [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
@ 2017-01-31 19:43 Hoan Tran
2017-02-02 19:47 ` Andy Shevchenko
2017-02-06 10:21 ` Linus Walleij
0 siblings, 2 replies; 9+ messages in thread
From: Hoan Tran @ 2017-01-31 19:43 UTC (permalink / raw)
To: Linus Walleij, Alexandre Courbot
Cc: linux-gpio, linux-kernel, lho, Duc Dang, Hoan Tran
Next generation of X-Gene SoC's GPIO hardware register map is very
similar to DW GPIO. It only differs by a few register addresses.
This patch modifies DW GPIO driver to accommodate the difference
in a few register addresses.
Signed-off-by: Hoan Tran <hotran@apm.com>
---
drivers/gpio/gpio-dwapb.c | 84 +++++++++++++++++++++++++++++++++++++----------
1 file changed, 67 insertions(+), 17 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index 6193f62..5f21751 100644
--- a/drivers/gpio/gpio-dwapb.c
+++ b/drivers/gpio/gpio-dwapb.c
@@ -21,6 +21,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
@@ -55,6 +56,13 @@
#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
+#define GPIO_REG_OFFSET_V2 1
+#define GPIO_INTMASK_V2 0x44
+#define GPIO_INTTYPE_LEVEL_V2 0x34
+#define GPIO_INT_POLARITY_V2 0x38
+#define GPIO_INTSTATUS_V2 0x3c
+#define GPIO_PORTA_EOI_V2 0x40
+
struct dwapb_gpio;
#ifdef CONFIG_PM_SLEEP
@@ -87,14 +95,36 @@ struct dwapb_gpio {
struct dwapb_gpio_port *ports;
unsigned int nr_ports;
struct irq_domain *domain;
+ unsigned int flags;
};
+static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
+{
+ if (!(gpio->flags & GPIO_REG_OFFSET_V2))
+ return offset;
+
+ switch (offset) {
+ case GPIO_INTMASK:
+ return GPIO_INTMASK_V2;
+ case GPIO_INTTYPE_LEVEL:
+ return GPIO_INTTYPE_LEVEL_V2;
+ case GPIO_INT_POLARITY:
+ return GPIO_INT_POLARITY_V2;
+ case GPIO_INTSTATUS:
+ return GPIO_INTSTATUS_V2;
+ case GPIO_PORTA_EOI:
+ return GPIO_PORTA_EOI_V2;
+ }
+
+ return offset;
+}
+
static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
{
struct gpio_chip *gc = &gpio->ports[0].gc;
void __iomem *reg_base = gpio->regs;
- return gc->read_reg(reg_base + offset);
+ return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
}
static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
@@ -103,7 +133,7 @@ static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
struct gpio_chip *gc = &gpio->ports[0].gc;
void __iomem *reg_base = gpio->regs;
- gc->write_reg(reg_base + offset, val);
+ gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
}
static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
@@ -336,8 +366,8 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
ct->chip.irq_disable = dwapb_irq_disable;
ct->chip.irq_request_resources = dwapb_irq_reqres;
ct->chip.irq_release_resources = dwapb_irq_relres;
- ct->regs.ack = GPIO_PORTA_EOI;
- ct->regs.mask = GPIO_INTMASK;
+ ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
+ ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
ct->type = IRQ_TYPE_LEVEL_MASK;
}
@@ -520,6 +550,21 @@ static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
return pdata;
}
+static const struct of_device_id dwapb_of_match[] = {
+ { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
+ { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dwapb_of_match);
+
+static const struct acpi_device_id dwapb_acpi_match[] = {
+ {"HISI0181", 0},
+ {"APMC0D07", 0},
+ {"APMC0D81", GPIO_REG_OFFSET_V2},
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
+
static int dwapb_gpio_probe(struct platform_device *pdev)
{
unsigned int i;
@@ -528,6 +573,7 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
int err;
struct device *dev = &pdev->dev;
struct dwapb_platform_data *pdata = dev_get_platdata(dev);
+ const struct of_device_id *of_devid;
if (!pdata) {
pdata = dwapb_gpio_get_pdata(dev);
@@ -555,6 +601,23 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
if (IS_ERR(gpio->regs))
return PTR_ERR(gpio->regs);
+ gpio->flags = 0;
+ of_devid = of_match_device(dwapb_of_match, dev);
+ if (of_devid) {
+ if (of_devid->data)
+ gpio->flags = (uintptr_t)of_devid->data;
+ }
+#ifdef CONFIG_ACPI
+ else {
+ const struct acpi_device_id *acpi_id;
+
+ acpi_id = acpi_match_device(dwapb_acpi_match, &pdev->dev);
+ if (acpi_id) {
+ if (acpi_id->driver_data)
+ gpio->flags = acpi_id->driver_data;
+ }
+ }
+#endif
for (i = 0; i < gpio->nr_ports; i++) {
err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
if (err)
@@ -581,19 +644,6 @@ static int dwapb_gpio_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id dwapb_of_match[] = {
- { .compatible = "snps,dw-apb-gpio" },
- { /* Sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, dwapb_of_match);
-
-static const struct acpi_device_id dwapb_acpi_match[] = {
- {"HISI0181", 0},
- {"APMC0D07", 0},
- { }
-};
-MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
-
#ifdef CONFIG_PM_SLEEP
static int dwapb_gpio_suspend(struct device *dev)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-01-31 19:43 [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC Hoan Tran
@ 2017-02-02 19:47 ` Andy Shevchenko
2017-02-03 1:18 ` Hoan Tran
2017-02-06 10:21 ` Linus Walleij
1 sibling, 1 reply; 9+ messages in thread
From: Andy Shevchenko @ 2017-02-02 19:47 UTC (permalink / raw)
To: Hoan Tran
Cc: Linus Walleij, Alexandre Courbot, linux-gpio, linux-kernel, lho,
Duc Dang
On Tue, Jan 31, 2017 at 9:43 PM, Hoan Tran <hotran@apm.com> wrote:
> Next generation of X-Gene SoC's GPIO hardware register map is very
> similar to DW GPIO. It only differs by a few register addresses.
> This patch modifies DW GPIO driver to accommodate the difference
> in a few register addresses.
> +#define GPIO_REG_OFFSET_V2 1
> +#define GPIO_INTMASK_V2 0x44
> +#define GPIO_INTTYPE_LEVEL_V2 0x34
> +#define GPIO_INT_POLARITY_V2 0x38
> +#define GPIO_INTSTATUS_V2 0x3c
> +#define GPIO_PORTA_EOI_V2 0x40
> +
> static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
> {
> struct gpio_chip *gc = &gpio->ports[0].gc;
> void __iomem *reg_base = gpio->regs;
>
> - return gc->read_reg(reg_base + offset);
> + return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
And what prevents us to introduce special read_reg for that registers?
Also what about to convert to regmap API?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-02 19:47 ` Andy Shevchenko
@ 2017-02-03 1:18 ` Hoan Tran
0 siblings, 0 replies; 9+ messages in thread
From: Hoan Tran @ 2017-02-03 1:18 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Linus Walleij, Alexandre Courbot, linux-gpio, linux-kernel,
Loc Ho, Duc Dang
Resend with plain text mode.
Hi Andy,
On Thu, Feb 2, 2017 at 11:47 AM, Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Tue, Jan 31, 2017 at 9:43 PM, Hoan Tran <hotran@apm.com> wrote:
>> Next generation of X-Gene SoC's GPIO hardware register map is very
>> similar to DW GPIO. It only differs by a few register addresses.
>> This patch modifies DW GPIO driver to accommodate the difference
>> in a few register addresses.
>
>> +#define GPIO_REG_OFFSET_V2 1
>> +#define GPIO_INTMASK_V2 0x44
>> +#define GPIO_INTTYPE_LEVEL_V2 0x34
>> +#define GPIO_INT_POLARITY_V2 0x38
>> +#define GPIO_INTSTATUS_V2 0x3c
>> +#define GPIO_PORTA_EOI_V2 0x40
>> +
>
>> static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
>> {
>> struct gpio_chip *gc = &gpio->ports[0].gc;
>> void __iomem *reg_base = gpio->regs;
>>
>> - return gc->read_reg(reg_base + offset);
>> + return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
>
> And what prevents us to introduce special read_reg for that registers?
How could we introduce a special read_reg here? If so, we also have to
have another special write_reg.
> Also what about to convert to regmap API?
Could you guide more how to use regmap in this case? The
gpio_reg_convert() is also used to send the GPIO_PORTA_EOI and
GPIO_INTMASK register offsets to irq_chip.
Thanks
Hoan
>
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-01-31 19:43 [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC Hoan Tran
2017-02-02 19:47 ` Andy Shevchenko
@ 2017-02-06 10:21 ` Linus Walleij
2017-02-06 23:49 ` Hoan Tran
2017-02-13 9:38 ` Jamie Iles
1 sibling, 2 replies; 9+ messages in thread
From: Linus Walleij @ 2017-02-06 10:21 UTC (permalink / raw)
To: Hoan Tran, Jamie Iles, Weike Chen, Sebastian Andrzej Siewior
Cc: Alexandre Courbot, linux-gpio, linux-kernel, Loc Ho, Duc Dang
On Tue, Jan 31, 2017 at 8:43 PM, Hoan Tran <hotran@apm.com> wrote:
> Next generation of X-Gene SoC's GPIO hardware register map is very
> similar to DW GPIO. It only differs by a few register addresses.
> This patch modifies DW GPIO driver to accommodate the difference
> in a few register addresses.
>
> Signed-off-by: Hoan Tran <hotran@apm.com>
On next iteration please include Jamie Iles, Weike Chen and Sebastian
Andrzej Siewior.
They all provided substantial contributions to this driver.
The dwapb needs a proper maintainer in MAINTAINERS actually, it is one of
those that can't use GPIOLIB_IRQCHIP so it requires special attention.
Jamie, interested in the job? Patches welcome :)
Also I've been thinking about this:
#define GPIO_SWPORTA_DR 0x00
#define GPIO_SWPORTA_DDR 0x04
#define GPIO_SWPORTB_DR 0x0c
#define GPIO_SWPORTB_DDR 0x10
#define GPIO_SWPORTC_DR 0x18
#define GPIO_SWPORTC_DDR 0x1c
#define GPIO_SWPORTD_DR 0x24
#define GPIO_SWPORTD_DDR 0x28
#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
#define GPIO_INT_POLARITY 0x3c
#define GPIO_INTSTATUS 0x40
#define GPIO_PORTA_DEBOUNCE 0x48
#define GPIO_PORTA_EOI 0x4c
#define GPIO_EXT_PORTA 0x50
#define GPIO_EXT_PORTB 0x54
#define GPIO_EXT_PORTC 0x58
#define GPIO_EXT_PORTD 0x5c
I wonder what is at addresses 0x08, 0x14, 0x20, 0x2c, 0x44?
Anything interesting we should know about? I bet they are not just
dead address space.
Is there a public datasheet for this thing that I can look at?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-06 10:21 ` Linus Walleij
@ 2017-02-06 23:49 ` Hoan Tran
2017-02-07 9:18 ` Andy Shevchenko
2017-02-13 9:38 ` Jamie Iles
1 sibling, 1 reply; 9+ messages in thread
From: Hoan Tran @ 2017-02-06 23:49 UTC (permalink / raw)
To: Linus Walleij
Cc: Jamie Iles, Weike Chen, Sebastian Andrzej Siewior,
Alexandre Courbot, linux-gpio, linux-kernel, Loc Ho, Duc Dang
Resend with plain text.
Hi Linus,
On Mon, Feb 6, 2017 at 2:21 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Jan 31, 2017 at 8:43 PM, Hoan Tran <hotran@apm.com> wrote:
>
>> Next generation of X-Gene SoC's GPIO hardware register map is very
>> similar to DW GPIO. It only differs by a few register addresses.
>> This patch modifies DW GPIO driver to accommodate the difference
>> in a few register addresses.
>>
>> Signed-off-by: Hoan Tran <hotran@apm.com>
>
> On next iteration please include Jamie Iles, Weike Chen and Sebastian
> Andrzej Siewior.
> They all provided substantial contributions to this driver.
>
> The dwapb needs a proper maintainer in MAINTAINERS actually, it is one of
> those that can't use GPIOLIB_IRQCHIP so it requires special attention.
> Jamie, interested in the job? Patches welcome :)
>
> Also I've been thinking about this:
>
> #define GPIO_SWPORTA_DR 0x00
> #define GPIO_SWPORTA_DDR 0x04
> #define GPIO_SWPORTB_DR 0x0c
> #define GPIO_SWPORTB_DDR 0x10
> #define GPIO_SWPORTC_DR 0x18
> #define GPIO_SWPORTC_DDR 0x1c
> #define GPIO_SWPORTD_DR 0x24
> #define GPIO_SWPORTD_DDR 0x28
> #define GPIO_INTEN 0x30
> #define GPIO_INTMASK 0x34
> #define GPIO_INTTYPE_LEVEL 0x38
> #define GPIO_INT_POLARITY 0x3c
> #define GPIO_INTSTATUS 0x40
> #define GPIO_PORTA_DEBOUNCE 0x48
> #define GPIO_PORTA_EOI 0x4c
> #define GPIO_EXT_PORTA 0x50
> #define GPIO_EXT_PORTB 0x54
> #define GPIO_EXT_PORTC 0x58
> #define GPIO_EXT_PORTD 0x5c
>
> I wonder what is at addresses 0x08, 0x14, 0x20, 0x2c, 0x44?
They are unused registers.
- 0x8, 0x14, 0x20, 0x2c are port data source registers.
- 0x44 is the raw interrupt status register.
>
> Anything interesting we should know about? I bet they are not just
> dead address space.
>
> Is there a public datasheet for this thing that I can look at?
I don't know if they public this datasheet. You can register and
download from here
https://www.synopsys.com/dw/ipdir.php?c=DW_apb_gpio
Thanks
Hoan
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-06 23:49 ` Hoan Tran
@ 2017-02-07 9:18 ` Andy Shevchenko
0 siblings, 0 replies; 9+ messages in thread
From: Andy Shevchenko @ 2017-02-07 9:18 UTC (permalink / raw)
To: Hoan Tran
Cc: Linus Walleij, Jamie Iles, Weike Chen, Sebastian Andrzej Siewior,
Alexandre Courbot, linux-gpio, linux-kernel, Loc Ho, Duc Dang
On Tue, Feb 7, 2017 at 1:49 AM, Hoan Tran <hotran@apm.com> wrote:
>> I wonder what is at addresses 0x08, 0x14, 0x20, 0x2c, 0x44?
>
> They are unused registers.
> - 0x8, 0x14, 0x20, 0x2c are port data source registers.
> - 0x44 is the raw interrupt status register.
>
>> Anything interesting we should know about? I bet they are not just
>> dead address space.
Sometimes they are (for example Synopsys DW DMA has few holes in address space).
>> Is there a public datasheet for this thing that I can look at?
>
> I don't know if they public this datasheet. You can register and
> download from here
> https://www.synopsys.com/dw/ipdir.php?c=DW_apb_gpio
Intel Quark x1000 SoC specification, which is public, at least sheds a
light on 0x44 (from above list). It has description of other used
registers (regarding to only one portA).
http://www.intel.me/content/www/xr/ar/embedded/products/quark/quark-x1000-datasheet.html
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-06 10:21 ` Linus Walleij
2017-02-06 23:49 ` Hoan Tran
@ 2017-02-13 9:38 ` Jamie Iles
2017-02-15 1:22 ` Hoan Tran
1 sibling, 1 reply; 9+ messages in thread
From: Jamie Iles @ 2017-02-13 9:38 UTC (permalink / raw)
To: Linus Walleij
Cc: Hoan Tran, Jamie Iles, Weike Chen, Sebastian Andrzej Siewior,
Alexandre Courbot, linux-gpio, linux-kernel, Loc Ho, Duc Dang
Hi Linus,
On Mon, Feb 06, 2017 at 11:21:09AM +0100, Linus Walleij wrote:
> On Tue, Jan 31, 2017 at 8:43 PM, Hoan Tran <hotran@apm.com> wrote:
>
> > Next generation of X-Gene SoC's GPIO hardware register map is very
> > similar to DW GPIO. It only differs by a few register addresses.
> > This patch modifies DW GPIO driver to accommodate the difference
> > in a few register addresses.
> >
> > Signed-off-by: Hoan Tran <hotran@apm.com>
>
> On next iteration please include Jamie Iles, Weike Chen and Sebastian
> Andrzej Siewior.
> They all provided substantial contributions to this driver.
>
> The dwapb needs a proper maintainer in MAINTAINERS actually, it is one of
> those that can't use GPIOLIB_IRQCHIP so it requires special attention.
> Jamie, interested in the job? Patches welcome :)
I actually don't have access to hardware using this driver anymore so
I'm probably not the right person for the job, but still happy to review
patches!
Jamie
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-13 9:38 ` Jamie Iles
@ 2017-02-15 1:22 ` Hoan Tran
2017-02-15 11:20 ` Jamie Iles
0 siblings, 1 reply; 9+ messages in thread
From: Hoan Tran @ 2017-02-15 1:22 UTC (permalink / raw)
To: Jamie Iles, Linus Walleij, Andy Shevchenko, Weike Chen,
Alexandre Courbot, Sebastian Andrzej Siewior
Cc: linux-gpio, linux-kernel, Loc Ho, Duc Dang
Hi Linus, Jamie and all,
Do you have any comments on this patch?
Thanks
Hoan
On Mon, Feb 13, 2017 at 1:38 AM, Jamie Iles <jamie@jamieiles.com> wrote:
> Hi Linus,
>
> On Mon, Feb 06, 2017 at 11:21:09AM +0100, Linus Walleij wrote:
>> On Tue, Jan 31, 2017 at 8:43 PM, Hoan Tran <hotran@apm.com> wrote:
>>
>> > Next generation of X-Gene SoC's GPIO hardware register map is very
>> > similar to DW GPIO. It only differs by a few register addresses.
>> > This patch modifies DW GPIO driver to accommodate the difference
>> > in a few register addresses.
>> >
>> > Signed-off-by: Hoan Tran <hotran@apm.com>
>>
>> On next iteration please include Jamie Iles, Weike Chen and Sebastian
>> Andrzej Siewior.
>> They all provided substantial contributions to this driver.
>>
>> The dwapb needs a proper maintainer in MAINTAINERS actually, it is one of
>> those that can't use GPIOLIB_IRQCHIP so it requires special attention.
>> Jamie, interested in the job? Patches welcome :)
>
> I actually don't have access to hardware using this driver anymore so
> I'm probably not the right person for the job, but still happy to review
> patches!
>
> Jamie
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC
2017-02-15 1:22 ` Hoan Tran
@ 2017-02-15 11:20 ` Jamie Iles
0 siblings, 0 replies; 9+ messages in thread
From: Jamie Iles @ 2017-02-15 11:20 UTC (permalink / raw)
To: Hoan Tran
Cc: Jamie Iles, Linus Walleij, Andy Shevchenko, Weike Chen,
Alexandre Courbot, Sebastian Andrzej Siewior, linux-gpio,
linux-kernel, Loc Ho, Duc Dang
Hi Hoan,
On Tue, Feb 14, 2017 at 05:22:09PM -0800, Hoan Tran wrote:
> Hi Linus, Jamie and all,
>
> Do you have any comments on this patch?
I think that the CONFIG_ACPI ifdef can be removed to clean it up -
acpi_match_device() returns NULL for !CONFIG_ACPI.
Other than that, looks good to me.
Jamie
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-02-15 11:20 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-31 19:43 [PATCH] gpio: dwapb: Add support for next generation of X-Gene SoC Hoan Tran
2017-02-02 19:47 ` Andy Shevchenko
2017-02-03 1:18 ` Hoan Tran
2017-02-06 10:21 ` Linus Walleij
2017-02-06 23:49 ` Hoan Tran
2017-02-07 9:18 ` Andy Shevchenko
2017-02-13 9:38 ` Jamie Iles
2017-02-15 1:22 ` Hoan Tran
2017-02-15 11:20 ` Jamie Iles
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