* [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328
@ 2017-02-06 2:50 Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 1/2] rockchip: clk: rk3328: add clk_mac2io_ext ID Elaine Zhang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Elaine Zhang @ 2017-02-06 2:50 UTC (permalink / raw)
To: heiko, mturquette, sboyd, xf, wdc
Cc: linux-clk, huangtao, xxx, linux-rockchip, linux-kernel,
linux-arm-kernel, Elaine Zhang
add clk_mac2io_ext ID.
describe clk_gmac using the new muxgrf type on rk3328.
Elaine Zhang (2):
rockchip: clk: rk3328: add clk_mac2io_ext ID
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
drivers/clk/rockchip/clk-rk3328.c | 9 +++++++++
include/dt-bindings/clock/rk3328-cru.h | 1 +
2 files changed, 10 insertions(+)
--
1.9.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/2] rockchip: clk: rk3328: add clk_mac2io_ext ID
2017-02-06 2:50 [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328 Elaine Zhang
@ 2017-02-06 2:50 ` Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 Elaine Zhang
2017-03-10 10:46 ` [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy " Heiko Stübner
2 siblings, 0 replies; 5+ messages in thread
From: Elaine Zhang @ 2017-02-06 2:50 UTC (permalink / raw)
To: heiko, mturquette, sboyd, xf, wdc
Cc: linux-clk, huangtao, xxx, linux-rockchip, linux-kernel,
linux-arm-kernel, Elaine Zhang
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
include/dt-bindings/clock/rk3328-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index ee702c8e4c09..d2b26a4b43eb 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -97,6 +97,7 @@
#define SCLK_MAC2IO_SRC 99
#define SCLK_MAC2IO 100
#define SCLK_MAC2PHY 101
+#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 120
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
2017-02-06 2:50 [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328 Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 1/2] rockchip: clk: rk3328: add clk_mac2io_ext ID Elaine Zhang
@ 2017-02-06 2:50 ` Elaine Zhang
2017-02-07 0:13 ` Heiko Stuebner
2017-03-10 10:46 ` [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy " Heiko Stübner
2 siblings, 1 reply; 5+ messages in thread
From: Elaine Zhang @ 2017-02-06 2:50 UTC (permalink / raw)
To: heiko, mturquette, sboyd, xf, wdc
Cc: linux-clk, huangtao, xxx, linux-rockchip, linux-kernel,
linux-arm-kernel, Elaine Zhang
With the newly introduced clk type for muxes in the grf we now can
describe some missing clocks, like the clk_gmac2io and clk_gmac2phy
that selects between clk_mac2io_src and gmac_clkin based on a bit
set in the general register files.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3328.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 1e384e143504..b04f29774ee7 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -20,6 +20,7 @@
#include <dt-bindings/clock/rk3328-cru.h>
#include "clk.h"
+#define RK3328_GRF_SOC_CON4 0x410
#define RK3328_GRF_SOC_STATUS0 0x480
#define RK3328_GRF_MAC_CON1 0x904
#define RK3328_GRF_MAC_CON2 0x908
@@ -214,6 +215,8 @@ enum rk3328_plls {
"gmac_clkin" };
PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
"phy_50m_out" };
+PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
+ "gmac_clkin" };
static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@@ -680,6 +683,10 @@ enum rk3328_plls {
COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(3), 5, GFLAGS),
+ MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
+ RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
+ MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
+ RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -691,6 +698,8 @@ enum rk3328_plls {
COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
RK3328_CLKGATE_CON(9), 2, GFLAGS),
+ MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
+ RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
2017-02-06 2:50 ` [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 Elaine Zhang
@ 2017-02-07 0:13 ` Heiko Stuebner
0 siblings, 0 replies; 5+ messages in thread
From: Heiko Stuebner @ 2017-02-07 0:13 UTC (permalink / raw)
To: Elaine Zhang
Cc: mturquette, sboyd, xf, wdc, linux-clk, huangtao, xxx,
linux-rockchip, linux-kernel, linux-arm-kernel
Hi Elaine,
Am Montag, 6. Februar 2017, 10:50:35 CET schrieb Elaine Zhang:
> With the newly introduced clk type for muxes in the grf we now can
> describe some missing clocks, like the clk_gmac2io and clk_gmac2phy
> that selects between clk_mac2io_src and gmac_clkin based on a bit
> set in the general register files.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
both patches look good, but I do have a question below.
Anyway, we're very late in the cycle for 4.10, so we'll need to wait until
after the next merge-window.
> ---
> drivers/clk/rockchip/clk-rk3328.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3328.c
> b/drivers/clk/rockchip/clk-rk3328.c index 1e384e143504..b04f29774ee7 100644
> --- a/drivers/clk/rockchip/clk-rk3328.c
> +++ b/drivers/clk/rockchip/clk-rk3328.c
> @@ -20,6 +20,7 @@
> #include <dt-bindings/clock/rk3328-cru.h>
> #include "clk.h"
>
> +#define RK3328_GRF_SOC_CON4 0x410
> #define RK3328_GRF_SOC_STATUS0 0x480
> #define RK3328_GRF_MAC_CON1 0x904
> #define RK3328_GRF_MAC_CON2 0x908
> @@ -214,6 +215,8 @@ enum rk3328_plls {
> "gmac_clkin" };
> PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
> "phy_50m_out" };
> +PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
> + "gmac_clkin" };
>
> static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
> [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
> @@ -680,6 +683,10 @@ enum rk3328_plls {
> COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
> RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
> RK3328_CLKGATE_CON(3), 5, GFLAGS),
> + MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p,
> CLK_SET_RATE_NO_REPARENT, + RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
> + MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p,
> CLK_SET_RATE_NO_REPARENT, + RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
>
> COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
> RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
> @@ -691,6 +698,8 @@ enum rk3328_plls {
> COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
> RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
> RK3328_CLKGATE_CON(9), 2, GFLAGS),
> + MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p,
> CLK_SET_RATE_NO_REPARENT, + RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
You don't set CLK_SET_RATE_PARENT but you do set CLK_SET_RATE_NO_REPARENT -
essentially disabling all automatic clock-changes for them.
Does this mean that these clocks should always only be set "manually" from
something like the assigned-clocks in dts?
This is not a problem in itself, I just want to understand how they should be
used :-)
Thanks
Heiko
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328
2017-02-06 2:50 [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328 Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 1/2] rockchip: clk: rk3328: add clk_mac2io_ext ID Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 Elaine Zhang
@ 2017-03-10 10:46 ` Heiko Stübner
2 siblings, 0 replies; 5+ messages in thread
From: Heiko Stübner @ 2017-03-10 10:46 UTC (permalink / raw)
To: Elaine Zhang
Cc: mturquette, sboyd, xf, wdc, linux-clk, huangtao, xxx,
linux-rockchip, linux-kernel, linux-arm-kernel
Am Montag, 6. Februar 2017, 10:50:33 CET schrieb Elaine Zhang:
> add clk_mac2io_ext ID.
> describe clk_gmac using the new muxgrf type on rk3328.
>
> Elaine Zhang (2):
> rockchip: clk: rk3328: add clk_mac2io_ext ID
> clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
applied with some minor style corrections to the subject for 4.12
Thanks
Heiko
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-03-10 10:46 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2017-02-06 2:50 [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy on rk3328 Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 1/2] rockchip: clk: rk3328: add clk_mac2io_ext ID Elaine Zhang
2017-02-06 2:50 ` [PATCH v1 2/2] clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 Elaine Zhang
2017-02-07 0:13 ` Heiko Stuebner
2017-03-10 10:46 ` [PATCH v1 0/2] clk: rockchip: describe clk_gmac2io and clk_gmac2phy " Heiko Stübner
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