* [PATCH v3 0/6] Add missing Tegra210 clocks
@ 2017-02-28 14:37 Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 1/6] clk: tegra: add cec clock Peter De Schrijver
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
This series adds a number of clocks which were missing from the Tegra210
clock definition. It applies on top of the 'Tegra210 clock bug fixes' series
posted earlier.
Change log:
v3: fixed compiler warnings
v2: fixed a few useless lines moving around
Peter De Schrijver (6):
clk: tegra: add cec clock
clk: tegra: define Tegra210 DMIC sync clocks
clk: tegra: fix constness for periph clks
clk: tegra: define Tegra210 DMIC clocks
clk: tegra: add super clk mux/div
clk: tegra: add aclk
drivers/clk/tegra/clk-id.h | 10 +++
drivers/clk/tegra/clk-periph.c | 4 +-
drivers/clk/tegra/clk-super.c | 87 +++++++++++++++++++++++--
drivers/clk/tegra/clk-tegra-audio.c | 85 +++++++++++++++++-------
drivers/clk/tegra/clk-tegra-periph.c | 22 +++++++
drivers/clk/tegra/clk-tegra114.c | 1 +
drivers/clk/tegra/clk-tegra124.c | 1 +
drivers/clk/tegra/clk-tegra210.c | 20 ++++++
drivers/clk/tegra/clk-tegra30.c | 1 +
drivers/clk/tegra/clk.h | 11 +++-
include/dt-bindings/clock/tegra114-car.h | 2 +-
include/dt-bindings/clock/tegra124-car-common.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 13 +++-
include/dt-bindings/clock/tegra30-car.h | 2 +-
14 files changed, 223 insertions(+), 38 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/6] clk: tegra: add cec clock
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 2/6] clk: tegra: define Tegra210 DMIC sync clocks Peter De Schrijver
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-periph.c | 1 +
drivers/clk/tegra/clk-tegra114.c | 1 +
drivers/clk/tegra/clk-tegra124.c | 1 +
drivers/clk/tegra/clk-tegra210.c | 1 +
drivers/clk/tegra/clk-tegra30.c | 1 +
include/dt-bindings/clock/tegra114-car.h | 2 +-
include/dt-bindings/clock/tegra124-car-common.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 2 +-
include/dt-bindings/clock/tegra30-car.h | 2 +-
10 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 1019eb8..fc978b2 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -308,6 +308,7 @@ enum clk_id {
tegra_clk_sclk_mux,
tegra_clk_sor_safe,
tegra_clk_ispa,
+ tegra_clk_cec,
tegra_clk_max,
};
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index c9e795b..a2aed27 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -837,6 +837,7 @@
GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
+ GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
};
static struct tegra_periph_init_data div_clks[] = {
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 933b5dd..fd1a99c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -819,6 +819,7 @@
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
+ [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index a112d3d..e81ea5b 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -928,6 +928,7 @@
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
+ [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 58d7f9c..bdb296a 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2222,6 +2222,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
+ [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..a2d163f 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -817,6 +817,7 @@
[tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
+ [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
};
static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 534c03f..ed5ca21 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
-/* 136 */
+#define TEGRA114_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index a215609..9352c7e 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
-/* 136 */
+#define TEGRA124_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index f5c6563..e7a2578 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
-/* 136 */
+#define TEGRA210_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 889e49b..7213354b 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -156,7 +156,7 @@
/* 133 */
/* 134 */
/* 135 */
-/* 136 */
+#define TEGRA30_CLK_CEC 136
/* 137 */
/* 138 */
/* 139 */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/6] clk: tegra: define Tegra210 DMIC sync clocks
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 1/6] clk: tegra: add cec clock Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 3/6] clk: tegra: fix constness for periph clks Peter De Schrijver
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock
of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add
a 3 new clocks similar to the audio* clocks which handle the same function
for the i2s and spdif clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 6 +++
drivers/clk/tegra/clk-tegra-audio.c | 85 +++++++++++++++++++++++---------
drivers/clk/tegra/clk-tegra210.c | 6 +++
include/dt-bindings/clock/tegra210-car.h | 9 +++-
4 files changed, 81 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index fc978b2..b40293c 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -309,6 +309,12 @@ enum clk_id {
tegra_clk_sor_safe,
tegra_clk_ispa,
tegra_clk_cec,
+ tegra_clk_dmic1_sync_clk,
+ tegra_clk_dmic2_sync_clk,
+ tegra_clk_dmic3_sync_clk,
+ tegra_clk_dmic1_sync_clk_mux,
+ tegra_clk_dmic2_sync_clk_mux,
+ tegra_clk_dmic3_sync_clk_mux,
tegra_clk_max,
};
diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
index e2bfa9b..b37cae7 100644
--- a/drivers/clk/tegra/clk-tegra-audio.c
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -31,6 +31,9 @@
#define AUDIO_SYNC_CLK_I2S3 0x4ac
#define AUDIO_SYNC_CLK_I2S4 0x4b0
#define AUDIO_SYNC_CLK_SPDIF 0x4b4
+#define AUDIO_SYNC_CLK_DMIC1 0x560
+#define AUDIO_SYNC_CLK_DMIC2 0x564
+#define AUDIO_SYNC_CLK_DMIC3 0x6b8
#define AUDIO_SYNC_DOUBLER 0x49c
@@ -91,8 +94,14 @@ struct tegra_audio2x_clk_initdata {
static DEFINE_SPINLOCK(clk_doubler_lock);
-static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
- "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
+static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
+ "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
+ "pll_a_out0", "vimclk_sync",
+};
+
+static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
+ "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
+ "vimclk_sync",
};
static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
@@ -114,6 +123,12 @@ struct tegra_audio2x_clk_initdata {
AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
};
+static struct tegra_audio_clk_initdata dmic_clks[] = {
+ AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
+ AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
+ AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
+};
+
static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
AUDIO2X(audio0, 113, 24),
AUDIO2X(audio1, 114, 25),
@@ -123,6 +138,41 @@ struct tegra_audio2x_clk_initdata {
AUDIO2X(spdif, 118, 29),
};
+static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
+ struct tegra_clk *tegra_clks,
+ struct tegra_audio_clk_initdata *sync,
+ int num_sync_clks,
+ const char * const *mux_names,
+ int num_mux_inputs)
+{
+ struct clk *clk;
+ struct clk **dt_clk;
+ struct tegra_audio_clk_initdata *data;
+ int i;
+
+ for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
+ dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
+ if (!dt_clk)
+ continue;
+
+ clk = clk_register_mux(NULL, data->mux_name, mux_names,
+ num_mux_inputs,
+ CLK_SET_RATE_NO_REPARENT,
+ clk_base + data->offset, 0, 3, 0,
+ NULL);
+ *dt_clk = clk;
+
+ dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
+ if (!dt_clk)
+ continue;
+
+ clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
+ 0, clk_base + data->offset, 4,
+ CLK_GATE_SET_TO_DISABLE, NULL);
+ *dt_clk = clk;
+ }
+}
+
void __init tegra_audio_clk_init(void __iomem *clk_base,
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
struct tegra_audio_clk_info *audio_info,
@@ -176,30 +226,17 @@ void __init tegra_audio_clk_init(void __iomem *clk_base,
*dt_clk = clk;
}
- for (i = 0; i < ARRAY_SIZE(audio_clks); i++) {
- struct tegra_audio_clk_initdata *data;
+ tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
+ ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
+ ARRAY_SIZE(mux_audio_sync_clk));
- data = &audio_clks[i];
- dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
+ /* make sure the DMIC sync clocks have a valid parent */
+ for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
+ writel_relaxed(1, clk_base + dmic_clks[i].offset);
- if (!dt_clk)
- continue;
- clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk,
- ARRAY_SIZE(mux_audio_sync_clk),
- CLK_SET_RATE_NO_REPARENT,
- clk_base + data->offset, 0, 3, 0,
- NULL);
- *dt_clk = clk;
-
- dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
- if (!dt_clk)
- continue;
-
- clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
- 0, clk_base + data->offset, 4,
- CLK_GATE_SET_TO_DISABLE, NULL);
- *dt_clk = clk;
- }
+ tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
+ ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
+ ARRAY_SIZE(mux_dmic_sync_clk));
for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
struct tegra_audio2x_clk_initdata *data;
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index bdb296a..ca63901 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2223,6 +2223,12 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
+ [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
+ [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
+ [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
+ [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
+ [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
+ [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
};
static struct tegra_devclk devclks[] __initdata = {
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index e7a2578..5aa1027 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -396,6 +396,13 @@
#define TEGRA210_CLK_PLL_C_UD 364
#define TEGRA210_CLK_SCLK_MUX 365
-#define TEGRA210_CLK_CLK_MAX 366
+#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
+#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
+#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
+#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
+#define TEGRA210_CLK_DMIC3_SYNC_CLK 392
+#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
+
+#define TEGRA210_CLK_CLK_MAX 394
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/6] clk: tegra: fix constness for periph clks
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 1/6] clk: tegra: add cec clock Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 2/6] clk: tegra: define Tegra210 DMIC sync clocks Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 4/6] clk: tegra: define Tegra210 DMIC clocks Peter De Schrijver
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
checkpatch now warns for const ** and expects const * const * to be used
instead. This means we have to update the prototypes and function
declarations to handle this change.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-periph.c | 4 ++--
drivers/clk/tegra/clk.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index a17ca6d..a5a5809 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -138,7 +138,7 @@ static void clk_periph_disable(struct clk_hw *hw)
};
static struct clk *_tegra_clk_register_periph(const char *name,
- const char **parent_names, int num_parents,
+ const char * const *parent_names, int num_parents,
struct tegra_clk_periph *periph,
void __iomem *clk_base, u32 offset,
unsigned long flags)
@@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name,
}
struct clk *tegra_clk_register_periph(const char *name,
- const char **parent_names, int num_parents,
+ const char * const *parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
u32 offset, unsigned long flags)
{
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a62ea73..8b09021e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -586,7 +586,7 @@ struct tegra_clk_periph {
extern const struct clk_ops tegra_clk_periph_ops;
struct clk *tegra_clk_register_periph(const char *name,
- const char **parent_names, int num_parents,
+ const char * const *parent_names, int num_parents,
struct tegra_clk_periph *periph, void __iomem *clk_base,
u32 offset, unsigned long flags);
struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -626,7 +626,7 @@ struct tegra_periph_init_data {
const char *name;
int clk_id;
union {
- const char **parent_names;
+ const char *const *parent_names;
const char *parent_name;
} p;
int num_parents;
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 4/6] clk: tegra: define Tegra210 DMIC clocks
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
` (2 preceding siblings ...)
2017-02-28 14:37 ` [PATCH v3 3/6] clk: tegra: fix constness for periph clks Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 5/6] clk: tegra: add super clk mux/div Peter De Schrijver
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Tegra210 has 3 inputs for Digital Microphones (DMICs). Provide the required
clocks for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 5 ++++-
drivers/clk/tegra/clk-tegra-periph.c | 21 +++++++++++++++++++++
drivers/clk/tegra/clk-tegra210.c | 3 +++
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index b40293c..d3a79a8 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -307,8 +307,11 @@ enum clk_id {
tegra_clk_xusb_ssp_src,
tegra_clk_sclk_mux,
tegra_clk_sor_safe,
- tegra_clk_ispa,
tegra_clk_cec,
+ tegra_clk_ispa,
+ tegra_clk_dmic1,
+ tegra_clk_dmic2,
+ tegra_clk_dmic3,
tegra_clk_dmic1_sync_clk,
tegra_clk_dmic2_sync_clk,
tegra_clk_dmic3_sync_clk,
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index a2aed27..9e6ac11 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -138,6 +138,9 @@
#define CLK_SOURCE_TSECB 0x6d8
#define CLK_SOURCE_MAUD 0x6d4
#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
+#define CLK_SOURCE_DMIC1 0x64c
+#define CLK_SOURCE_DMIC2 0x650
+#define CLK_SOURCE_DMIC3 0x6bc
#define MASK(x) (BIT(x) - 1)
@@ -625,6 +628,21 @@
};
#define mux_clkm_plldp_sor0lvds_idx NULL
+static const char * const mux_dmic1[] = {
+ "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
+};
+#define mux_dmic1_idx NULL
+
+static const char * const mux_dmic2[] = {
+ "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
+};
+#define mux_dmic2_idx NULL
+
+static const char * const mux_dmic3[] = {
+ "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
+};
+#define mux_dmic3_idx NULL
+
static struct tegra_periph_init_data periph_clks[] = {
AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
@@ -794,6 +812,9 @@
MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
+ MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
+ MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
+ MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
};
static struct tegra_periph_init_data gate_clks[] = {
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index ca63901..cfe7078 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2223,6 +2223,9 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
+ [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
+ [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
+ [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
[tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
[tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
[tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 5/6] clk: tegra: add super clk mux/div
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
` (3 preceding siblings ...)
2017-02-28 14:37 ` [PATCH v3 4/6] clk: tegra: define Tegra210 DMIC clocks Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 6/6] clk: tegra: add aclk Peter De Schrijver
2017-03-20 13:08 ` [PATCH v3 0/6] Add missing Tegra210 clocks Thierry Reding
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
Add a super clock type which implements both mux and divider. This is used
for aclk.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-super.c | 87 +++++++++++++++++++++++++++++++++++++++++--
drivers/clk/tegra/clk.h | 7 +++-
2 files changed, 89 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 131d1b50..84267cf 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -121,9 +121,50 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
return err;
}
+const struct clk_ops tegra_clk_super_mux_ops = {
+ .get_parent = clk_super_get_parent,
+ .set_parent = clk_super_set_parent,
+};
+
+static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
+ struct clk_hw *div_hw = &super->frac_div.hw;
+
+ __clk_hw_set_clk(div_hw, hw);
+
+ return super->div_ops->round_rate(div_hw, rate, parent_rate);
+}
+
+static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
+ struct clk_hw *div_hw = &super->frac_div.hw;
+
+ __clk_hw_set_clk(div_hw, hw);
+
+ return super->div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
+ struct clk_hw *div_hw = &super->frac_div.hw;
+
+ __clk_hw_set_clk(div_hw, hw);
+
+ return super->div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
const struct clk_ops tegra_clk_super_ops = {
.get_parent = clk_super_get_parent,
.set_parent = clk_super_set_parent,
+ .set_rate = clk_super_set_rate,
+ .round_rate = clk_super_round_rate,
+ .recalc_rate = clk_super_recalc_rate,
};
struct clk *tegra_clk_register_super_mux(const char *name,
@@ -136,13 +177,11 @@ struct clk *tegra_clk_register_super_mux(const char *name,
struct clk_init_data init;
super = kzalloc(sizeof(*super), GFP_KERNEL);
- if (!super) {
- pr_err("%s: could not allocate super clk\n", __func__);
+ if (!super)
return ERR_PTR(-ENOMEM);
- }
init.name = name;
- init.ops = &tegra_clk_super_ops;
+ init.ops = &tegra_clk_super_mux_ops;
init.flags = flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
@@ -163,3 +202,43 @@ struct clk *tegra_clk_register_super_mux(const char *name,
return clk;
}
+
+struct clk *tegra_clk_register_super_clk(const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags, void __iomem *reg, u8 clk_super_flags,
+ spinlock_t *lock)
+{
+ struct tegra_clk_super_mux *super;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ super = kzalloc(sizeof(*super), GFP_KERNEL);
+ if (!super)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &tegra_clk_super_ops;
+ init.flags = flags;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ super->reg = reg;
+ super->lock = lock;
+ super->width = 4;
+ super->flags = clk_super_flags;
+ super->frac_div.reg = reg + 4;
+ super->frac_div.shift = 16;
+ super->frac_div.width = 8;
+ super->frac_div.frac_width = 1;
+ super->frac_div.lock = lock;
+ super->div_ops = &tegra_clk_frac_div_ops;
+
+ /* Data in .init is copied by clk_register(), so stack variable OK */
+ super->hw.init = &init;
+
+ clk = clk_register(NULL, &super->hw);
+ if (IS_ERR(clk))
+ kfree(super);
+
+ return clk;
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 8b09021e..960e47e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -686,6 +686,8 @@ struct tegra_periph_init_data {
struct tegra_clk_super_mux {
struct clk_hw hw;
void __iomem *reg;
+ struct tegra_clk_frac_div frac_div;
+ const struct clk_ops *div_ops;
u8 width;
u8 flags;
u8 div2_index;
@@ -702,7 +704,10 @@ struct clk *tegra_clk_register_super_mux(const char *name,
const char **parent_names, u8 num_parents,
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
-
+struct clk *tegra_clk_register_super_clk(const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags, void __iomem *reg, u8 clk_super_flags,
+ spinlock_t *lock);
/**
* struct clk_init_table - clock initialization table
* @clk_id: clock id as mentioned in device tree bindings
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 6/6] clk: tegra: add aclk
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
` (4 preceding siblings ...)
2017-02-28 14:37 ` [PATCH v3 5/6] clk: tegra: add super clk mux/div Peter De Schrijver
@ 2017-02-28 14:37 ` Peter De Schrijver
2017-03-20 13:08 ` [PATCH v3 0/6] Add missing Tegra210 clocks Thierry Reding
6 siblings, 0 replies; 8+ messages in thread
From: Peter De Schrijver @ 2017-02-28 14:37 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot,
Rob Herring, Mark Rutland, Rhyland Klein, linux-clk, linux-tegra,
linux-kernel, devicetree
This clock clocks the ADSP cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 10 ++++++++++
include/dt-bindings/clock/tegra210-car.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index cfe7078..9a2512a 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2308,6 +2308,11 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
static struct clk **clks;
+static const char * const aclk_parents[] = {
+ "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
+ "clk_m"
+};
+
static __init void tegra210_periph_clk_init(void __iomem *clk_base,
void __iomem *pmc_base)
{
@@ -2369,6 +2374,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
clk_register_clkdev(clk, "cml1", NULL);
clks[TEGRA210_CLK_CML1] = clk;
+ clk = tegra_clk_register_super_clk("aclk", aclk_parents,
+ ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
+ 0, NULL);
+ clks[TEGRA210_CLK_ACLK] = clk;
+
tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
}
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 5aa1027..8744b19 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -396,6 +396,8 @@
#define TEGRA210_CLK_PLL_C_UD 364
#define TEGRA210_CLK_SCLK_MUX 365
+#define TEGRA210_CLK_ACLK 370
+
#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/6] Add missing Tegra210 clocks
2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
` (5 preceding siblings ...)
2017-02-28 14:37 ` [PATCH v3 6/6] clk: tegra: add aclk Peter De Schrijver
@ 2017-03-20 13:08 ` Thierry Reding
6 siblings, 0 replies; 8+ messages in thread
From: Thierry Reding @ 2017-03-20 13:08 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Stephen Boyd,
Stephen Warren, Alexandre Courbot, Rob Herring, Mark Rutland,
Rhyland Klein, linux-clk, linux-tegra, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 1626 bytes --]
On Tue, Feb 28, 2017 at 04:37:16PM +0200, Peter De Schrijver wrote:
> This series adds a number of clocks which were missing from the Tegra210
> clock definition. It applies on top of the 'Tegra210 clock bug fixes' series
> posted earlier.
>
> Change log:
>
> v3: fixed compiler warnings
>
> v2: fixed a few useless lines moving around
>
>
> Peter De Schrijver (6):
> clk: tegra: add cec clock
> clk: tegra: define Tegra210 DMIC sync clocks
> clk: tegra: fix constness for periph clks
> clk: tegra: define Tegra210 DMIC clocks
> clk: tegra: add super clk mux/div
> clk: tegra: add aclk
>
> drivers/clk/tegra/clk-id.h | 10 +++
> drivers/clk/tegra/clk-periph.c | 4 +-
> drivers/clk/tegra/clk-super.c | 87 +++++++++++++++++++++++--
> drivers/clk/tegra/clk-tegra-audio.c | 85 +++++++++++++++++-------
> drivers/clk/tegra/clk-tegra-periph.c | 22 +++++++
> drivers/clk/tegra/clk-tegra114.c | 1 +
> drivers/clk/tegra/clk-tegra124.c | 1 +
> drivers/clk/tegra/clk-tegra210.c | 20 ++++++
> drivers/clk/tegra/clk-tegra30.c | 1 +
> drivers/clk/tegra/clk.h | 11 +++-
> include/dt-bindings/clock/tegra114-car.h | 2 +-
> include/dt-bindings/clock/tegra124-car-common.h | 2 +-
> include/dt-bindings/clock/tegra210-car.h | 13 +++-
> include/dt-bindings/clock/tegra30-car.h | 2 +-
> 14 files changed, 223 insertions(+), 38 deletions(-)
Applied to for-4.12/clk, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-03-20 13:13 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2017-02-28 14:37 [PATCH v3 0/6] Add missing Tegra210 clocks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 1/6] clk: tegra: add cec clock Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 2/6] clk: tegra: define Tegra210 DMIC sync clocks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 3/6] clk: tegra: fix constness for periph clks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 4/6] clk: tegra: define Tegra210 DMIC clocks Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 5/6] clk: tegra: add super clk mux/div Peter De Schrijver
2017-02-28 14:37 ` [PATCH v3 6/6] clk: tegra: add aclk Peter De Schrijver
2017-03-20 13:08 ` [PATCH v3 0/6] Add missing Tegra210 clocks Thierry Reding
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