[PATCH v2 0/3] add support of u2phy for rk3328

[PATCH v2 0/3] add support of u2phy for rk3328

[Meng Dongyang]

The config information of RK3328 about address and port property
is different from before platform. So add config information in the
data of match table and documentation of the device tree bindings
of u2phy.

Changes in v2:
 - move u2phy grf specification to .../devicetree/bindings/soc/rockchip/grf.txt
 - add otg port config information of rk3328

Meng Dongyang (3):
  Documentation: bindings: add assign clock property in u2phy node
  Documentation: bindings: add DT documentation for u2phy and u2phy grf
  phy: rockchip-inno-usb2: add support of u2phy for rk3328

 .../bindings/phy/phy-rockchip-inno-usb2.txt        |  6 +++
 .../devicetree/bindings/soc/rockchip/grf.txt       | 15 +++++++
 drivers/phy/phy-rockchip-inno-usb2.c               | 52 ++++++++++++++++++++++
 3 files changed, 73 insertions(+)

-- 
1.9.1

[PATCH v2 1/3] Documentation: bindings: add assign clock property in u2phy node

[Meng Dongyang]

On some platform such as RK3328, the 480m clock may need to assign
clock parent in dts in stead of clock driver. So this patch add
property of assigned-clocks and assigned-clock-parents to assign
parent for 480m clock.

Changes in v2:
 - move u2phy grf specification to grf.txt

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
---
 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
index 3c29c77..e71a8d2 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
@@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
 
 Required properties (phy (parent) node):
  - compatible : should be one of the listed compatibles:
+	* "rockchip,rk3328-usb2phy"
 	* "rockchip,rk3366-usb2phy"
 	* "rockchip,rk3399-usb2phy"
  - reg : the address offset of grf for usb-phy configuration.
@@ -11,6 +12,11 @@ Required properties (phy (parent) node):
 Optional properties:
  - clocks : phandle + phy specifier pair, for the input clock of phy.
  - clock-names : input clock name of phy, must be "phyclk".
+ - assigned-clocks : phandle of usb 480m clock.
+ - assigned-clock-parents : parent of usb 480m clock, select between
+		 usb-phy output 480m and xin24m.
+		 Refer to clk/clock-bindings.txt for generic clock
+		 consumer properties.
 
 Required nodes : a sub-node is required for each port the phy provides.
 		 The sub-node name is used to identify host or otg port,
-- 
1.9.1

[PATCH v2 2/3] Documentation: bindings: add DT documentation for u2phy and u2phy grf

[Meng Dongyang]

Due to the u2phy registers are separated from general grf, we need to
add u2phy grf node and place u2phy node in it. So this patch add u2phy
grf node.

Changes in v2:
 - add u2phy grf specification

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index 013e71a..6ac23f9 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -7,6 +7,9 @@ From RK3368 SoCs, the GRF is divided into two sections,
 - GRF, used for general non-secure system,
 - PMUGRF, used for always on system
 
+On RK3328 SoCs, the GRF is divided into three sections,
+except GRF and PMUGRF, add a section for USB2PHYGRF,
+
 Required Properties:
 
 - compatible: GRF should be one of the followings
@@ -19,6 +22,8 @@ Required Properties:
 - compatible: PMUGRF should be one of the followings
    - "rockchip,rk3368-pmugrf", "syscon": for rk3368
    - "rockchip,rk3399-pmugrf", "syscon": for rk3399
+- compatible: USB2GRF should be one of the followings
+   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
 - reg: physical base address of the controller and length of memory mapped
   region.
 
@@ -33,3 +38,13 @@ Example: GRF and PMUGRF of RK3399 SoCs
 		compatible = "rockchip,rk3399-grf", "syscon";
 		reg = <0x0 0xff770000 0x0 0x10000>;
 	};
+
+Example: USB2GRF of RK3328 SoCs
+
+	usb2phy_grf: syscon@ff450000 {
+		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xff450000 0x0 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
-- 
1.9.1

[PATCH v2 3/3] phy: rockchip-inno-usb2: add support of u2phy for rk3328

[Meng Dongyang]

Add u2phy config information in the data of match table for
rk3328.

Changes in v2:
 - add support of otg port

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 52 ++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index 4ea95c2..0dcccc6 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -1141,6 +1141,57 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
+	{
+		.reg = 0x100,
+		.num_ports	= 2,
+		.phy_tuning	= rk3328_usb2phy_tuning,
+		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
+				.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
+				.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
+				.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
+				.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
+				.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
+				.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
+				.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
+				.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
+				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
+				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
+				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
+				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
+				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
+				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
+				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
+				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
+				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
+			}
+		},
+		.chg_det = {
+			.opmode		= { 0x0100, 3, 0, 5, 1 },
+			.cp_det		= { 0x0120, 24, 24, 0, 1 },
+			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
+			.dp_det		= { 0x0120, 25, 25, 0, 1 },
+			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
 	{
 		.reg = 0x700,
@@ -1223,6 +1274,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
 };
 
 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
+	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
 	{}
-- 
1.9.1

Re: [PATCH v2 1/3] Documentation: bindings: add assign clock property in u2phy node

[Rob Herring]

On Thu, Mar 02, 2017 at 03:49:03PM +0800, Meng Dongyang wrote:
> On some platform such as RK3328, the 480m clock may need to assign
> clock parent in dts in stead of clock driver. So this patch add
> property of assigned-clocks and assigned-clock-parents to assign
> parent for 480m clock.
> 
> Changes in v2:
>  - move u2phy grf specification to grf.txt
> 
> Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
> ---
>  Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 6 ++++++
>  1 file changed, 6 insertions(+)

If you respin, use "dt-bindings: phy: ..." for the subject.

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 2/3] Documentation: bindings: add DT documentation for u2phy and u2phy grf

[Rob Herring]

On Thu, Mar 02, 2017 at 03:49:04PM +0800, Meng Dongyang wrote:
> Due to the u2phy registers are separated from general grf, we need to
> add u2phy grf node and place u2phy node in it. So this patch add u2phy
> grf node.

Similar comment on the subject.

> 
> Changes in v2:
>  - add u2phy grf specification
> 
> Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
> ---
>  Documentation/devicetree/bindings/soc/rockchip/grf.txt | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> index 013e71a..6ac23f9 100644
> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> @@ -7,6 +7,9 @@ From RK3368 SoCs, the GRF is divided into two sections,
>  - GRF, used for general non-secure system,
>  - PMUGRF, used for always on system
>  
> +On RK3328 SoCs, the GRF is divided into three sections,
> +except GRF and PMUGRF, add a section for USB2PHYGRF,
> +
>  Required Properties:
>  
>  - compatible: GRF should be one of the followings
> @@ -19,6 +22,8 @@ Required Properties:
>  - compatible: PMUGRF should be one of the followings
>     - "rockchip,rk3368-pmugrf", "syscon": for rk3368
>     - "rockchip,rk3399-pmugrf", "syscon": for rk3399
> +- compatible: USB2GRF should be one of the followings
> +   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
>  - reg: physical base address of the controller and length of memory mapped
>    region.
>  
> @@ -33,3 +38,13 @@ Example: GRF and PMUGRF of RK3399 SoCs
>  		compatible = "rockchip,rk3399-grf", "syscon";
>  		reg = <0x0 0xff770000 0x0 0x10000>;
>  	};
> +
> +Example: USB2GRF of RK3328 SoCs
> +
> +	usb2phy_grf: syscon@ff450000 {
> +		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
> +			     "simple-mfd";

simple-mfd is not documented. Do you have child nodes?

What makes this a syscon? It has non-PHY registers?


> +		reg = <0x0 0xff450000 0x0 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> -- 
> 1.9.1
> 
> 

Re: [PATCH v2 2/3] Documentation: bindings: add DT documentation for u2phy and u2phy grf

[rock-chips(daniel.meng)]

On 2017/3/3 14:21, Rob Herring wrote:
> On Thu, Mar 02, 2017 at 03:49:04PM +0800, Meng Dongyang wrote:
>> Due to the u2phy registers are separated from general grf, we need to
>> add u2phy grf node and place u2phy node in it. So this patch add u2phy
>> grf node.
> Similar comment on the subject.
>
>> Changes in v2:
>>   - add u2phy grf specification
>>
>> Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
>> ---
>>   Documentation/devicetree/bindings/soc/rockchip/grf.txt | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
>> index 013e71a..6ac23f9 100644
>> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
>> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
>> @@ -7,6 +7,9 @@ From RK3368 SoCs, the GRF is divided into two sections,
>>   - GRF, used for general non-secure system,
>>   - PMUGRF, used for always on system
>>   
>> +On RK3328 SoCs, the GRF is divided into three sections,
>> +except GRF and PMUGRF, add a section for USB2PHYGRF,
>> +
>>   Required Properties:
>>   
>>   - compatible: GRF should be one of the followings
>> @@ -19,6 +22,8 @@ Required Properties:
>>   - compatible: PMUGRF should be one of the followings
>>      - "rockchip,rk3368-pmugrf", "syscon": for rk3368
>>      - "rockchip,rk3399-pmugrf", "syscon": for rk3399
>> +- compatible: USB2GRF should be one of the followings
>> +   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
>>   - reg: physical base address of the controller and length of memory mapped
>>     region.
>>   
>> @@ -33,3 +38,13 @@ Example: GRF and PMUGRF of RK3399 SoCs
>>   		compatible = "rockchip,rk3399-grf", "syscon";
>>   		reg = <0x0 0xff770000 0x0 0x10000>;
>>   	};
>> +
>> +Example: USB2GRF of RK3328 SoCs
>> +
>> +	usb2phy_grf: syscon@ff450000 {
>> +		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
>> +			     "simple-mfd";
> simple-mfd is not documented. Do you have child nodes?
do you mean we need to add a child node of phy here?
>
> What makes this a syscon? It has non-PHY registers?
rk3328 devides grf into three parts and we put all u2phy registers into 
the part of u2phy grf,
so here we add a simple usb2phy_grf.
>
>
>> +		reg = <0x0 0xff450000 0x0 0x10000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +	};
>> -- 
>> 1.9.1
>>
>>
>
>

Re: [PATCH v2 2/3] Documentation: bindings: add DT documentation for u2phy and u2phy grf

[Heiko Stuebner]

Am Freitag, 3. März 2017, 00:21:56 CET schrieb Rob Herring:
> On Thu, Mar 02, 2017 at 03:49:04PM +0800, Meng Dongyang wrote:
> > Due to the u2phy registers are separated from general grf, we need to
> > add u2phy grf node and place u2phy node in it. So this patch add u2phy
> > grf node.
> 
> Similar comment on the subject.
> 
> > Changes in v2:
> >  - add u2phy grf specification
> > 
> > Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
> > ---
> > 
> >  Documentation/devicetree/bindings/soc/rockchip/grf.txt | 15
> >  +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> > b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index
> > 013e71a..6ac23f9 100644
> > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
> > @@ -7,6 +7,9 @@ From RK3368 SoCs, the GRF is divided into two sections,
> > 
> >  - GRF, used for general non-secure system,
> >  - PMUGRF, used for always on system
> > 
> > +On RK3328 SoCs, the GRF is divided into three sections,
> > +except GRF and PMUGRF, add a section for USB2PHYGRF,
> > +
> > 
> >  Required Properties:
> >  
> >  - compatible: GRF should be one of the followings
> > 
> > @@ -19,6 +22,8 @@ Required Properties:
> >  - compatible: PMUGRF should be one of the followings
> >  
> >     - "rockchip,rk3368-pmugrf", "syscon": for rk3368
> >     - "rockchip,rk3399-pmugrf", "syscon": for rk3399
> > 
> > +- compatible: USB2GRF should be one of the followings
> > +   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
> > 
> >  - reg: physical base address of the controller and length of memory
> >  mapped
> >  
> >    region.
> > 
> > @@ -33,3 +38,13 @@ Example: GRF and PMUGRF of RK3399 SoCs
> > 
> >  		compatible = "rockchip,rk3399-grf", "syscon";
> >  		reg = <0x0 0xff770000 0x0 0x10000>;
> >  	
> >  	};
> > 
> > +
> > +Example: USB2GRF of RK3328 SoCs
> > +
> > +	usb2phy_grf: syscon@ff450000 {
> > +		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
> > +			     "simple-mfd";
> 
> simple-mfd is not documented. Do you have child nodes?

Yes, this will have child nodes and I guess we don't really need the 
additional example, that only differs in the compatible.


> What makes this a syscon? It has non-PHY registers?

It is still a "General Register Files" block in all of the socs manual
and yes, that special area also contains registers not used by the phy driver.


Heiko

Re: [PATCH v2 3/3] phy: rockchip-inno-usb2: add support of u2phy for rk3328

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3769 bytes --]

Hi Meng,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.10]
[cannot apply to next-20170303]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Meng-Dongyang/Documentation-bindings-add-assign-clock-property-in-u2phy-node/20170304-192646
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: xtensa-allmodconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 4.9.0
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=xtensa 

All errors (new ones prefixed by >>):

   drivers/phy/phy-rockchip-inno-usb2.c:1143:3: error: unknown field 'phy_tuning' specified in initializer
      .phy_tuning = rk3328_usb2phy_tuning,
      ^
   drivers/phy/phy-rockchip-inno-usb2.c:1143:17: error: 'rk3328_usb2phy_tuning' undeclared here (not in a function)
      .phy_tuning = rk3328_usb2phy_tuning,
                    ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1151:5: error: unknown field 'idfall_det_en' specified in initializer
        .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1152:5: error: unknown field 'idfall_det_st' specified in initializer
        .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1153:5: error: unknown field 'idfall_det_clr' specified in initializer
        .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1154:5: error: unknown field 'idrise_det_en' specified in initializer
        .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1155:5: error: unknown field 'idrise_det_st' specified in initializer
        .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1156:5: error: unknown field 'idrise_det_clr' specified in initializer
        .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
        ^
>> drivers/phy/phy-rockchip-inno-usb2.c:1162:5: error: unknown field 'utmi_iddig' specified in initializer
        .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
        ^

vim +/idfall_det_en +1151 drivers/phy/phy-rockchip-inno-usb2.c

  1137	}
  1138	
  1139	static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
  1140		{
  1141			.reg = 0x100,
  1142			.num_ports	= 2,
> 1143			.phy_tuning	= rk3328_usb2phy_tuning,
  1144			.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
  1145			.port_cfgs	= {
  1146				[USB2PHY_PORT_OTG] = {
  1147					.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
  1148					.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
  1149					.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
  1150					.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
> 1151					.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
> 1152					.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
> 1153					.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
> 1154					.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
> 1155					.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
> 1156					.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
  1157					.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
  1158					.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
  1159					.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
  1160					.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
  1161					.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
> 1162					.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
  1163					.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
  1164				},
  1165				[USB2PHY_PORT_HOST] = {

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 48158 bytes --]