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From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux-foundation.org>
Cc: <bp@alien8.de>, <peterz@infradead.org>, <joro@8bytes.org>,
	<mingo@redhat.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v12 04/10] iommu/amd: Clean up iommu_pc_get_set_reg()
Date: Wed, 22 Mar 2017 02:02:36 -0500	[thread overview]
Message-ID: <1490166162-10002-5-git-send-email-Suravee.Suthikulpanit@amd.com> (raw)
In-Reply-To: <1490166162-10002-1-git-send-email-Suravee.Suthikulpanit@amd.com>

From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Clean up coding style and fix a bug in the 64-bit register read
logic since it overwrites the upper 32-bit when reading the lower 32-bit.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 drivers/iommu/amd_iommu_init.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 6130278..ce65a47 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -2763,22 +2763,25 @@ static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
 	if (WARN_ON((fxn > 0x28) || (fxn & 7)))
 		return -ENODEV;
 
-	offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
+	offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
 
 	/* Limit the offset to the hw defined mmio region aperture */
-	max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
+	max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
 				(iommu->max_counters << 8) | 0x28);
 	if ((offset < MMIO_CNTR_REG_OFFSET) ||
 	    (offset > max_offset_lim))
 		return -EINVAL;
 
 	if (is_write) {
-		writel((u32)*value, iommu->mmio_base + offset);
-		writel((*value >> 32), iommu->mmio_base + offset + 4);
+		u64 val = *value & GENMASK_ULL(47, 0);
+
+		writel((u32)val, iommu->mmio_base + offset);
+		writel((val >> 32), iommu->mmio_base + offset + 4);
 	} else {
 		*value = readl(iommu->mmio_base + offset + 4);
 		*value <<= 32;
-		*value = readl(iommu->mmio_base + offset);
+		*value |= readl(iommu->mmio_base + offset);
+		*value &= GENMASK_ULL(47, 0);
 	}
 
 	return 0;
-- 
1.8.3.1

  parent reply	other threads:[~2017-03-22  7:05 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-22  7:02 [PATCH v12 00/10] perf/amd/iommu: Enable multi-IOMMU support Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 01/10] perf/amd/iommu: Declare pr_fmt and remove unnecessary pr_debug Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 02/10] perf/amd/iommu: Clean up bitwise operations Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 03/10] perf/amd/iommu: Clean up perf_iommu_read() Suravee Suthikulpanit
2017-03-22  7:02 ` Suravee Suthikulpanit [this message]
2017-03-22  7:02 ` [PATCH v12 05/10] iommu/amd: Introduce amd_iommu_get_num_iommus() Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 06/10] perf/amd/iommu: Modify functions to query max banks and counters Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 07/10] perf/amd/iommu: Modify amd_iommu_pc_get_set_reg_val() to allow specifying IOMMU Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 08/10] perf/amd/iommu: Fix sysfs perf attribute groups Suravee Suthikulpanit
2017-03-22  7:02 ` [PATCH v12 09/10] perf/amd/iommu: Introduce amd_iommu-specific struct in struct hw_perf_event Suravee Suthikulpanit
2017-03-24 17:53   ` Borislav Petkov
2017-03-22  7:02 ` [PATCH v12 10/10] perf/amd/iommu: Enable support for multiple IOMMUs Suravee Suthikulpanit
2017-03-30  8:39   ` [tip:perf/core] x86/events/amd/iommu: " tip-bot for Suravee Suthikulpanit

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