From: Xiaoguang Chen <xiaoguang.chen@intel.com>
To: kraxel@redhat.com, alex.williamson@redhat.com,
intel-gfx@lists.freedesktop.org,
intel-gvt-dev@lists.freedesktop.org, zhi.a.wang@intel.com,
zhenyuw@linux.intel.com, linux-kernel@vger.kernel.org,
zhiyuan.lv@intel.com, kevin.tian@intel.com
Cc: Xiaoguang Chen <xiaoguang.chen@intel.com>, Bing Niu <bing.niu@intel.com>
Subject: [RFC PATCH 2/6] drm/i915/gvt: OpRegion support for GVT-g
Date: Fri, 28 Apr 2017 17:35:26 +0800 [thread overview]
Message-ID: <1493372130-27727-3-git-send-email-xiaoguang.chen@intel.com> (raw)
In-Reply-To: <1493372130-27727-1-git-send-email-xiaoguang.chen@intel.com>
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu <bing.niu@intel.com>
Signed-off-by: Xiaoguang Chen <xiaoguang.chen@intel.com>
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 97 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/opregion.c | 12 ++++-
2 files changed, 107 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3c6a02b..389f072 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,6 +53,8 @@
#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
struct vfio_region;
struct intel_vgpu_regops {
size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
@@ -436,6 +438,92 @@ static void kvmgt_protect_table_del(struct kvmgt_guest_info *info,
}
}
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+ size_t count, loff_t *ppos, bool iswrite)
+{
+ unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+ VFIO_PCI_NUM_REGIONS;
+ void *base = vgpu->vdev.region[i].data;
+ loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+ if (pos >= vgpu->vdev.region[i].size || iswrite) {
+ gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+ return -EINVAL;
+ }
+ count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+ memcpy(buf, base + pos, count);
+
+ return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+ struct vfio_region *region)
+{
+ memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+ .rw = intel_vgpu_reg_rw_opregion,
+ .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+ unsigned int type, unsigned int subtype,
+ const struct intel_vgpu_regops *ops,
+ size_t size, u32 flags, void *data)
+{
+ struct vfio_region *region;
+
+ region = krealloc(vgpu->vdev.region,
+ (vgpu->vdev.num_regions + 1) * sizeof(*region),
+ GFP_KERNEL);
+ if (!region)
+ return -ENOMEM;
+
+ vgpu->vdev.region = region;
+ vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+ vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+ vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+ vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+ vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+ vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+ vgpu->vdev.num_regions++;
+
+ return 0;
+}
+
+static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
+{
+ unsigned int addr;
+ void *base;
+ int ret;
+
+ addr = vgpu->gvt->opregion.opregion_pa;
+ if (!addr || !(~addr))
+ return -ENODEV;
+
+ base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+ if (!base)
+ return -ENOMEM;
+
+ if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+ memunmap(base);
+ return -EINVAL;
+ }
+
+ ret = intel_vgpu_register_reg(vgpu,
+ PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
+ VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+ &intel_vgpu_regops_opregion, OPREGION_SIZE,
+ VFIO_REGION_INFO_FLAG_READ, base);
+ if (ret) {
+ memunmap(base);
+ return ret;
+ }
+
+ return ret;
+}
+
static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
{
struct intel_vgpu *vgpu = NULL;
@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
vgpu->vdev.mdev = mdev;
mdev_set_drvdata(mdev, vgpu);
+ ret = intel_vgpu_reg_init_opregion(vgpu);
+ if (ret) {
+ gvt_vgpu_err("create OpRegion failed\n");
+ goto out;
+ }
+
+ gvt_dbg_core("create OpRegion succeeded for mdev:%s\n",
+ dev_name(mdev_dev(mdev)));
+
gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
dev_name(mdev_dev(mdev)));
ret = 0;
diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c
index 3117991..99591bc 100644
--- a/drivers/gpu/drm/i915/gvt/opregion.c
+++ b/drivers/gpu/drm/i915/gvt/opregion.c
@@ -283,14 +283,22 @@ int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci)
{
u32 *scic, *parm;
u32 func, subfunc;
+ u32 scic_val, parm_val;
+ u32 gpa;
- scic = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_SCIC;
- parm = vgpu_opregion(vgpu)->va + INTEL_GVT_OPREGION_PARM;
+ memcpy(&gpa, vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION,
+ sizeof(gpa));
+ intel_gvt_hypervisor_read_gpa(vgpu, gpa + INTEL_GVT_OPREGION_SCIC,
+ &scic_val, sizeof(scic_val));
+ intel_gvt_hypervisor_read_gpa(vgpu, gpa + INTEL_GVT_OPREGION_PARM,
+ &parm_val, sizeof(parm_val));
if (!(swsci & SWSCI_SCI_SELECT)) {
gvt_vgpu_err("requesting SMI service\n");
return 0;
}
+ scic = &scic_val;
+ parm = &parm_val;
/* ignore non 0->1 trasitions */
if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI]
& SWSCI_SCI_TRIGGER) ||
--
1.9.1
next prev parent reply other threads:[~2017-04-28 9:40 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-28 9:35 [RFC PATCH 0/6] drm/i915/gvt: dma-buf support for GVT-g Xiaoguang Chen
2017-04-28 9:35 ` [RFC PATCH 1/6] drm/i915/gvt: extend the GVT-g architecture to support vfio device region Xiaoguang Chen
2017-04-28 9:35 ` Xiaoguang Chen [this message]
2017-04-28 9:35 ` [RFC PATCH 3/6] drm/i915/gvt: framebuffer decoder support for GVT-g Xiaoguang Chen
2017-04-28 9:35 ` [RFC PATCH 4/6] drm/i915: export i915 dmabuf_ops Xiaoguang Chen
2017-04-28 9:35 ` [RFC PATCH 5/6] drm/i915/gvt: dmabuf support for GVT-g Xiaoguang Chen
2017-04-28 10:08 ` [Intel-gfx] " Chris Wilson
2017-05-02 7:40 ` Chen, Xiaoguang
2017-05-04 3:12 ` Chen, Xiaoguang
2017-05-02 9:37 ` Gerd Hoffmann
2017-04-28 9:35 ` [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf Xiaoguang Chen
2017-05-02 9:50 ` Gerd Hoffmann
2017-05-03 1:39 ` Chen, Xiaoguang
2017-05-04 3:09 ` Chen, Xiaoguang
2017-05-04 16:08 ` Alex Williamson
2017-05-05 6:55 ` Gerd Hoffmann
2017-05-05 15:11 ` Alex Williamson
2017-05-11 8:45 ` Chen, Xiaoguang
2017-05-11 13:27 ` Gerd Hoffmann
2017-05-11 15:45 ` Alex Williamson
2017-05-12 2:12 ` Chen, Xiaoguang
2017-05-12 2:58 ` Alex Williamson
2017-05-12 3:52 ` Chen, Xiaoguang
2017-05-12 9:12 ` Gerd Hoffmann
2017-05-12 16:38 ` Alex Williamson
2017-05-15 3:36 ` Chen, Xiaoguang
2017-05-15 17:44 ` Alex Williamson
2017-05-16 10:16 ` Chen, Xiaoguang
2017-05-17 21:43 ` Alex Williamson
2017-05-18 1:51 ` Chen, Xiaoguang
2017-05-18 14:56 ` Alex Williamson
2017-05-19 6:23 ` Chen, Xiaoguang
2017-05-19 8:04 ` Gerd Hoffmann
2017-05-19 8:17 ` Chen, Xiaoguang
2017-05-19 8:57 ` Gerd Hoffmann
2017-05-19 9:14 ` Chen, Xiaoguang
2017-05-19 10:51 ` Gerd Hoffmann
2017-05-18 6:22 ` Gerd Hoffmann
2017-05-12 6:56 ` Chen, Xiaoguang
2017-05-12 17:04 ` Alex Williamson
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