* [PATCH v3 1/4] clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
2017-05-02 7:34 [PATCH v3 0/4] make some special clk as critical_clocks Elaine Zhang
@ 2017-05-02 7:34 ` Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks Elaine Zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: heiko, xf
Cc: mturquette, sboyd, linux-clk, huangtao, xxx, linux-rockchip,
linux-kernel, linux-arm-kernel, Elaine Zhang
No driver to handle this clk, Chip design requirements for this clock to always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 924f560dcf80..e97bee585b2f 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -436,6 +436,7 @@ enum rk3036_plls {
"aclk_peri",
"hclk_peri",
"pclk_peri",
+ "pclk_ddrupctl",
};
static void __init rk3036_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks
2017-05-02 7:34 [PATCH v3 0/4] make some special clk as critical_clocks Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 1/4] clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock Elaine Zhang
@ 2017-05-02 7:34 ` Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 3/4] clk: rockchip: rk3288: " Elaine Zhang
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: heiko, xf
Cc: mturquette, sboyd, linux-clk, huangtao, xxx, linux-rockchip,
linux-kernel, linux-arm-kernel, Elaine Zhang
The jtag\bus\peri\initmem\rom\stimer\phy clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl\ddrmon\ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.
All these non-noc\non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch and bus IDLE(or pd on/off).
The software is not very good to slove this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index db6e5a9e6de6..4d3203f887e2 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -445,7 +445,7 @@ enum rk3228_plls {
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3228_spdif_fracmux),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
GATE(0, "sclk_otgphy0", "xin24m", 0,
@@ -644,9 +644,37 @@ enum rk3228_plls {
static const char *const rk3228_critical_clocks[] __initconst = {
"aclk_cpu",
+ "pclk_cpu",
+ "hclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_peri",
+ "aclk_rga_noc",
+ "aclk_iep_noc",
+ "aclk_vop_noc",
+ "aclk_hdcp_noc",
+ "hclk_vio_ahb_arbi",
+ "hclk_vio_noc",
+ "hclk_vop_noc",
+ "hclk_host0_arb",
+ "hclk_host1_arb",
+ "hclk_host2_arb",
+ "hclk_otg_pmu",
+ "aclk_gpu_noc",
+ "sclk_initmem_mbist",
+ "aclk_initmem",
+ "hclk_rom",
+ "pclk_ddrupctl",
+ "pclk_ddrmon",
+ "pclk_msch_noc",
+ "pclk_stimer",
+ "pclk_ddrphy",
+ "pclk_acodecphy",
+ "pclk_phy_noc",
+ "aclk_vpu_noc",
+ "aclk_rkvdec_noc",
+ "hclk_vpu_noc",
+ "hclk_rkvdec_noc",
};
static void __init rk3228_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/4] clk: rockchip: rk3288: make noc and some special clk as critical_clocks
2017-05-02 7:34 [PATCH v3 0/4] make some special clk as critical_clocks Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 1/4] clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks Elaine Zhang
@ 2017-05-02 7:34 ` Elaine Zhang
2017-05-02 7:34 ` [PATCH v3 4/4] clk: rockchip: rk3368: make " Elaine Zhang
2017-06-02 14:10 ` [PATCH v3 0/4] " Heiko Stuebner
4 siblings, 0 replies; 6+ messages in thread
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: heiko, xf
Cc: mturquette, sboyd, linux-clk, huangtao, xxx, linux-rockchip,
linux-kernel, linux-arm-kernel, Elaine Zhang
The atclk\dbg\jtag\xin12m\pclk_core clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl0\ddrupctl1\publ0\publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The pmu_hclk_otg0 is Chip design defect, must be always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3288.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 68ba7d4105e7..450de24a1b42 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -292,13 +292,13 @@ enum rk3288_plls {
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 6, GFLAGS),
- COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
+ COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 8, GFLAGS),
- GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
+ GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 9, GFLAGS),
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -626,7 +626,7 @@ enum rk3288_plls {
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK3288_CLKSEL_CON(22), 7, IFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -635,7 +635,7 @@ enum rk3288_plls {
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
- GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
+ GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 9, GFLAGS),
DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -816,6 +816,12 @@ enum rk3288_plls {
"pclk_alive_niu",
"pclk_pd_pmu",
"pclk_pmu_niu",
+ "pclk_core_niu",
+ "pclk_ddrupctl0",
+ "pclk_publ0",
+ "pclk_ddrupctl1",
+ "pclk_publ1",
+ "pmu_hclk_otg0",
};
static void __iomem *rk3288_cru_base;
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 4/4] clk: rockchip: rk3368: make some special clk as critical_clocks
2017-05-02 7:34 [PATCH v3 0/4] make some special clk as critical_clocks Elaine Zhang
` (2 preceding siblings ...)
2017-05-02 7:34 ` [PATCH v3 3/4] clk: rockchip: rk3288: " Elaine Zhang
@ 2017-05-02 7:34 ` Elaine Zhang
2017-06-02 14:10 ` [PATCH v3 0/4] " Heiko Stuebner
4 siblings, 0 replies; 6+ messages in thread
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: heiko, xf
Cc: mturquette, sboyd, linux-clk, huangtao, xxx, linux-rockchip,
linux-kernel, linux-arm-kernel, Elaine Zhang
The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.
The ddrphy\ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The pmu_hclk_otg0 is Chip design defect, must be always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3368.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 6cb474c593e7..b38343f9177c 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -638,7 +638,7 @@ enum rk3368_plls {
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 5, GFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
@@ -858,6 +858,9 @@ enum rk3368_plls {
*/
"pclk_pwm1",
"pclk_pd_pmu",
+ "pclk_ddrphy",
+ "pclk_ddrupctl",
+ "pmu_hclk_otg0",
};
static void __init rk3368_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 0/4] make some special clk as critical_clocks
2017-05-02 7:34 [PATCH v3 0/4] make some special clk as critical_clocks Elaine Zhang
` (3 preceding siblings ...)
2017-05-02 7:34 ` [PATCH v3 4/4] clk: rockchip: rk3368: make " Elaine Zhang
@ 2017-06-02 14:10 ` Heiko Stuebner
4 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2017-06-02 14:10 UTC (permalink / raw)
To: Elaine Zhang
Cc: xf, mturquette, sboyd, linux-clk, huangtao, xxx, linux-rockchip,
linux-kernel, linux-arm-kernel
Am Dienstag, 2. Mai 2017, 15:34:02 CEST schrieb Elaine Zhang:
> change in V3:
> reword the commit message,explain why the specific clocks are need to be critical.
>
> change in v2:
> fix up some clks which have their own driver, not need to set as critical clocks
>
> Elaine Zhang (4):
> clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
> clk: rockchip: rk3228: make noc and some special clk as
> critical_clocks
> clk: rockchip: rk3288: make noc and some special clk as
> critical_clocks
> clk: rockchip: rk3368: make some special clk as critical_clocks
applied all 4 for 4.13
Thanks
Heiko
^ permalink raw reply [flat|nested] 6+ messages in thread