From: Geetha sowjanya <gakula@caviumnetworks.com>
To: will.deacon@arm.com, robin.murphy@arm.com,
lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,
sudeep.holla@arm.com, iommu@lists.linux-foundation.org
Cc: jcm@redhat.com, linux-kernel@vger.kernel.org,
robert.richter@cavium.com, catalin.marinas@arm.com,
sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org,
linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com,
linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com,
Geetha Sowjanya <geethasowjanya.akula@cavium.com>
Subject: [PATCH v3 6/7] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Date: Fri, 5 May 2017 17:38:10 +0530 [thread overview]
Message-ID: <1493986091-30521-7-git-send-email-gakula@caviumnetworks.com> (raw)
In-Reply-To: <1493986091-30521-1-git-send-email-gakula@caviumnetworks.com>
From: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
This patch addresses the issue by checking if any interrupt sources are
using same irq number, then they are registered as shared irqs.
Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
---
drivers/iommu/arm-smmu-v3.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 016b702..46428e7 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -2236,10 +2236,30 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
devm_add_action(dev, arm_smmu_free_msis, dev);
}
+static int get_irq_flags(struct arm_smmu_device *smmu, int irq)
+{
+ int match_count = 0;
+
+ if (irq == smmu->evtq.q.irq)
+ match_count++;
+ if (irq == smmu->cmdq.q.irq)
+ match_count++;
+ if (irq == smmu->gerr_irq)
+ match_count++;
+ if (irq == smmu->priq.q.irq)
+ match_count++;
+
+ if (match_count > 1)
+ return IRQF_SHARED | IRQF_ONESHOT;
+
+ return 0;
+}
+
static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
{
int ret, irq;
u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
+ u32 irqflags = 0;
/* Disable IRQs first */
ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
@@ -2254,9 +2274,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
/* Request interrupt lines */
irq = smmu->evtq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_evtq_thread,
- IRQF_ONESHOT,
+ IRQF_ONESHOT | irqflags,
"arm-smmu-v3-evtq", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable evtq irq\n");
@@ -2264,8 +2285,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
irq = smmu->cmdq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_irq(smmu->dev, irq,
- arm_smmu_cmdq_sync_handler, 0,
+ arm_smmu_cmdq_sync_handler, irqflags,
"arm-smmu-v3-cmdq-sync", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n");
@@ -2273,8 +2295,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
irq = smmu->gerr_irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
- 0, "arm-smmu-v3-gerror", smmu);
+ irqflags, "arm-smmu-v3-gerror", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable gerror irq\n");
}
@@ -2282,9 +2305,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
if (smmu->features & ARM_SMMU_FEAT_PRI) {
irq = smmu->priq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_priq_thread,
- IRQF_ONESHOT,
+ IRQF_ONESHOT | irqflags,
"arm-smmu-v3-priq",
smmu);
if (ret < 0)
--
1.8.3.1
next prev parent reply other threads:[~2017-05-05 12:28 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-05 12:08 [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-05-05 12:08 ` [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74 Geetha sowjanya
2017-05-05 22:26 ` Robert Richter
2017-05-05 23:03 ` Robert Richter
2017-05-08 9:17 ` Linu Cherian
2017-05-08 9:29 ` Robert Richter
2017-05-08 9:59 ` Robin Murphy
2017-05-08 10:04 ` Robert Richter
2017-05-05 12:08 ` [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU Geetha sowjanya
2017-05-05 22:18 ` Robert Richter
2017-05-08 9:44 ` Linu Cherian
2017-05-08 10:09 ` Robert Richter
2017-05-08 10:50 ` Linu Cherian
2017-05-08 12:21 ` Robert Richter
2017-05-08 11:03 ` Geetha Akula
2017-05-05 12:08 ` [PATCH v3 3/7] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition Geetha sowjanya
2017-05-05 13:53 ` Hanjun Guo
2017-05-05 14:56 ` David Daney
2017-05-05 14:58 ` Will Deacon
2017-05-05 15:33 ` Jon Masters
2017-05-05 12:08 ` [PATCH v3 4/7] iommu/arm-smmu-v3: For ACPI based device probing, set PAGE0_REGS_ONLY option for ThunderX2 SMMUv3 implementation Geetha sowjanya
2017-05-05 12:08 ` [PATCH v3 5/7] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model Geetha sowjanya
2017-05-05 22:19 ` Robert Richter
2017-05-05 12:08 ` Geetha sowjanya [this message]
2017-05-08 11:21 ` [PATCH v3 6/7] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Robin Murphy
2017-05-08 12:02 ` Geetha Akula
2017-05-05 12:08 ` [PATCH v3 7/7] arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas Geetha sowjanya
2017-05-05 22:22 ` [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds Robert Richter
2017-05-08 15:15 ` Linu Cherian
2017-05-09 16:07 ` Robert Richter
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