[PATCH v2 0/6] Add support for the ICU unit in Marvell Armada 7K/8K

[PATCH v2 0/6] Add support for the ICU unit in Marvell Armada 7K/8K

[Thomas Petazzoni]

Hello,

The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which
contains the CPU cores) and the CP (which contains most
peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs,
doubling the number of available peripherals.

In terms of interrupt handling, all devices in the CPs are connected
through wired interrupt to a unit called ICU located in each CP. This
unit converts the wired interrupts from the devices into memory
transactions.

Inside the AP, there is a GIC extension called GICP, which allows a
memory write transaction to trigger a GIC SPI interrupt. The ICUs in
each CP are therefore configured to trigger a memory write into the
appropriate GICP register so that a wired interrupt from a CP device
is converted into a memory write, itself converted into a regular GIC
SPI interrupt.

Until now, the configuration of the ICU was done statically by the
firmware, and therefore the Device Tree files in Linux were specifying
directly GIC interrupts for the interrupts of CP devices. However,
with the growing number of devices in the CP, a static allocation
scheme doesn't work for the long term.

This patch series therefore makes Linux aware of the ICU: GIC SPI
interrupts are dynamically allocated, and the ICU is configured
accordingly to route a CP wired interrupt to the allocated GIC SPI
interrupt.

In detail:

 - The first two patches are the Device Tree binding patches

 - The third patch is a minimal driver for the GICP unit, which simply
   allows to allocate GICP interrupts.

 - The fourth patch is the most important done, which adds the driver
   for the ICU itself.

 - The fifth patch adjust Kconfig.platforms to select the GICP and ICU
   drivers.

 - The last patch adjusts the Device Tree files of the Armada 7K/8K to
   use the ICU.

Changes since v1:

 - Fix the #interrupt-cells value in the ICU DT binding
   example. Pointed by Marc Zyngier.

 - Add details about the possible group types in the ICU DT binding
   documentation, as requested by Marc Zyngier. This allowed to
   discover that the list of types listed was not matching the macros
   provided in <dt-bindings/interrupt-controller/mvebu-icu.h>, so this
   was fixed as well.

 - Changed the "gicp" property of the ICU to "marvell,gicp", as
   suggested by Marc Zyngier.

 - Add a marvell,spi-ranges property to the gicp node, which defines
   which ranges of GIC SPI interrupts are available for us by the
   GICP.

 - Move more GICP logic into the gicp driver. Indeed, it was confusing
   to have in the ICU driver some global logic mixed with per-ICU
   logic: there is only one GICP per system, but one ICU per CP (so in
   an Armada 8K we have one GICP but two ICUs). So it makes more sense
   to handle the GICP aspects in one driver (which has only one
   device) and the ICU aspects in another driver (which has one device
   per ICU).

 - Use writel_relaxed() as suggested by Marc Zyngier.

 - Use irq_set_irqchip_state() in the ICU driver to clear any pending
   interrupt when allocating an interrupt. This ensures we don't get
   bothered by an interrupt left pending by the firmware. This
   replaces a more manual pending interrupt clearing done in the GICP
   driver, which wasn't suitable for edge triggered
   interrupts. Suggested by Marc Zyngier.

 - Use devm_kstrdup() instead of kstrdup() to fix a potential memory
   leak in the error path of ICU's ->probe() function. Noticed by Marc
   Zyngier.

 - Change compatible strings from "marvell,gicp" to
   "marvell,ap806-gicp" and "marvell,icu" to "marvell,cp110-icu", as
   future versions of those IP blocks may be different. Suggested by
   Yehuda Yitschak.

 - Use a shorter name for the irqchip domain, suggested by Grégory
   Clement.

 - Rename ICU_{SATA0,SATA1}_IRQ_INT to ICU_{SATA0,SATA1}_ICU_ID to
   clarify we're talking about ICU identifiers and not interrupt
   numbers. Suggested by Yehuda Yitschak.

 - Fix bogus message when checking the ICU group type, make sure the
   message says "wrong ICU group type" and not "wrong ICU
   type". Suggested by Yehuda Yitschak.

 - Add a check that the ICU identifier used in the DT is not higher
   than ICU_MAX_IRQS. Suggested by Yehuda Yitschak.

Best regards,

Thomas


Thomas Petazzoni (6):
  dt-bindings: interrupt-controller: add DT binding for the Marvell GICP
  dt-bindings: interrupt-controller: add DT binding for the Marvell ICU
  irqchip: irq-mvebu-gicp: new driver for Marvell GICP
  irqchip: irq-mvebu-icu: new driver for Marvell ICU
  arm64: marvell: enable ICU and GICP drivers
  arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K

 .../bindings/interrupt-controller/marvell,gicp.txt |  24 ++
 .../bindings/interrupt-controller/marvell,icu.txt  |  54 ++++
 arch/arm64/Kconfig.platforms                       |   2 +
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi      |   6 +
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  60 ++--
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |  54 ++--
 drivers/irqchip/Kconfig                            |   6 +
 drivers/irqchip/Makefile                           |   2 +
 drivers/irqchip/irq-mvebu-gicp.c                   | 170 ++++++++++
 drivers/irqchip/irq-mvebu-gicp.h                   |  15 +
 drivers/irqchip/irq-mvebu-icu.c                    | 346 +++++++++++++++++++++
 .../dt-bindings/interrupt-controller/mvebu-icu.h   |  15 +
 12 files changed, 706 insertions(+), 48 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
 create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
 create mode 100644 drivers/irqchip/irq-mvebu-gicp.h
 create mode 100644 drivers/irqchip/irq-mvebu-icu.c
 create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h

-- 
2.7.4

[PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

[Thomas Petazzoni]

This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level in the AP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../bindings/interrupt-controller/marvell,gicp.txt | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
new file mode 100644
index 0000000..3fc36963
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
@@ -0,0 +1,24 @@
+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,ap806-gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
+  for this GICP
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+	compatible = "marvell,ap806-gicp";
+	reg = <0x3f0040 0x10>;
+	marvell,spi-ranges = <64 64>, <288 64>;
+};
-- 
2.7.4

[PATCH v2 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU

[Thomas Petazzoni]

This commit adds the Device Tree binding documentation for the Marvell
ICU interrupt controller, which collects wired interrupts from the
devices located into the CP110 hardware block of Marvell Armada 7K/8K,
and converts them into SPI interrupts in the GIC located in the AP
hardware block, using the GICP extension.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../bindings/interrupt-controller/marvell,icu.txt  | 54 ++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
new file mode 100644
index 0000000..3e7954c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
@@ -0,0 +1,54 @@
+Marvell ICU Interrupt Controller
+--------------------------------
+
+The Marvell ICU (Interrupt Consolidation Unit) controller is
+responsible for collecting all wired-interrupt sources in the CP and
+communicating them to the GIC in the AP, the unit translates interrupt
+requests on input wires to MSG memory mapped transactions to the GIC.
+
+Required properties:
+
+- compatible: Should be "marvell,cp110-icu"
+
+- reg: Should contain ICU registers location and length.
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 3.
+
+  The 1st cell is the group type of the ICU interrupt. Possible group
+  types are:
+
+   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
+   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
+   ICU_GRP_SEI (0x4) : System error interrupt
+   ICU_GRP_REI (0x5) : RAM error interrupt
+
+  The 2nd cell is the index of the interrupt in the ICU unit.
+
+  The 3rd cell is the type of the interrupt. See arm,gic.txt for
+  details.
+
+- interrupt-controller: Identifies the node as an interrupt
+  controller.
+
+- interrupt-parent: Indicates the node of the parent interrupt
+  controller. Should be pointer to the GIC.
+
+- gicp: Should point to the GICP controller, the GIC extension that
+  allows to trigger interrupts using MSG memory mapped transactions.
+
+Example:
+
+icu: interrupt-controller@1e0000 {
+	compatible = "marvell,cp110-icu";
+	reg = <0x1e0000 0x10>;
+	#interrupt-cells = <3>;
+	interrupt-controller;
+	interrupt-parent = <&gic>;
+	marvell,gicp = <&gicp>;
+};
+
+usb3h0: usb3@500000 {
+	interrupt-parent = <&icu>;
+	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.7.4

[PATCH v2 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP

[Thomas Petazzoni]

This commit adds a simple driver for the Marvell GICP, a hardware unit
that converts memory writes into GIC SPI interrupts. The driver provides
a number of functions to the ICU driver to allocate GICP interrupts, and
get the physical addresses that the ICUs should write to to set/clear
interrupts.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/irqchip/Kconfig          |   3 +
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-mvebu-gicp.c | 170 +++++++++++++++++++++++++++++++++++++++
 drivers/irqchip/irq-mvebu-gicp.h |  15 ++++
 4 files changed, 189 insertions(+)
 create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
 create mode 100644 drivers/irqchip/irq-mvebu-gicp.h

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 478f8ac..e527ee5 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -268,6 +268,9 @@ config IRQ_MXS
 	select IRQ_DOMAIN
 	select STMP_DEVICE
 
+config MVEBU_GICP
+	bool
+
 config MVEBU_ODMI
 	bool
 	select GENERIC_MSI_IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b64c59b..11eb858 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100)		+= irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
 obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
+obj-$(CONFIG_MVEBU_GICP)		+= irq-mvebu-gicp.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_MVEBU_PIC)			+= irq-mvebu-pic.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c
new file mode 100644
index 0000000..73c0117
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-gicp.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "irq-mvebu-gicp.h"
+
+#define GICP_SETSPI_NSR_OFFSET	0x0
+#define GICP_CLRSPI_NSR_OFFSET	0x8
+
+struct mvebu_gicp_spi_range {
+	unsigned int start;
+	unsigned int count;
+};
+
+struct mvebu_gicp {
+	struct mvebu_gicp_spi_range *spi_ranges;
+	unsigned int spi_ranges_cnt;
+	unsigned int spi_cnt;
+	unsigned long *spi_bitmap;
+	spinlock_t spi_lock;
+	struct resource *res;
+};
+
+int mvebu_gicp_alloc(struct mvebu_gicp *gicp)
+{
+	int idx;
+
+	spin_lock(&gicp->spi_lock);
+	idx = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
+	if (idx == gicp->spi_cnt) {
+		spin_unlock(&gicp->spi_lock);
+		return -ENOSPC;
+	}
+	set_bit(idx, gicp->spi_bitmap);
+	spin_unlock(&gicp->spi_lock);
+
+	return idx;
+}
+
+void mvebu_gicp_free(struct mvebu_gicp *gicp, int idx)
+{
+	spin_lock(&gicp->spi_lock);
+	clear_bit(idx, gicp->spi_bitmap);
+	spin_unlock(&gicp->spi_lock);
+}
+
+int mvebu_gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
+{
+	int i;
+
+	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
+		struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
+
+		if (idx < r->count)
+			return r->start + idx;
+
+		idx -= r->count;
+	}
+
+	return -EINVAL;
+}
+
+int mvebu_gicp_spi_to_idx(struct mvebu_gicp *gicp, int spi)
+{
+	int i;
+	int idx = 0;
+
+	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
+		struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
+
+		if (spi >= r->start && spi < (r->start + r->count))
+			return idx + (spi - r->start);
+
+		idx += r->count;
+	}
+
+	return -EINVAL;
+}
+
+int mvebu_gicp_spi_count(struct mvebu_gicp *gicp)
+{
+	return gicp->spi_cnt;
+}
+
+phys_addr_t mvebu_gicp_setspi_phys_addr(struct mvebu_gicp *gicp)
+{
+	return gicp->res->start + GICP_SETSPI_NSR_OFFSET;
+}
+
+phys_addr_t mvebu_gicp_clrspi_phys_addr(struct mvebu_gicp *gicp)
+{
+	return gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
+}
+
+static int mvebu_gicp_probe(struct platform_device *pdev)
+{
+	struct mvebu_gicp *gicp;
+	int ret, i;
+
+	gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
+	if (!gicp)
+		return -ENOMEM;
+
+	gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!gicp->res)
+		return -ENODEV;
+
+	ret = of_property_count_u32_elems(pdev->dev.of_node,
+					  "marvell,spi-ranges");
+	if (ret < 0)
+		return ret;
+
+	gicp->spi_ranges_cnt = ret / 2;
+
+	gicp->spi_ranges =
+		devm_kzalloc(&pdev->dev,
+			     gicp->spi_ranges_cnt *
+			     sizeof(struct mvebu_gicp_spi_range),
+			     GFP_KERNEL);
+	if (!gicp->spi_ranges)
+		return -ENOMEM;
+
+	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
+		of_property_read_u32_index(pdev->dev.of_node,
+					   "marvell,spi-ranges",
+					   i * 2,
+					   &gicp->spi_ranges[i].start);
+
+		of_property_read_u32_index(pdev->dev.of_node,
+					   "marvell,spi-ranges",
+					   i * 2 + 1,
+					   &gicp->spi_ranges[i].count);
+
+		gicp->spi_cnt += gicp->spi_ranges[i].count;
+	}
+
+	gicp->spi_bitmap = devm_kzalloc(&pdev->dev,
+					BITS_TO_LONGS(gicp->spi_cnt),
+					GFP_KERNEL);
+	if (!gicp->spi_bitmap)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, gicp);
+
+	return 0;
+}
+
+static const struct of_device_id mvebu_gicp_of_match[] = {
+	{ .compatible = "marvell,ap806-gicp", },
+	{},
+};
+
+static struct platform_driver mvebu_gicp_driver = {
+	.probe  = mvebu_gicp_probe,
+	.driver = {
+		.name = "mvebu-gicp",
+		.of_match_table = mvebu_gicp_of_match,
+	},
+};
+builtin_platform_driver(mvebu_gicp_driver);
diff --git a/drivers/irqchip/irq-mvebu-gicp.h b/drivers/irqchip/irq-mvebu-gicp.h
new file mode 100644
index 0000000..7290166
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-gicp.h
@@ -0,0 +1,15 @@
+#ifndef __MVEBU_GICP_H__
+#define __MVEBU_GICP_H__
+
+struct mvebu_gicp;
+
+int mvebu_gicp_alloc(struct mvebu_gicp *gicp);
+void mvebu_gicp_free(struct mvebu_gicp *gicp, int idx);
+int mvebu_gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx);
+int mvebu_gicp_spi_to_idx(struct mvebu_gicp *gicp, int spi);
+phys_addr_t mvebu_gicp_setspi_phys_addr(struct mvebu_gicp *gicp);
+phys_addr_t mvebu_gicp_clrspi_phys_addr(struct mvebu_gicp *gicp);
+int mvebu_gicp_spi_count(struct mvebu_gicp *gicp);
+
+#endif /* __MVEBU_GICP_H__ */
+
-- 
2.7.4

[PATCH v2 4/6] irqchip: irq-mvebu-icu: new driver for Marvell ICU

[Thomas Petazzoni]

The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.

Until now, the ICU was configured in a static fashion by the firmware,
and Linux was relying on this static configuration. By having Linux
configure the ICU, we are more flexible, and we can allocate dynamically
the GIC SPI interrupts only for devices that are actually in use.

The driver was initially written by Hanna Hawa <hannah@marvell.com>.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/irqchip/Kconfig                            |   3 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-mvebu-icu.c                    | 346 +++++++++++++++++++++
 .../dt-bindings/interrupt-controller/mvebu-icu.h   |  15 +
 4 files changed, 365 insertions(+)
 create mode 100644 drivers/irqchip/irq-mvebu-icu.c
 create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e527ee5..676232a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -271,6 +271,9 @@ config IRQ_MXS
 config MVEBU_GICP
 	bool
 
+config MVEBU_ICU
+	bool
+
 config MVEBU_ODMI
 	bool
 	select GENERIC_MSI_IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 11eb858..18fa5fa 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
 obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
 obj-$(CONFIG_MVEBU_GICP)		+= irq-mvebu-gicp.o
+obj-$(CONFIG_MVEBU_ICU)			+= irq-mvebu-icu.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_MVEBU_PIC)			+= irq-mvebu-pic.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
new file mode 100644
index 0000000..1f6471e
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa <hannah@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
+#include "irq-mvebu-gicp.h"
+
+/* ICU registers */
+#define ICU_SETSPI_NSR_AL	0x10
+#define ICU_SETSPI_NSR_AH	0x14
+#define ICU_CLRSPI_NSR_AL	0x18
+#define ICU_CLRSPI_NSR_AH	0x1c
+#define ICU_INT_CFG(x)          (0x100 + 4 * (x))
+#define   ICU_INT_ENABLE	BIT(24)
+#define   ICU_IS_EDGE		BIT(28)
+#define   ICU_GROUP_SHIFT	29
+
+/* ICU definitions */
+#define ICU_MAX_IRQS		207
+#define ICU_SATA0_ICU_ID	109
+#define ICU_SATA1_ICU_ID	107
+
+struct mvebu_icu {
+	struct irq_chip irq_chip;
+	void __iomem *base;
+	struct irq_domain *domain;
+	struct device *dev;
+	struct mvebu_gicp *gicp;
+};
+
+static int
+mvebu_icu_irq_parent_domain_alloc(struct irq_domain *domain,
+				  unsigned int virq, unsigned int type,
+				  int *irq_msg_num)
+{
+	struct mvebu_icu *icu = domain->host_data;
+	struct irq_fwspec fwspec;
+	int gicp_idx, ret;
+
+	gicp_idx = mvebu_gicp_alloc(icu->gicp);
+	if (gicp_idx < 0) {
+		dev_err(icu->dev, "Cannot allocate GICP interrupt\n");
+		return gicp_idx;
+	}
+
+	fwspec.fwnode = domain->parent->fwnode;
+	fwspec.param_count = 3;
+	fwspec.param[0] = GIC_SPI;
+	fwspec.param[1] = mvebu_gicp_idx_to_spi(icu->gicp, gicp_idx) - 32;
+	fwspec.param[2] = type;
+
+	/* Allocate the IRQ in the parent */
+	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
+	if (ret) {
+		mvebu_gicp_free(icu->gicp, gicp_idx);
+		return ret;
+	}
+
+	*irq_msg_num = gicp_idx;
+
+	return 0;
+}
+
+static void
+mvebu_icu_irq_parent_domain_free(struct irq_domain *domain,
+				 unsigned int virq,
+				 int irq_msg_num)
+{
+	struct mvebu_icu *icu = domain->host_data;
+
+	irq_domain_free_irqs_parent(domain, virq, 1);
+	mvebu_gicp_free(icu->gicp, irq_msg_num);
+}
+
+static int
+mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
+			       unsigned long *hwirq, unsigned int *type)
+{
+	struct mvebu_icu *icu = d->host_data;
+	unsigned int icu_group;
+
+	/* Check the count of the parameters in dt */
+	if (WARN_ON(fwspec->param_count < 3)) {
+		dev_err(icu->dev, "wrong ICU parameter count %d\n",
+			fwspec->param_count);
+		return -EINVAL;
+	}
+
+	/* Only ICU group type is handled */
+	icu_group = fwspec->param[0];
+	if (icu_group != ICU_GRP_NSR && icu_group != ICU_GRP_SR &&
+	    icu_group != ICU_GRP_SEI && icu_group != ICU_GRP_REI) {
+		dev_err(icu->dev, "wrong ICU group type %x\n", icu_group);
+		return -EINVAL;
+	}
+
+	*hwirq = fwspec->param[1];
+	if (*hwirq < 0 || *hwirq >= ICU_MAX_IRQS) {
+		dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
+		return -EINVAL;
+	}
+
+	/* Mask the type to prevent wrong DT configuration */
+	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+
+	return 0;
+}
+
+static int
+mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+			   unsigned int nr_irqs, void *args)
+{
+	int err = 0, irq_msg_num = 0;
+	unsigned long hwirq;
+	unsigned int type = 0;
+	unsigned int icu_group, icu_int;
+	struct irq_fwspec *fwspec = args;
+	struct mvebu_icu *icu = domain->host_data;
+
+	err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq, &type);
+	if (err) {
+		dev_err(icu->dev, "failed to translate ICU parameters\n");
+		return err;
+	}
+
+	icu_group = fwspec->param[0];
+
+	err = mvebu_icu_irq_parent_domain_alloc(domain, virq, type,
+						&irq_msg_num);
+	if (err) {
+		dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
+		return err;
+	}
+
+	/* Configure the ICU with irq number & type */
+	icu_int = irq_msg_num | ICU_INT_ENABLE;
+	if (type & IRQ_TYPE_EDGE_RISING)
+		icu_int |= ICU_IS_EDGE;
+	icu_int |= icu_group << ICU_GROUP_SHIFT;
+	writel_relaxed(icu_int, icu->base + ICU_INT_CFG(hwirq));
+
+	/*
+	 * The SATA unit has 2 ports, and a dedicated ICU entry per
+	 * port. The ahci sata driver supports only one irq interrupt
+	 * per SATA unit. To solve this conflict, we configure the 2
+	 * SATA wired interrupts in the south bridge into 1 GIC
+	 * interrupt in the north bridge. Even if only a single port
+	 * is enabled, if sata node is enabled, both interrupts are
+	 * configured (regardless of which port is actually in use).
+	 */
+	if (hwirq == ICU_SATA0_ICU_ID || hwirq == ICU_SATA1_ICU_ID) {
+		writel_relaxed(icu_int,
+			       icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
+		writel_relaxed(icu_int,
+			       icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
+	}
+
+	/* Make sure there is no interrupt left pending by the firmware */
+	err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
+	if (err) {
+		mvebu_icu_irq_parent_domain_free(domain, virq, irq_msg_num);
+		return err;
+	}
+
+	err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+					    &icu->irq_chip, icu);
+	if (err) {
+		dev_err(icu->dev, "failed to set the data to IRQ domain\n");
+		mvebu_icu_irq_parent_domain_free(domain, virq, irq_msg_num);
+		return err;
+	}
+
+	return 0;
+}
+
+static void
+mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
+			  unsigned int nr_irqs)
+{
+	struct mvebu_icu *icu = domain->host_data;
+	struct irq_data *irq = irq_get_irq_data(virq);
+	struct irq_data *irq_parent = irq->parent_data;
+	int irq_msg_num;
+
+	irq_msg_num = mvebu_gicp_spi_to_idx(icu->gicp,
+					    irqd_to_hwirq(irq_parent));
+
+	WARN_ON(nr_irqs != 1);
+
+	writel_relaxed(0, icu->base + ICU_INT_CFG(irqd_to_hwirq(irq)));
+
+	mvebu_icu_irq_parent_domain_free(domain, virq, irq_msg_num);
+}
+
+static const struct irq_domain_ops mvebu_icu_domain_ops = {
+	.translate = mvebu_icu_irq_domain_translate,
+	.alloc     = mvebu_icu_irq_domain_alloc,
+	.free      = mvebu_icu_irq_domain_free,
+};
+
+static int mvebu_icu_probe(struct platform_device *pdev)
+{
+	struct mvebu_icu *icu;
+	struct irq_domain *parent_domain;
+	struct device_node *node = pdev->dev.of_node;
+	struct platform_device *gicp_pdev;
+	struct device_node *parent_irq_dn;
+	struct device_node *gicp_dn;
+	struct resource *res;
+	struct resource *gicp_res;
+	phys_addr_t setspi, clrspi;
+	u32 i, icu_int;
+
+	icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
+			   GFP_KERNEL);
+	if (!icu)
+		return -ENOMEM;
+
+	icu->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	icu->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(icu->base)) {
+		dev_err(&pdev->dev, "Failed to map icu base address.\n");
+		return PTR_ERR(icu->base);
+	}
+
+	icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+					    "ICU.%x",
+					    (unsigned int)res->start);
+	if (!icu->irq_chip.name)
+		return -ENOMEM;
+
+	icu->irq_chip.irq_mask = irq_chip_mask_parent;
+	icu->irq_chip.irq_unmask = irq_chip_unmask_parent;
+	icu->irq_chip.irq_eoi = irq_chip_eoi_parent;
+	icu->irq_chip.irq_set_type = irq_chip_set_type_parent;
+#ifdef CONFIG_SMP
+	icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent;
+#endif
+
+	gicp_dn = of_parse_phandle(node, "marvell,gicp", 0);
+	if (!gicp_dn) {
+		dev_err(&pdev->dev, "Missing marvell,gicp property.\n");
+		return -ENODEV;
+	}
+
+	gicp_pdev = of_find_device_by_node(gicp_dn);
+	if (!gicp_pdev) {
+		dev_err(&pdev->dev, "Cannot find gicp device.\n");
+		return -ENODEV;
+	}
+
+	icu->gicp = platform_get_drvdata(gicp_pdev);
+
+	gicp_res = platform_get_resource(gicp_pdev, IORESOURCE_MEM, 0);
+	if (!gicp_res) {
+		dev_err(&pdev->dev, "Failed to get gicp resource\n");
+		return -ENODEV;
+	}
+
+	parent_irq_dn = of_irq_find_parent(node);
+	if (!parent_irq_dn) {
+		dev_err(&pdev->dev, "failed to find parent IRQ node\n");
+		return -ENODEV;
+	}
+
+	parent_domain = irq_find_host(parent_irq_dn);
+	if (!parent_domain) {
+		dev_err(&pdev->dev, "Unable to locate ICU parent domain\n");
+		return -ENODEV;
+	}
+
+	get_device(&gicp_pdev->dev);
+
+	/*
+	 * We need the GICP to be probed() before us
+	 */
+	if (!device_is_bound(&gicp_pdev->dev))
+		return -EPROBE_DEFER;
+
+	/* Set Clear/Set ICU SPI message address in AP */
+	setspi = mvebu_gicp_setspi_phys_addr(icu->gicp);
+	writel_relaxed(upper_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AH);
+	writel_relaxed(lower_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AL);
+	clrspi = mvebu_gicp_clrspi_phys_addr(icu->gicp);
+	writel_relaxed(upper_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AH);
+	writel_relaxed(lower_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AL);
+
+	/*
+	 * Clean all ICU interrupts with type SPI_NSR, required to
+	 * avoid unpredictable SPI assignments done by firmware.
+	 */
+	for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
+		icu_int = readl(icu->base + ICU_INT_CFG(i));
+		if ((icu_int >> ICU_GROUP_SHIFT) == ICU_GRP_NSR)
+			writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
+	}
+
+	icu->domain =
+		irq_domain_add_hierarchy(parent_domain, 0,
+					 mvebu_gicp_spi_count(icu->gicp),
+					 node, &mvebu_icu_domain_ops, icu);
+	if (!icu->domain) {
+		dev_err(&pdev->dev, "Failed to create ICU domain\n");
+		put_device(&gicp_pdev->dev);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id mvebu_icu_of_match[] = {
+	{ .compatible = "marvell,cp110-icu", },
+	{},
+};
+
+static struct platform_driver mvebu_icu_driver = {
+	.probe  = mvebu_icu_probe,
+	.driver = {
+		.name = "mvebu-icu",
+		.of_match_table = mvebu_icu_of_match,
+	},
+};
+builtin_platform_driver(mvebu_icu_driver);
diff --git a/include/dt-bindings/interrupt-controller/mvebu-icu.h b/include/dt-bindings/interrupt-controller/mvebu-icu.h
new file mode 100644
index 0000000..8249558
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/mvebu-icu.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for the MVEBU ICU driver.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+
+/* interrupt specifier cell 0 */
+
+#define ICU_GRP_NSR		0x0
+#define ICU_GRP_SR		0x1
+#define ICU_GRP_SEI		0x4
+#define ICU_GRP_REI		0x5
+
+#endif
-- 
2.7.4

[PATCH v2 5/6] arm64: marvell: enable ICU and GICP drivers

[Thomas Petazzoni]

This commit enables the newly introduced Marvell GICP and ICUs driver
for the 64-bit Marvell EBU platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm64/Kconfig.platforms | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4afcffc..bf3b505 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -106,6 +106,8 @@ config ARCH_MVEBU
 	select ARMADA_AP806_SYSCON
 	select ARMADA_CP110_SYSCON
 	select ARMADA_37XX_CLK
+	select MVEBU_GICP
+	select MVEBU_ICU
 	select MVEBU_ODMI
 	select MVEBU_PIC
 	help
-- 
2.7.4

[PATCH v2 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K

[Thomas Petazzoni]

This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi      |  6 +++
 .../boot/dts/marvell/armada-cp110-master.dtsi      | 60 +++++++++++++---------
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 54 ++++++++++---------
 3 files changed, 72 insertions(+), 48 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index fe41bf9..91dca05 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -146,6 +146,12 @@
 				marvell,spi-base = <128>, <136>, <144>, <152>;
 			};
 
+			gicp: gicp@3f0040 {
+				compatible = "marvell,ap806-gicp";
+				reg = <0x3f0040 0x10>;
+				marvell,spi-ranges = <64 64>, <288 64>;
+			};
+
 			pic: interrupt-controller@3f0100 {
 				compatible = "marvell,armada-8k-pic";
 				reg = <0x3f0100 0x10>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index ac8df52..00af338 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -44,19 +44,20 @@
  * Device Tree file for Marvell Armada CP110 Master.
  */
 
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
 / {
 	cp110-master {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
+		interrupt-parent = <&cpm_icu>;
 		ranges;
 
 		config-space@f2000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";
-			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf2000000 0x2000000>;
 
 			cpm_ethernet: ethernet@0 {
@@ -68,21 +69,21 @@
 				dma-coherent;
 
 				cpm_eth0: eth0 {
-					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";
 				};
 
 				cpm_eth1: eth1 {
-					interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";
 				};
 
 				cpm_eth2: eth2 {
-					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";
@@ -96,6 +97,15 @@
 				reg = <0x12a200 0x10>;
 			};
 
+			cpm_icu: interrupt-controller@1e0000 {
+				compatible = "marvell,cp110-icu";
+				reg = <0x1e0000 0x10>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				marvell,gicp = <&gicp>;
+			};
+
 			cpm_syscon0: system-controller@440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";
@@ -120,14 +130,14 @@
 				compatible = "marvell,armada-8k-rtc";
 				reg = <0x284000 0x20>, <0x284080 0x24>;
 				reg-names = "rtc", "rtc-soc";
-				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			cpm_sata0: sata@540000 {
 				compatible = "marvell,armada-8k-ahci",
 					     "generic-ahci";
 				reg = <0x540000 0x30000>;
-				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 15>;
 				status = "disabled";
 			};
@@ -137,7 +147,7 @@
 					     "generic-xhci";
 				reg = <0x500000 0x4000>;
 				dma-coherent;
-				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 22>;
 				status = "disabled";
 			};
@@ -147,7 +157,7 @@
 					     "generic-xhci";
 				reg = <0x510000 0x4000>;
 				dma-coherent;
-				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 23>;
 				status = "disabled";
 			};
@@ -195,7 +205,7 @@
 				reg = <0x701000 0x20>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 21>;
 				status = "disabled";
 			};
@@ -205,7 +215,7 @@
 				reg = <0x701100 0x20>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 21>;
 				status = "disabled";
 			};
@@ -213,7 +223,7 @@
 			cpm_trng: trng@760000 {
 				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 				reg = <0x760000 0x7d>;
-				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_syscon0 1 25>;
 				status = "okay";
 			};
@@ -221,7 +231,7 @@
 			cpm_sdhci0: sdhci@780000 {
 				compatible = "marvell,armada-cp110-sdhci";
 				reg = <0x780000 0x300>;
-				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
 				clock-names = "core";
 				clocks = <&cpm_syscon0 1 4>;
 				dma-coherent;
@@ -231,13 +241,13 @@
 			cpm_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
 				| IRQ_TYPE_LEVEL_HIGH)>,
-					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+					     <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_syscon0 1 26>;
@@ -264,8 +274,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 			num-lanes = <1>;
 			clocks = <&cpm_syscon0 1 13>;
 			status = "disabled";
@@ -290,8 +300,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xf7000000 0  0xf7000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 
 			num-lanes = <1>;
 			clocks = <&cpm_syscon0 1 11>;
@@ -317,8 +327,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xf8000000 0  0xf8000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 
 			num-lanes = <1>;
 			clocks = <&cpm_syscon0 1 12>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 7740a75..bee48ae 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -49,14 +49,13 @@
 		#address-cells = <2>;
 		#size-cells = <2>;
 		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
+		interrupt-parent = <&cps_icu>;
 		ranges;
 
 		config-space@f4000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";
-			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf4000000 0x2000000>;
 
 			cps_rtc: rtc@284000 {
@@ -75,21 +74,21 @@
 				dma-coherent;
 
 				cps_eth0: eth0 {
-					interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <0>;
 					gop-port-id = <0>;
 					status = "disabled";
 				};
 
 				cps_eth1: eth1 {
-					interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <1>;
 					gop-port-id = <2>;
 					status = "disabled";
 				};
 
 				cps_eth2: eth2 {
-					interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
 					port-id = <2>;
 					gop-port-id = <3>;
 					status = "disabled";
@@ -103,6 +102,15 @@
 				reg = <0x12a200 0x10>;
 			};
 
+			cps_icu: interrupt-controller@1e0000 {
+				compatible = "marvell,cp110-icu";
+				reg = <0x1e0000 0x10>;
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				interrupt-parent = <&gic>;
+				marvell,gicp = <&gicp>;
+			};
+
 			cps_syscon0: system-controller@440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";
@@ -127,7 +135,7 @@
 				compatible = "marvell,armada-8k-ahci",
 					     "generic-ahci";
 				reg = <0x540000 0x30000>;
-				interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 15>;
 				status = "disabled";
 			};
@@ -137,7 +145,7 @@
 					     "generic-xhci";
 				reg = <0x500000 0x4000>;
 				dma-coherent;
-				interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 22>;
 				status = "disabled";
 			};
@@ -147,7 +155,7 @@
 					     "generic-xhci";
 				reg = <0x510000 0x4000>;
 				dma-coherent;
-				interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 23>;
 				status = "disabled";
 			};
@@ -195,7 +203,7 @@
 				reg = <0x701000 0x20>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 21>;
 				status = "disabled";
 			};
@@ -205,7 +213,7 @@
 				reg = <0x701100 0x20>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 21>;
 				status = "disabled";
 			};
@@ -213,7 +221,7 @@
 			cps_trng: trng@760000 {
 				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 				reg = <0x760000 0x7d>;
-				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cps_syscon0 1 25>;
 				status = "okay";
 			};
@@ -221,13 +229,13 @@
 			cps_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
 				| IRQ_TYPE_LEVEL_HIGH)>,
-					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+					     <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+					     <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "mem", "ring0", "ring1",
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_syscon0 1 26>;
@@ -254,8 +262,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 			num-lanes = <1>;
 			clocks = <&cps_syscon0 1 13>;
 			status = "disabled";
@@ -280,8 +288,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 
 			num-lanes = <1>;
 			clocks = <&cps_syscon0 1 11>;
@@ -307,8 +315,8 @@
 				/* non-prefetchable memory */
 				0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
 			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
-			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 
 			num-lanes = <1>;
 			clocks = <&cps_syscon0 1 12>;
-- 
2.7.4

Re: [PATCH v2 0/6] Add support for the ICU unit in Marvell Armada 7K/8K

[Gregory CLEMENT]

Hi Thomas,
 
 On ven., juin 02 2017, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:

> Hello,
>
> The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which
> contains the CPU cores) and the CP (which contains most
> peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs,
> doubling the number of available peripherals.
>
> In terms of interrupt handling, all devices in the CPs are connected
> through wired interrupt to a unit called ICU located in each CP. This
> unit converts the wired interrupts from the devices into memory
> transactions.
>
> Inside the AP, there is a GIC extension called GICP, which allows a
> memory write transaction to trigger a GIC SPI interrupt. The ICUs in
> each CP are therefore configured to trigger a memory write into the
> appropriate GICP register so that a wired interrupt from a CP device
> is converted into a memory write, itself converted into a regular GIC
> SPI interrupt.
>
> Until now, the configuration of the ICU was done statically by the
> firmware, and therefore the Device Tree files in Linux were specifying
> directly GIC interrupts for the interrupts of CP devices. However,
> with the growing number of devices in the CP, a static allocation
> scheme doesn't work for the long term.
>
> This patch series therefore makes Linux aware of the ICU: GIC SPI
> interrupts are dynamically allocated, and the ICU is configured
> accordingly to route a CP wired interrupt to the allocated GIC SPI
> interrupt.
>
> In detail:
>
>  - The first two patches are the Device Tree binding patches
>
>  - The third patch is a minimal driver for the GICP unit, which simply
>    allows to allocate GICP interrupts.
>
>  - The fourth patch is the most important done, which adds the driver
>    for the ICU itself.
>
>  - The fifth patch adjust Kconfig.platforms to select the GICP and ICU
>    drivers.
>
>  - The last patch adjusts the Device Tree files of the Armada 7K/8K to
>    use the ICU.
>
> Changes since v1:
>
>  - Fix the #interrupt-cells value in the ICU DT binding
>    example. Pointed by Marc Zyngier.
>
>  - Add details about the possible group types in the ICU DT binding
>    documentation, as requested by Marc Zyngier. This allowed to
>    discover that the list of types listed was not matching the macros
>    provided in <dt-bindings/interrupt-controller/mvebu-icu.h>, so this
>    was fixed as well.
>
>  - Changed the "gicp" property of the ICU to "marvell,gicp", as
>    suggested by Marc Zyngier.
>
>  - Add a marvell,spi-ranges property to the gicp node, which defines
>    which ranges of GIC SPI interrupts are available for us by the
>    GICP.
>
>  - Move more GICP logic into the gicp driver. Indeed, it was confusing
>    to have in the ICU driver some global logic mixed with per-ICU
>    logic: there is only one GICP per system, but one ICU per CP (so in
>    an Armada 8K we have one GICP but two ICUs). So it makes more sense
>    to handle the GICP aspects in one driver (which has only one
>    device) and the ICU aspects in another driver (which has one device
>    per ICU).
>
>  - Use writel_relaxed() as suggested by Marc Zyngier.
>
>  - Use irq_set_irqchip_state() in the ICU driver to clear any pending
>    interrupt when allocating an interrupt. This ensures we don't get
>    bothered by an interrupt left pending by the firmware. This
>    replaces a more manual pending interrupt clearing done in the GICP
>    driver, which wasn't suitable for edge triggered
>    interrupts. Suggested by Marc Zyngier.
>
>  - Use devm_kstrdup() instead of kstrdup() to fix a potential memory
>    leak in the error path of ICU's ->probe() function. Noticed by Marc
>    Zyngier.
>
>  - Change compatible strings from "marvell,gicp" to
>    "marvell,ap806-gicp" and "marvell,icu" to "marvell,cp110-icu", as
>    future versions of those IP blocks may be different. Suggested by
>    Yehuda Yitschak.
>
>  - Use a shorter name for the irqchip domain, suggested by Grégory
>    Clement.
>
>  - Rename ICU_{SATA0,SATA1}_IRQ_INT to ICU_{SATA0,SATA1}_ICU_ID to
>    clarify we're talking about ICU identifiers and not interrupt
>    numbers. Suggested by Yehuda Yitschak.
>
>  - Fix bogus message when checking the ICU group type, make sure the
>    message says "wrong ICU group type" and not "wrong ICU
>    type". Suggested by Yehuda Yitschak.
>
>  - Add a check that the ICU identifier used in the DT is not higher
>    than ICU_MAX_IRQS. Suggested by Yehuda Yitschak.
>
> Best regards,
>
> Thomas
>
>
> Thomas Petazzoni (6):
>   dt-bindings: interrupt-controller: add DT binding for the Marvell GICP
>   dt-bindings: interrupt-controller: add DT binding for the Marvell ICU
>   irqchip: irq-mvebu-gicp: new driver for Marvell GICP
>   irqchip: irq-mvebu-icu: new driver for Marvell ICU
>   arm64: marvell: enable ICU and GICP drivers
>   arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K

The series looks very good now, for all the patches:
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Once the binding and the drivers will be approved I will applu patch 5
and 6 to the mvebu trees.

Thanks,

Gregory


>
>  .../bindings/interrupt-controller/marvell,gicp.txt |  24 ++
>  .../bindings/interrupt-controller/marvell,icu.txt  |  54 ++++
>  arch/arm64/Kconfig.platforms                       |   2 +
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi      |   6 +
>  .../boot/dts/marvell/armada-cp110-master.dtsi      |  60 ++--
>  .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |  54 ++--
>  drivers/irqchip/Kconfig                            |   6 +
>  drivers/irqchip/Makefile                           |   2 +
>  drivers/irqchip/irq-mvebu-gicp.c                   | 170 ++++++++++
>  drivers/irqchip/irq-mvebu-gicp.h                   |  15 +
>  drivers/irqchip/irq-mvebu-icu.c                    | 346 +++++++++++++++++++++
>  .../dt-bindings/interrupt-controller/mvebu-icu.h   |  15 +
>  12 files changed, 706 insertions(+), 48 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
>  create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
>  create mode 100644 drivers/irqchip/irq-mvebu-gicp.h
>  create mode 100644 drivers/irqchip/irq-mvebu-icu.c
>  create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h
>
> -- 
> 2.7.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

[Rob Herring]

On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> This commit adds the Device Tree binding documentation for the Marvell
> GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> using memory transactions. It is used by the ICU unit in the Marvell
> CP110 block to turn wired interrupts inside the CP into SPI interrupts
> at the GIC level in the AP.

Sounds like an MSI block?

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  .../bindings/interrupt-controller/marvell,gicp.txt | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> new file mode 100644
> index 0000000..3fc36963
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> @@ -0,0 +1,24 @@
> +Marvell GICP Controller
> +-----------------------
> +
> +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
> +interrupts by doing a memory transaction. It is used by the ICU
> +located in the Marvell CP110 to turn wired interrupts inside the CP
> +into GIC SPI interrupts.
> +
> +Required properties:
> +
> +- compatible: Must be "marvell,ap806-gicp"
> +
> +- reg: Must be the address and size of the GICP SPI registers
> +
> +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> +  for this GICP

These are base+size?

> +
> +Example:
> +
> +gicp_spi: gicp-spi@3f0040 {
> +	compatible = "marvell,ap806-gicp";
> +	reg = <0x3f0040 0x10>;
> +	marvell,spi-ranges = <64 64>, <288 64>;
> +};
> -- 
> 2.7.4
> 

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU

[Rob Herring]

On Fri, Jun 02, 2017 at 12:06:53PM +0200, Thomas Petazzoni wrote:
> This commit adds the Device Tree binding documentation for the Marvell
> ICU interrupt controller, which collects wired interrupts from the
> devices located into the CP110 hardware block of Marvell Armada 7K/8K,
> and converts them into SPI interrupts in the GIC located in the AP
> hardware block, using the GICP extension.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  .../bindings/interrupt-controller/marvell,icu.txt  | 54 ++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> new file mode 100644
> index 0000000..3e7954c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
> @@ -0,0 +1,54 @@
> +Marvell ICU Interrupt Controller
> +--------------------------------
> +
> +The Marvell ICU (Interrupt Consolidation Unit) controller is
> +responsible for collecting all wired-interrupt sources in the CP and
> +communicating them to the GIC in the AP, the unit translates interrupt
> +requests on input wires to MSG memory mapped transactions to the GIC.
> +
> +Required properties:
> +
> +- compatible: Should be "marvell,cp110-icu"
> +
> +- reg: Should contain ICU registers location and length.
> +
> +- #interrupt-cells: Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 3.
> +
> +  The 1st cell is the group type of the ICU interrupt. Possible group
> +  types are:
> +
> +   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
> +   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
> +   ICU_GRP_SEI (0x4) : System error interrupt
> +   ICU_GRP_REI (0x5) : RAM error interrupt
> +
> +  The 2nd cell is the index of the interrupt in the ICU unit.
> +
> +  The 3rd cell is the type of the interrupt. See arm,gic.txt for
> +  details.
> +
> +- interrupt-controller: Identifies the node as an interrupt
> +  controller.
> +
> +- interrupt-parent: Indicates the node of the parent interrupt
> +  controller. Should be pointer to the GIC.
> +
> +- gicp: Should point to the GICP controller, the GIC extension that
> +  allows to trigger interrupts using MSG memory mapped transactions.
> +
> +Example:
> +
> +icu: interrupt-controller@1e0000 {
> +	compatible = "marvell,cp110-icu";
> +	reg = <0x1e0000 0x10>;
> +	#interrupt-cells = <3>;
> +	interrupt-controller;
> +	interrupt-parent = <&gic>;

If you have a parent, then you should have some interrupts. I guess that 
would be your ranges property? I suppose that is fine.

> +	marvell,gicp = <&gicp>;
> +};
> +
> +usb3h0: usb3@500000 {
> +	interrupt-parent = <&icu>;
> +	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
> +};
> -- 
> 2.7.4
> 

Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

[Marc Zyngier]

On 07/06/17 23:24, Rob Herring wrote:
> On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
>> This commit adds the Device Tree binding documentation for the Marvell
>> GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
>> using memory transactions. It is used by the ICU unit in the Marvell
>> CP110 block to turn wired interrupts inside the CP into SPI interrupts
>> at the GIC level in the AP.
> 
> Sounds like an MSI block?

Almost. It also allows to deal with level interrupts, which a classic
MSI controller cannot manage. This looks like it has been lifted from
the GICv3 spec, which offers the exact same mechanism for SPIs.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

[Thomas Petazzoni]

Hello,

On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote:
> On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> > This commit adds the Device Tree binding documentation for the Marvell
> > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> > using memory transactions. It is used by the ICU unit in the Marvell
> > CP110 block to turn wired interrupts inside the CP into SPI interrupts
> > at the GIC level in the AP.  
> 
> Sounds like an MSI block?

Marc Zyngier answered on this (much better than I could have done).

> > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> > +  for this GICP  
> 
> These are base+size?

Correct. Does your question suggest that I should update the binding
document to make this explicit?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU

[Thomas Petazzoni]

Hello,

On Wed, 7 Jun 2017 17:33:17 -0500, Rob Herring wrote:

> > +Example:
> > +
> > +icu: interrupt-controller@1e0000 {
> > +	compatible = "marvell,cp110-icu";
> > +	reg = <0x1e0000 0x10>;
> > +	#interrupt-cells = <3>;
> > +	interrupt-controller;
> > +	interrupt-parent = <&gic>;  
> 
> If you have a parent, then you should have some interrupts. I guess that 
> would be your ranges property? I suppose that is fine.

The ranges of interrupts available is defined by the gicp node. Indeed,
as explained in the cover letter:

 - We have one GICP in the SoC, providing a number of GIC SPI interrupts

 - We have one ICU per CP in the SoC. So for example in the Armada 8K,
   we have two CPs, and therefore two ICUs.

So the range of available GIC SPI interrupts it not associated to each
ICU, it's a global range of GIC SPI interrupts: each can freely be
allocated by any of the ICUs in the system.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH v2 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP

[Marc Zyngier]

Hi Thomas,

On 02/06/17 11:06, Thomas Petazzoni wrote:
> This commit adds a simple driver for the Marvell GICP, a hardware unit
> that converts memory writes into GIC SPI interrupts. The driver provides
> a number of functions to the ICU driver to allocate GICP interrupts, and
> get the physical addresses that the ICUs should write to to set/clear
> interrupts.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  drivers/irqchip/Kconfig          |   3 +
>  drivers/irqchip/Makefile         |   1 +
>  drivers/irqchip/irq-mvebu-gicp.c | 170 +++++++++++++++++++++++++++++++++++++++
>  drivers/irqchip/irq-mvebu-gicp.h |  15 ++++
>  4 files changed, 189 insertions(+)
>  create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
>  create mode 100644 drivers/irqchip/irq-mvebu-gicp.h
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 478f8ac..e527ee5 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -268,6 +268,9 @@ config IRQ_MXS
>  	select IRQ_DOMAIN
>  	select STMP_DEVICE
>  
> +config MVEBU_GICP
> +	bool
> +
>  config MVEBU_ODMI
>  	bool
>  	select GENERIC_MSI_IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b64c59b..11eb858 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100)		+= irq-sa11x0.o
>  obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
>  obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
>  obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
> +obj-$(CONFIG_MVEBU_GICP)		+= irq-mvebu-gicp.o
>  obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
>  obj-$(CONFIG_MVEBU_PIC)			+= irq-mvebu-pic.o
>  obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
> diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c
> new file mode 100644
> index 0000000..73c0117
> --- /dev/null
> +++ b/drivers/irqchip/irq-mvebu-gicp.c
> @@ -0,0 +1,170 @@
> +/*
> + * Copyright (C) 2017 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include "irq-mvebu-gicp.h"
> +
> +#define GICP_SETSPI_NSR_OFFSET	0x0
> +#define GICP_CLRSPI_NSR_OFFSET	0x8
> +
> +struct mvebu_gicp_spi_range {
> +	unsigned int start;
> +	unsigned int count;
> +};
> +
> +struct mvebu_gicp {
> +	struct mvebu_gicp_spi_range *spi_ranges;
> +	unsigned int spi_ranges_cnt;
> +	unsigned int spi_cnt;
> +	unsigned long *spi_bitmap;
> +	spinlock_t spi_lock;
> +	struct resource *res;
> +};
> +
> +int mvebu_gicp_alloc(struct mvebu_gicp *gicp)
> +{
> +	int idx;
> +
> +	spin_lock(&gicp->spi_lock);
> +	idx = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
> +	if (idx == gicp->spi_cnt) {
> +		spin_unlock(&gicp->spi_lock);
> +		return -ENOSPC;
> +	}
> +	set_bit(idx, gicp->spi_bitmap);
> +	spin_unlock(&gicp->spi_lock);
> +
> +	return idx;
> +}
> +
> +void mvebu_gicp_free(struct mvebu_gicp *gicp, int idx)
> +{
> +	spin_lock(&gicp->spi_lock);
> +	clear_bit(idx, gicp->spi_bitmap);
> +	spin_unlock(&gicp->spi_lock);
> +}
> +
> +int mvebu_gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
> +{
> +	int i;
> +
> +	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
> +		struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
> +
> +		if (idx < r->count)
> +			return r->start + idx;
> +
> +		idx -= r->count;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +int mvebu_gicp_spi_to_idx(struct mvebu_gicp *gicp, int spi)
> +{
> +	int i;
> +	int idx = 0;
> +
> +	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
> +		struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
> +
> +		if (spi >= r->start && spi < (r->start + r->count))
> +			return idx + (spi - r->start);
> +
> +		idx += r->count;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +int mvebu_gicp_spi_count(struct mvebu_gicp *gicp)
> +{
> +	return gicp->spi_cnt;
> +}
> +
> +phys_addr_t mvebu_gicp_setspi_phys_addr(struct mvebu_gicp *gicp)
> +{
> +	return gicp->res->start + GICP_SETSPI_NSR_OFFSET;
> +}
> +
> +phys_addr_t mvebu_gicp_clrspi_phys_addr(struct mvebu_gicp *gicp)
> +{
> +	return gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
> +}
> +
> +static int mvebu_gicp_probe(struct platform_device *pdev)
> +{
> +	struct mvebu_gicp *gicp;
> +	int ret, i;
> +
> +	gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
> +	if (!gicp)
> +		return -ENOMEM;
> +
> +	gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!gicp->res)
> +		return -ENODEV;
> +
> +	ret = of_property_count_u32_elems(pdev->dev.of_node,
> +					  "marvell,spi-ranges");
> +	if (ret < 0)
> +		return ret;
> +
> +	gicp->spi_ranges_cnt = ret / 2;
> +
> +	gicp->spi_ranges =
> +		devm_kzalloc(&pdev->dev,
> +			     gicp->spi_ranges_cnt *
> +			     sizeof(struct mvebu_gicp_spi_range),
> +			     GFP_KERNEL);
> +	if (!gicp->spi_ranges)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
> +		of_property_read_u32_index(pdev->dev.of_node,
> +					   "marvell,spi-ranges",
> +					   i * 2,
> +					   &gicp->spi_ranges[i].start);
> +
> +		of_property_read_u32_index(pdev->dev.of_node,
> +					   "marvell,spi-ranges",
> +					   i * 2 + 1,
> +					   &gicp->spi_ranges[i].count);
> +
> +		gicp->spi_cnt += gicp->spi_ranges[i].count;
> +	}
> +
> +	gicp->spi_bitmap = devm_kzalloc(&pdev->dev,
> +					BITS_TO_LONGS(gicp->spi_cnt),
> +					GFP_KERNEL);
> +	if (!gicp->spi_bitmap)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, gicp);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mvebu_gicp_of_match[] = {
> +	{ .compatible = "marvell,ap806-gicp", },
> +	{},
> +};
> +
> +static struct platform_driver mvebu_gicp_driver = {
> +	.probe  = mvebu_gicp_probe,
> +	.driver = {
> +		.name = "mvebu-gicp",
> +		.of_match_table = mvebu_gicp_of_match,
> +	},
> +};
> +builtin_platform_driver(mvebu_gicp_driver);
> diff --git a/drivers/irqchip/irq-mvebu-gicp.h b/drivers/irqchip/irq-mvebu-gicp.h
> new file mode 100644
> index 0000000..7290166
> --- /dev/null
> +++ b/drivers/irqchip/irq-mvebu-gicp.h
> @@ -0,0 +1,15 @@
> +#ifndef __MVEBU_GICP_H__
> +#define __MVEBU_GICP_H__
> +
> +struct mvebu_gicp;
> +
> +int mvebu_gicp_alloc(struct mvebu_gicp *gicp);
> +void mvebu_gicp_free(struct mvebu_gicp *gicp, int idx);
> +int mvebu_gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx);
> +int mvebu_gicp_spi_to_idx(struct mvebu_gicp *gicp, int spi);
> +phys_addr_t mvebu_gicp_setspi_phys_addr(struct mvebu_gicp *gicp);
> +phys_addr_t mvebu_gicp_clrspi_phys_addr(struct mvebu_gicp *gicp);
> +int mvebu_gicp_spi_count(struct mvebu_gicp *gicp);
> +
> +#endif /* __MVEBU_GICP_H__ */
> +
> 

The more I look at this code, the more I think this should actually be
an IRQ domain of its own. It already has an allocator, and I believe a
number of these exported functions disappear by virtue of having linked
data structures.

Also, given that this GICP is a perfect clone of the equivalent GICv3
feature, we could use it the same way should someone glue an ICU on a
GICv3 system...

I appreciate that I did say the exact opposite on IRC, but hey, I admit
I was wrong! ;-)

What do you think?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

[Rob Herring]

On Thu, Jun 08, 2017 at 02:10:23PM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote:
> > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> > > This commit adds the Device Tree binding documentation for the Marvell
> > > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> > > using memory transactions. It is used by the ICU unit in the Marvell
> > > CP110 block to turn wired interrupts inside the CP into SPI interrupts
> > > at the GIC level in the AP.  
> > 
> > Sounds like an MSI block?
> 
> Marc Zyngier answered on this (much better than I could have done).
> 
> > > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> > > +  for this GICP  
> > 
> > These are base+size?
> 
> Correct. Does your question suggest that I should update the binding
> document to make this explicit?

Yes, please.

Rob

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU

[Rob Herring]

On Thu, Jun 08, 2017 at 02:12:02PM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> On Wed, 7 Jun 2017 17:33:17 -0500, Rob Herring wrote:
> 
> > > +Example:
> > > +
> > > +icu: interrupt-controller@1e0000 {
> > > +	compatible = "marvell,cp110-icu";
> > > +	reg = <0x1e0000 0x10>;
> > > +	#interrupt-cells = <3>;
> > > +	interrupt-controller;
> > > +	interrupt-parent = <&gic>;  
> > 
> > If you have a parent, then you should have some interrupts. I guess that 
> > would be your ranges property? I suppose that is fine.
> 
> The ranges of interrupts available is defined by the gicp node. Indeed,
> as explained in the cover letter:
> 
>  - We have one GICP in the SoC, providing a number of GIC SPI interrupts
> 
>  - We have one ICU per CP in the SoC. So for example in the Armada 8K,
>    we have two CPs, and therefore two ICUs.
> 
> So the range of available GIC SPI interrupts it not associated to each
> ICU, it's a global range of GIC SPI interrupts: each can freely be
> allocated by any of the ICUs in the system.

Okay, I guess I have no issues with this one.

Acked-by: Rob Herring <robh@kernel.org>