* [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10
@ 2017-06-08 14:18 Dinh Nguyen
2017-06-20 0:03 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: Dinh Nguyen @ 2017-06-08 14:18 UTC (permalink / raw)
To: linux-clk; +Cc: dinguyen, sboyd, mturquette, linux-kernel
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: Add a Fixes tag
---
drivers/clk/socfpga/clk-gate-a10.c | 2 +-
drivers/clk/socfpga/clk.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index c2d5727..36376c5 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -86,7 +86,7 @@ static int socfpga_clk_prepare(struct clk_hw *hwclk)
}
}
- hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+ hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
regmap_write(socfpgaclk->sys_mgr_base_addr,
SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index 814c724..9cf1230 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -32,6 +32,9 @@
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
+ ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
+
extern void __iomem *clk_mgr_base_addr;
extern void __iomem *clk_mgr_a10_base_addr;
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10
2017-06-08 14:18 [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10 Dinh Nguyen
@ 2017-06-20 0:03 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2017-06-20 0:03 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: linux-clk, mturquette, linux-kernel
On 06/08, Dinh Nguyen wrote:
> The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
> offset by 1 additional bit.
>
> Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
> Stratix10 platforms.
>
> Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-06-20 0:03 ` Stephen Boyd
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