From: Ludovic Barre <ludovic.Barre@st.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl
Date: Fri, 7 Jul 2017 09:26:31 +0200 [thread overview]
Message-ID: <1499412391-25480-9-git-send-email-ludovic.Barre@st.com> (raw)
In-Reply-To: <1499412391-25480-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index fcc1e06..8854d26 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
@@ -57,6 +59,8 @@
reg = <0x0 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
reg = <0x400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
reg = <0x800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
usart1_pins: usart1@0 {
--
2.7.4
next prev parent reply other threads:[~2017-07-07 7:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-07 7:26 [PATCH 0/8] irqchip: stm32: add stm32h7 support Ludovic Barre
2017-07-07 7:26 ` [PATCH 1/8] irqchip: stm32: select GENERIC_IRQ_CHIP Ludovic Barre
2017-07-07 7:26 ` [PATCH 2/8] irqchip: stm32: add multi-bank management Ludovic Barre
2017-08-07 13:21 ` Marc Zyngier
2017-08-08 9:28 ` Ludovic BARRE
2017-07-07 7:26 ` [PATCH 3/8] dt-bindings: interrupt-controllers: add compatible string for stm32h7 Ludovic Barre
2017-07-07 7:26 ` [PATCH 4/8] irqchip: stm32: add stm32h7 support Ludovic Barre
2017-07-07 7:26 ` [PATCH 5/8] irqchip: stm32: fix initial values Ludovic Barre
2017-07-07 7:26 ` [PATCH 6/8] irqchip: stm32: move the wakeup on interrupt mask Ludovic Barre
2017-07-07 7:26 ` [PATCH 7/8] ARM: dts: stm32: add exti support for stm32h743 Ludovic Barre
2017-07-07 7:26 ` Ludovic Barre [this message]
2017-07-07 8:16 ` [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl Alexandre Torgue
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