[PATCH v3 00/16] coresight: Support for ARM Coresight SoC-600

[PATCH v3 00/16] coresight: Support for ARM Coresight SoC-600

[Suzuki K Poulose]

This series adds support for ARM Coresight SoC-600 IP, which implements
Coresight V3 architecture. It also does some clean up of the replicator
driver namings used in the driver to prevent confusions to the user.

The SoC-600 comes with an improved TMC which supports new features,
including Save-Restore and Software FIFO2 mode (for streaming the trace
data over functional I/O like USB/PCI).

This series only supports Save-Restore feature of the new ETR by reusing
the driver to perform additional setups required in case we are dealing
with an IP which supports it. Towards this we keep track of the capabilities
of the given TMC ETR. Some of the features are advertised via DEVID
register (address width, scatter gather support), while some are not
(save-restore). So we attach a static capability mask with the device
PID for the unadvertised features and detect the rest at device probe.

Tested on Juno (with Coresight SoC 400) and an FPGA based system
for SoC 600. Applies on Mathieu's coresight/next.

Changes since V2:
 - Fix typos in masks for ETM3.
 - Fix all dts for obsoleted compatible string for replicator.
 - Detect advertised capabilities at runtime.
 - Add support for detecting the address width at runtime, new
   feature in SoC-600.
 - Add support for split ARCACHE/WCACHE encoding for AXI transactions

Changes since V1
 - Rename coresight-replicator-qcom.c => coresight-dynamic-replicator.c
 - Fix PIDR2 codings for ETB-10, ETM3x
 - Fix cosmetic issues pointed out by  Mathieu
 - Fix commit description for
	 "coresight tmc: Handle configuration types properly"
 - Drop SWFIFO2 from the capability of SoC-600 TMC


Suzuki K Poulose (18):
  coresight replicator: Cleanup programmable replicator naming
  arm64: juno: dts:  Use the new coresight replicator string
  arm: qcom-msm8974: dts: Update coresight replicator
  arm64: qcom-msm8916: dts: Update coresight replicator
  coresight: Extend the PIDR mask to cover relevant bits in PIDR2
  coresight: Add support for reading 64bit registers
  coresight tmc: Add helpers for accessing 64bit registers
  coresight tmc: Expose DBA and AXICTL
  coresight replicator: Expose replicator management registers
  coresight tmc: Handle configuration types properly
  coresight tmc etr: Add capabilitiy information
  coresight tmc: Detect support for scatter gather
  coresight tmc etr: Detect address width at runtime
  coresight tmc etr: Cleanup AXICTL register handling
  coresigh tmc etr: Setup AXI cache encoding for read transfers
  coresight tmc: Support for save-restore in ETR
  coresight tmc: Add support for Coresight SoC 600 TMC
  coresight: Add support for Coresight SoC 600 components

 .../devicetree/bindings/arm/coresight.txt          |   4 +-
 arch/arm/boot/dts/qcom-msm8974.dtsi                |   2 +-
 arch/arm64/boot/dts/arm/juno-base.dtsi             |   2 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi              |   2 +-
 drivers/hwtracing/coresight/Kconfig                |  10 +-
 drivers/hwtracing/coresight/Makefile               |   2 +-
 .../coresight/coresight-dynamic-replicator.c       | 221 +++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etb10.c      |   4 +-
 drivers/hwtracing/coresight/coresight-etm3x.c      |  24 +--
 drivers/hwtracing/coresight/coresight-funnel.c     |   9 +-
 drivers/hwtracing/coresight/coresight-priv.h       |  35 +++-
 .../coresight/coresight-replicator-qcom.c          | 196 ------------------
 drivers/hwtracing/coresight/coresight-stm.c        |   8 +-
 drivers/hwtracing/coresight/coresight-tmc-etf.c    |   8 +-
 drivers/hwtracing/coresight/coresight-tmc-etr.c    |  37 ++--
 drivers/hwtracing/coresight/coresight-tmc.c        |  84 ++++++--
 drivers/hwtracing/coresight/coresight-tmc.h        |  87 +++++++-
 drivers/hwtracing/coresight/coresight-tpiu.c       |   9 +-
 18 files changed, 481 insertions(+), 263 deletions(-)
 create mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c
 delete mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c

-- 
2.7.5

[PATCH v3 01/18] coresight replicator: Cleanup programmable replicator naming

[Suzuki K Poulose]

The Linux coresight drivers define the programmable ATB replicator as
Qualcomm replicator, while this is designed by ARM. This can cause confusion
to a user selecting the driver. Cleanup all references to make it
 explicitly clear. This patch :

 1) Replace the compatible string for the replicator :
	qcom,coresight-replicator1x => arm,coresight-dynamic-replicator
 2) Changes the Kconfig symbol (since this is not part of any defconfigs)
	 CORESIGHT_QCOM_REPLICATOR => CORESIGHT_DYNAMIC_REPLICATOR
 3) Improves the help message in the Kconfig.
 4) Changes the name of the driver and the file :
	coresight-replicator-qcom => coresight-dynamic-replicator

Cc: Pratik Patel <pratikp@codeaurora.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since V1:
 - Since the driver doesn't use the compatible string, change the
   recommended compatible string.
 - Rename the driver file to coresight-dynamic-replicator.c
---
 .../devicetree/bindings/arm/coresight.txt          |   4 +-
 drivers/hwtracing/coresight/Kconfig                |  10 +-
 drivers/hwtracing/coresight/Makefile               |   2 +-
 .../coresight/coresight-dynamic-replicator.c       | 195 ++++++++++++++++++++
 .../coresight/coresight-replicator-qcom.c          | 196 ---------------------
 5 files changed, 203 insertions(+), 204 deletions(-)
 create mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c
 delete mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index fcbae6a..15ac8e8 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -34,8 +34,8 @@ its hardware characteristcs.
 		- Embedded Trace Macrocell (version 4.x):
 			"arm,coresight-etm4x", "arm,primecell";
 
-		- Qualcomm Configurable Replicator (version 1.x):
-			"qcom,coresight-replicator1x", "arm,primecell";
+		- Coresight programmable Replicator :
+			"arm,coresight-dynamic-replicator", "arm,primecell";
 
 		- System Trace Macrocell:
 			"arm,coresight-stm", "arm,primecell"; [1]
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 8d55d6d..ef9cb3c 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -70,13 +70,13 @@ config CORESIGHT_SOURCE_ETM4X
 	  for instruction level tracing. Depending on the implemented version
 	  data tracing may also be available.
 
-config CORESIGHT_QCOM_REPLICATOR
-	bool "Qualcomm CoreSight Replicator driver"
+config CORESIGHT_DYNAMIC_REPLICATOR
+	bool "CoreSight Programmable Replicator driver"
 	depends on CORESIGHT_LINKS_AND_SINKS
 	help
-	  This enables support for Qualcomm CoreSight link driver. The
-	  programmable ATB replicator sends the ATB trace stream from the
-	  ETB/ETF to the TPIUi and ETR.
+	  This enables support for dynamic CoreSight replicator link driver.
+	  The programmable ATB replicator allows independent filtering of the
+	  trace data based on the traceid.
 
 config CORESIGHT_STM
 	bool "CoreSight System Trace Macrocell driver"
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 433d590..5bae90ce 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -14,6 +14,6 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
 					coresight-etm3x-sysfs.o
 obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
 					coresight-etm4x-sysfs.o
-obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
+obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o
 obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
 obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
new file mode 100644
index 0000000..1675031
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/clk.h>
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#include "coresight-priv.h"
+
+#define REPLICATOR_IDFILTER0		0x000
+#define REPLICATOR_IDFILTER1		0x004
+
+/**
+ * struct replicator_state - specifics associated to a replicator component
+ * @base:	memory mapped base address for this component.
+ * @dev:	the device entity associated with this component
+ * @atclk:	optional clock for the core parts of the replicator.
+ * @csdev:	component vitals needed by the framework
+ */
+struct replicator_state {
+	void __iomem		*base;
+	struct device		*dev;
+	struct clk		*atclk;
+	struct coresight_device	*csdev;
+};
+
+static int replicator_enable(struct coresight_device *csdev, int inport,
+			      int outport)
+{
+	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+	CS_UNLOCK(drvdata->base);
+
+	/*
+	 * Ensure that the other port is disabled
+	 * 0x00 - passing through the replicator unimpeded
+	 * 0xff - disable (or impede) the flow of ATB data
+	 */
+	if (outport == 0) {
+		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
+		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+	} else {
+		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
+		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+	}
+
+	CS_LOCK(drvdata->base);
+
+	dev_info(drvdata->dev, "REPLICATOR enabled\n");
+	return 0;
+}
+
+static void replicator_disable(struct coresight_device *csdev, int inport,
+				int outport)
+{
+	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+	CS_UNLOCK(drvdata->base);
+
+	/* disable the flow of ATB data through port */
+	if (outport == 0)
+		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
+	else
+		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
+
+	CS_LOCK(drvdata->base);
+
+	dev_info(drvdata->dev, "REPLICATOR disabled\n");
+}
+
+static const struct coresight_ops_link replicator_link_ops = {
+	.enable		= replicator_enable,
+	.disable	= replicator_disable,
+};
+
+static const struct coresight_ops replicator_cs_ops = {
+	.link_ops	= &replicator_link_ops,
+};
+
+static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
+{
+	int ret;
+	struct device *dev = &adev->dev;
+	struct resource *res = &adev->res;
+	struct coresight_platform_data *pdata = NULL;
+	struct replicator_state *drvdata;
+	struct coresight_desc desc = { 0 };
+	struct device_node *np = adev->dev.of_node;
+	void __iomem *base;
+
+	if (np) {
+		pdata = of_get_coresight_platform_data(dev, np);
+		if (IS_ERR(pdata))
+			return PTR_ERR(pdata);
+		adev->dev.platform_data = pdata;
+	}
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+
+	drvdata->dev = &adev->dev;
+	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
+	if (!IS_ERR(drvdata->atclk)) {
+		ret = clk_prepare_enable(drvdata->atclk);
+		if (ret)
+			return ret;
+	}
+
+	/* Validity for the resource is already checked by the AMBA core */
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	drvdata->base = base;
+	dev_set_drvdata(dev, drvdata);
+	pm_runtime_put(&adev->dev);
+
+	desc.type = CORESIGHT_DEV_TYPE_LINK;
+	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
+	desc.ops = &replicator_cs_ops;
+	desc.pdata = adev->dev.platform_data;
+	desc.dev = &adev->dev;
+	drvdata->csdev = coresight_register(&desc);
+	if (IS_ERR(drvdata->csdev))
+		return PTR_ERR(drvdata->csdev);
+
+	dev_info(dev, "initialized\n");
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int replicator_runtime_suspend(struct device *dev)
+{
+	struct replicator_state *drvdata = dev_get_drvdata(dev);
+
+	if (drvdata && !IS_ERR(drvdata->atclk))
+		clk_disable_unprepare(drvdata->atclk);
+
+	return 0;
+}
+
+static int replicator_runtime_resume(struct device *dev)
+{
+	struct replicator_state *drvdata = dev_get_drvdata(dev);
+
+	if (drvdata && !IS_ERR(drvdata->atclk))
+		clk_prepare_enable(drvdata->atclk);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops replicator_dev_pm_ops = {
+	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
+			   replicator_runtime_resume,
+			   NULL)
+};
+
+static struct amba_id replicator_ids[] = {
+	{
+		.id     = 0x0003b909,
+		.mask   = 0x0003ffff,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver replicator_driver = {
+	.drv = {
+		.name	= "coresight-dynamic-replicator",
+		.pm	= &replicator_dev_pm_ops,
+		.suppress_bind_attrs = true,
+	},
+	.probe		= replicator_probe,
+	.id_table	= replicator_ids,
+};
+builtin_amba_driver(replicator_driver);
diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
deleted file mode 100644
index 0a3d15f..0000000
--- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/amba/bus.h>
-#include <linux/clk.h>
-#include <linux/coresight.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/pm_runtime.h>
-#include <linux/slab.h>
-
-#include "coresight-priv.h"
-
-#define REPLICATOR_IDFILTER0		0x000
-#define REPLICATOR_IDFILTER1		0x004
-
-/**
- * struct replicator_state - specifics associated to a replicator component
- * @base:	memory mapped base address for this component.
- * @dev:	the device entity associated with this component
- * @atclk:	optional clock for the core parts of the replicator.
- * @csdev:	component vitals needed by the framework
- */
-struct replicator_state {
-	void __iomem		*base;
-	struct device		*dev;
-	struct clk		*atclk;
-	struct coresight_device	*csdev;
-};
-
-static int replicator_enable(struct coresight_device *csdev, int inport,
-			      int outport)
-{
-	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
-
-	CS_UNLOCK(drvdata->base);
-
-	/*
-	 * Ensure that the other port is disabled
-	 * 0x00 - passing through the replicator unimpeded
-	 * 0xff - disable (or impede) the flow of ATB data
-	 */
-	if (outport == 0) {
-		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
-		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
-	} else {
-		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
-		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
-	}
-
-	CS_LOCK(drvdata->base);
-
-	dev_info(drvdata->dev, "REPLICATOR enabled\n");
-	return 0;
-}
-
-static void replicator_disable(struct coresight_device *csdev, int inport,
-				int outport)
-{
-	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
-
-	CS_UNLOCK(drvdata->base);
-
-	/* disable the flow of ATB data through port */
-	if (outport == 0)
-		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
-	else
-		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
-
-	CS_LOCK(drvdata->base);
-
-	dev_info(drvdata->dev, "REPLICATOR disabled\n");
-}
-
-static const struct coresight_ops_link replicator_link_ops = {
-	.enable		= replicator_enable,
-	.disable	= replicator_disable,
-};
-
-static const struct coresight_ops replicator_cs_ops = {
-	.link_ops	= &replicator_link_ops,
-};
-
-static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
-{
-	int ret;
-	struct device *dev = &adev->dev;
-	struct resource *res = &adev->res;
-	struct coresight_platform_data *pdata = NULL;
-	struct replicator_state *drvdata;
-	struct coresight_desc desc = { 0 };
-	struct device_node *np = adev->dev.of_node;
-	void __iomem *base;
-
-	if (np) {
-		pdata = of_get_coresight_platform_data(dev, np);
-		if (IS_ERR(pdata))
-			return PTR_ERR(pdata);
-		adev->dev.platform_data = pdata;
-	}
-
-	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-	if (!drvdata)
-		return -ENOMEM;
-
-	drvdata->dev = &adev->dev;
-	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
-	if (!IS_ERR(drvdata->atclk)) {
-		ret = clk_prepare_enable(drvdata->atclk);
-		if (ret)
-			return ret;
-	}
-
-	/* Validity for the resource is already checked by the AMBA core */
-	base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
-
-	drvdata->base = base;
-	dev_set_drvdata(dev, drvdata);
-	pm_runtime_put(&adev->dev);
-
-	desc.type = CORESIGHT_DEV_TYPE_LINK;
-	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
-	desc.ops = &replicator_cs_ops;
-	desc.pdata = adev->dev.platform_data;
-	desc.dev = &adev->dev;
-	drvdata->csdev = coresight_register(&desc);
-	if (IS_ERR(drvdata->csdev))
-		return PTR_ERR(drvdata->csdev);
-
-	dev_info(dev, "%s initialized\n", (char *)id->data);
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static int replicator_runtime_suspend(struct device *dev)
-{
-	struct replicator_state *drvdata = dev_get_drvdata(dev);
-
-	if (drvdata && !IS_ERR(drvdata->atclk))
-		clk_disable_unprepare(drvdata->atclk);
-
-	return 0;
-}
-
-static int replicator_runtime_resume(struct device *dev)
-{
-	struct replicator_state *drvdata = dev_get_drvdata(dev);
-
-	if (drvdata && !IS_ERR(drvdata->atclk))
-		clk_prepare_enable(drvdata->atclk);
-
-	return 0;
-}
-#endif
-
-static const struct dev_pm_ops replicator_dev_pm_ops = {
-	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
-			   replicator_runtime_resume,
-			   NULL)
-};
-
-static struct amba_id replicator_ids[] = {
-	{
-		.id     = 0x0003b909,
-		.mask   = 0x0003ffff,
-		.data	= "REPLICATOR 1.0",
-	},
-	{ 0, 0 },
-};
-
-static struct amba_driver replicator_driver = {
-	.drv = {
-		.name	= "coresight-replicator-qcom",
-		.pm	= &replicator_dev_pm_ops,
-		.suppress_bind_attrs = true,
-	},
-	.probe		= replicator_probe,
-	.id_table	= replicator_ids,
-};
-builtin_amba_driver(replicator_driver);
-- 
2.7.5

[PATCH v3 02/18] arm64: juno: dts: Use the new coresight replicator string

[Suzuki K Poulose]

Use the new compatible for ATB programmable replicator in Juno.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index bfe7d68..c82c706 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -373,7 +373,7 @@
 	};
 
 	replicator@20120000 {
-		compatible = "qcom,coresight-replicator1x", "arm,primecell";
+		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 		reg = <0 0x20120000 0 0x1000>;
 
 		clocks = <&soc_smc50mhz>;
-- 
2.7.5

[PATCH v3 03/18] arm: qcom-msm8974: dts: Update coresight replicator

[Suzuki K Poulose]

Replace the obsolete compatible string for Coresight programmable
replicator with the new one.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 307bf6a..3c7c6b9 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -729,7 +729,7 @@
 		};
 
 		replicator@fc31c000 {
-			compatible = "qcom,coresight-replicator1x", "arm,primecell";
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 			reg = <0xfc31c000 0x1000>;
 
 			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
-- 
2.7.5

[PATCH v3 04/18] arm64: qcom-msm8916: dts: Update coresight replicator

[Suzuki K Poulose]

Replace the obsolete compatible string for Coresight programmable
replicator with the new one.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 17691ab..a0db8c6 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -994,7 +994,7 @@
 		};
 
 		replicator@824000 {
-			compatible = "qcom,coresight-replicator1x", "arm,primecell";
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 			reg = <0x824000 0x1000>;
 
 			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
-- 
2.7.5

[PATCH v3 05/18] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

[Suzuki K Poulose]

As per coresight standards, PIDR2 register has the following format :

 [2-0]	- JEP106_bits6to4
 [3]	- JEDEC, designer ID is specified by JEDEC.

However some of the drivers only use mask of 0x3 for the PIDR2 leaving
bits [3-2] unchecked, which could potentially match the component for
a different device altogether. This patch fixes the mask and the
corresponding id bits for the existing devices.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
I have not touched the TPIU ids for Ux500 (see commit: 4339b699),
as I don't have a platform to fix/correct the ids.
---
 .../coresight/coresight-dynamic-replicator.c       |  4 ++--
 drivers/hwtracing/coresight/coresight-etb10.c      |  4 ++--
 drivers/hwtracing/coresight/coresight-etm3x.c      | 24 +++++++++++-----------
 drivers/hwtracing/coresight/coresight-funnel.c     |  4 ++--
 drivers/hwtracing/coresight/coresight-stm.c        |  8 ++++----
 drivers/hwtracing/coresight/coresight-tmc.c        |  4 ++--
 drivers/hwtracing/coresight/coresight-tpiu.c       |  4 ++--
 7 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index 1675031..ccbafaf 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -177,8 +177,8 @@ static const struct dev_pm_ops replicator_dev_pm_ops = {
 
 static struct amba_id replicator_ids[] = {
 	{
-		.id     = 0x0003b909,
-		.mask   = 0x0003ffff,
+		.id     = 0x000bb909,
+		.mask   = 0x000fffff,
 	},
 	{ 0, 0 },
 };
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index d5b9642..be6f59c 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -730,8 +730,8 @@ static const struct dev_pm_ops etb_dev_pm_ops = {
 
 static struct amba_id etb_ids[] = {
 	{
-		.id	= 0x0003b907,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb907,
+		.mask	= 0x000fffff,
 	},
 	{ 0, 0},
 };
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index a51b6b6..1af7f9e 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -887,33 +887,33 @@ static const struct dev_pm_ops etm_dev_pm_ops = {
 
 static struct amba_id etm_ids[] = {
 	{	/* ETM 3.3 */
-		.id	= 0x0003b921,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb921,
+		.mask	= 0x000fffff,
 		.data	= "ETM 3.3",
 	},
 	{	/* ETM 3.5 - Cortex-A5 */
-		.id	= 0x0003b955,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb955,
+		.mask	= 0x000fffff,
 		.data	= "ETM 3.5",
 	},
 	{	/* ETM 3.5 */
-		.id	= 0x0003b956,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb956,
+		.mask	= 0x000fffff,
 		.data	= "ETM 3.5",
 	},
 	{	/* PTM 1.0 */
-		.id	= 0x0003b950,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb950,
+		.mask	= 0x000fffff,
 		.data	= "PTM 1.0",
 	},
 	{	/* PTM 1.1 */
-		.id	= 0x0003b95f,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb95f,
+		.mask	= 0x000fffff,
 		.data	= "PTM 1.1",
 	},
 	{	/* PTM 1.1 Qualcomm */
-		.id	= 0x0003006f,
-		.mask	= 0x0003ffff,
+		.id	= 0x000b006f,
+		.mask	= 0x000fffff,
 		.data	= "PTM 1.1",
 	},
 	{ 0, 0},
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 860fe6e..6f7f3d3 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -248,8 +248,8 @@ static const struct dev_pm_ops funnel_dev_pm_ops = {
 
 static struct amba_id funnel_ids[] = {
 	{
-		.id     = 0x0003b908,
-		.mask   = 0x0003ffff,
+		.id     = 0x000bb908,
+		.mask   = 0x000fffff,
 	},
 	{ 0, 0},
 };
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index 93fc26f..1bcda80 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -916,13 +916,13 @@ static const struct dev_pm_ops stm_dev_pm_ops = {
 
 static struct amba_id stm_ids[] = {
 	{
-		.id     = 0x0003b962,
-		.mask   = 0x0003ffff,
+		.id     = 0x000bb962,
+		.mask   = 0x000fffff,
 		.data	= "STM32",
 	},
 	{
-		.id	= 0x0003b963,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb963,
+		.mask	= 0x000fffff,
 		.data	= "STM500",
 	},
 	{ 0, 0},
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 8644887..eb0c7b3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -393,8 +393,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 
 static struct amba_id tmc_ids[] = {
 	{
-		.id     = 0x0003b961,
-		.mask   = 0x0003ffff,
+		.id     = 0x000bb961,
+		.mask   = 0x000fffff,
 	},
 	{ 0, 0},
 };
diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index 0673baf..59c1510 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -194,8 +194,8 @@ static const struct dev_pm_ops tpiu_dev_pm_ops = {
 
 static struct amba_id tpiu_ids[] = {
 	{
-		.id	= 0x0003b912,
-		.mask	= 0x0003ffff,
+		.id	= 0x000bb912,
+		.mask	= 0x000fffff,
 	},
 	{
 		.id	= 0x0004b912,
-- 
2.7.5

[PATCH v3 06/18] coresight: Add support for reading 64bit registers

[Suzuki K Poulose]

Add support for reading a lower and upper 32bits of a register
as a single 64bit register.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-priv.h | 27 ++++++++++++++++++++++-----
 drivers/hwtracing/coresight/coresight-tmc.c  |  4 ++--
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 5f662d8..1080a67 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -39,23 +39,29 @@
 #define ETM_MODE_EXCL_USER	BIT(31)
 
 typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
-#define coresight_simple_func(type, func, name, offset)			\
+#define __coresight_simple_func(type, func, name, lo_off, hi_off)	\
 static ssize_t name##_show(struct device *_dev,				\
 			   struct device_attribute *attr, char *buf)	\
 {									\
 	type *drvdata = dev_get_drvdata(_dev->parent);			\
 	coresight_read_fn fn = func;					\
-	u32 val;							\
+	u64 val;							\
 	pm_runtime_get_sync(_dev->parent);				\
 	if (fn)								\
-		val = fn(_dev->parent, offset);				\
+		val = (u64)fn(_dev->parent, lo_off);			\
 	else								\
-		val = readl_relaxed(drvdata->base + offset);		\
+		val = coresight_read_reg_pair(drvdata->base,		\
+						 lo_off, hi_off);	\
 	pm_runtime_put_sync(_dev->parent);				\
-	return scnprintf(buf, PAGE_SIZE, "0x%x\n", val);		\
+	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val);		\
 }									\
 static DEVICE_ATTR_RO(name)
 
+#define coresight_simple_func(type, func, name, offset)			\
+	__coresight_simple_func(type, func, name, offset, -1)
+#define coresight_simple_reg64(type, name, lo_off, hi_off)		\
+	__coresight_simple_func(type, NULL, name, lo_off, hi_off)
+
 enum etm_addr_type {
 	ETM_ADDR_TYPE_NONE,
 	ETM_ADDR_TYPE_SINGLE,
@@ -106,6 +112,17 @@ static inline void CS_UNLOCK(void __iomem *addr)
 	} while (0);
 }
 
+static inline u64
+coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
+{
+	u64 val;
+
+	val = readl_relaxed(addr + lo_offset);
+	val |= (hi_offset < 0) ? 0 :
+	       (u64)readl_relaxed(addr + hi_offset) << 32;
+	return val;
+}
+
 void coresight_disable_path(struct list_head *path);
 int coresight_enable_path(struct list_head *path, u32 mode);
 struct coresight_device *coresight_get_sink(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index eb0c7b3..ccdc2d3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -222,8 +222,6 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
 
 coresight_tmc_simple_func(rsz, TMC_RSZ);
 coresight_tmc_simple_func(sts, TMC_STS);
-coresight_tmc_simple_func(rrp, TMC_RRP);
-coresight_tmc_simple_func(rwp, TMC_RWP);
 coresight_tmc_simple_func(trg, TMC_TRG);
 coresight_tmc_simple_func(ctl, TMC_CTL);
 coresight_tmc_simple_func(ffsr, TMC_FFSR);
@@ -231,6 +229,8 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
 coresight_tmc_simple_func(mode, TMC_MODE);
 coresight_tmc_simple_func(pscr, TMC_PSCR);
 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
+coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
+coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
 
 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_rsz.attr,
-- 
2.7.5

[PATCH v3 07/18] coresight tmc: Add helpers for accessing 64bit registers

[Suzuki K Poulose]

Coresight TMC splits 64bit registers into a pair of 32bit registers
(e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-priv.h    |  8 ++++++++
 drivers/hwtracing/coresight/coresight-tmc-etf.c |  8 ++++----
 drivers/hwtracing/coresight/coresight-tmc-etr.c |  8 ++++----
 drivers/hwtracing/coresight/coresight-tmc.h     | 19 +++++++++++++++++++
 4 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 1080a67..93333f9 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -123,6 +123,14 @@ coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
 	return val;
 }
 
+static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
+						 s32 lo_offset, s32 hi_offset)
+{
+	writel_relaxed((u32)val, addr + lo_offset);
+	if (hi_offset >= 0)
+		writel_relaxed((u32)(val >> 32), addr + hi_offset);
+}
+
 void coresight_disable_path(struct list_head *path);
 int coresight_enable_path(struct list_head *path, u32 mode);
 struct coresight_device *coresight_get_sink(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e3b9fb8..aecd712 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -371,7 +371,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 {
 	int i, cur;
 	u32 *buf_ptr;
-	u32 read_ptr, write_ptr;
+	u64 read_ptr, write_ptr;
 	u32 status, to_read;
 	unsigned long offset;
 	struct cs_buffers *buf = sink_config;
@@ -388,8 +388,8 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 
 	tmc_flush_and_stop(drvdata);
 
-	read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
-	write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
+	read_ptr = tmc_read_rrp(drvdata);
+	write_ptr = tmc_read_rwp(drvdata);
 
 	/*
 	 * Get a hold of the status register and see if a wrap around
@@ -441,7 +441,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 		if (read_ptr > (drvdata->size - 1))
 			read_ptr -= drvdata->size;
 		/* Tell the HW */
-		writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
+		tmc_write_rrp(drvdata, read_ptr);
 		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
 	}
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 5d31269..ff11b92 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -44,9 +44,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
 		  TMC_AXICTL_PROT_CTL_B1;
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+	tmc_write_dba(drvdata, drvdata->paddr);
 
-	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
-	writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
 	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 		       TMC_FFCR_TRIGON_TRIGIN,
@@ -59,9 +58,10 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 
 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
 {
-	u32 rwp, val;
+	u64 rwp;
+	u32 val;
 
-	rwp = readl_relaxed(drvdata->base + TMC_RWP);
+	rwp = tmc_read_rwp(drvdata);
 	val = readl_relaxed(drvdata->base + TMC_STS);
 
 	/*
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 51c0185..c78de00 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -18,6 +18,7 @@
 #ifndef _CORESIGHT_TMC_H
 #define _CORESIGHT_TMC_H
 
+#include <linux/io.h>
 #include <linux/miscdevice.h>
 
 #define TMC_RSZ			0x004
@@ -139,4 +140,22 @@ extern const struct coresight_ops tmc_etf_cs_ops;
 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
 extern const struct coresight_ops tmc_etr_cs_ops;
+
+
+#define TMC_REG_PAIR(name, lo_off, hi_off)				\
+static inline u64							\
+tmc_read_##name(struct tmc_drvdata *drvdata)				\
+{									\
+	return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);	\
+}									\
+static inline void							\
+tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)			\
+{									\
+	coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);	\
+}
+
+TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
+TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
+TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
+
 #endif
-- 
2.7.5

[PATCH v3 08/18] coresight tmc: Expose DBA and AXICTL

[Suzuki K Poulose]

Expose DBALO,DBAHI and AXICTL registers

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index ccdc2d3..6bf4170 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -229,8 +229,10 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
 coresight_tmc_simple_func(mode, TMC_MODE);
 coresight_tmc_simple_func(pscr, TMC_PSCR);
 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
+coresight_tmc_simple_func(axictl, TMC_AXICTL);
 coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
 coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
+coresight_simple_reg64(struct tmc_drvdata, dba, TMC_DBALO, TMC_DBAHI);
 
 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_rsz.attr,
@@ -244,6 +246,8 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_mode.attr,
 	&dev_attr_pscr.attr,
 	&dev_attr_devid.attr,
+	&dev_attr_dba.attr,
+	&dev_attr_axictl.attr,
 	NULL,
 };
 
-- 
2.7.5

[PATCH v3 09/18] coresight replicator: Expose replicator management registers

[Suzuki K Poulose]

Expose the idfilter* registers of the programmable replicator.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 .../coresight/coresight-dynamic-replicator.c        | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index ccbafaf..4df4726 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -95,6 +95,26 @@ static const struct coresight_ops replicator_cs_ops = {
 	.link_ops	= &replicator_link_ops,
 };
 
+coresight_simple_func(struct replicator_state, NULL, idfilter0,
+				 REPLICATOR_IDFILTER0);
+coresight_simple_func(struct replicator_state, NULL, idfilter1,
+				REPLICATOR_IDFILTER1);
+static struct attribute *replicator_mgmt_attrs[] = {
+	&dev_attr_idfilter0.attr,
+	&dev_attr_idfilter1.attr,
+	NULL,
+};
+
+static const struct attribute_group replicator_mgmt_group = {
+	.attrs = replicator_mgmt_attrs,
+	.name = "mgmt",
+};
+
+static const struct attribute_group *replicator_groups[] = {
+	&replicator_mgmt_group,
+	NULL,
+};
+
 static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret;
@@ -139,6 +159,7 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
 	desc.ops = &replicator_cs_ops;
 	desc.pdata = adev->dev.platform_data;
 	desc.dev = &adev->dev;
+	desc.groups = replicator_groups;
 	drvdata->csdev = coresight_register(&desc);
 	if (IS_ERR(drvdata->csdev))
 		return PTR_ERR(drvdata->csdev);
-- 
2.7.5

[PATCH v3 10/18] coresight tmc: Handle configuration types properly

[Suzuki K Poulose]

Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. This would break
the existing driver which will treat anything other than ETR/ETB as an
ETF. Fix the driver to check the configuration type properly and also
add a warning if we encounter an unsupported configuration (ETS).

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 6bf4170..73184a1 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -358,11 +358,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 	desc.dev = dev;
 	desc.groups = coresight_tmc_groups;
 
-	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
+	switch (drvdata->config_type) {
+	case TMC_CONFIG_TYPE_ETB:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etb_cs_ops;
-	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
+		break;
+	case TMC_CONFIG_TYPE_ETR:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;
@@ -373,10 +375,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 		if (ret)
 			goto out;
-	} else {
+		break;
+	case TMC_CONFIG_TYPE_ETF:
 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 		desc.ops = &tmc_etf_cs_ops;
+		break;
+	default:
+		pr_err("%s: Unsupported TMC config\n", pdata->name);
+		ret = -EINVAL;
+		goto out;
 	}
 
 	drvdata->csdev = coresight_register(&desc);
-- 
2.7.5

[PATCH v3 11/18] coresight tmc etr: Add capabilitiy information

[Suzuki K Poulose]

With new version of TMC ETR, there are differing set of
features supported by the TMC. Add the capability of a
given TMC ETR for making safer decisions at runtime.

The device configuration register of the TMC (DEVID) lists
some of the capabilities. So, we can detect some of them at
probe. However, some of the features (or changes in behavior)
are not advertised and we have to depend on the PID to infer
the features. So we use a static description of the "unadvertised"
capabilities attached to the PID. Combining both, the static
and the dynamic capabilities, we maintain a bitmask of the
available features which can be later checked to take
appropriate actions.

Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 20 +++++++++++++++-----
 drivers/hwtracing/coresight/coresight-tmc.h | 20 ++++++++++++++++++++
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 73184a1..ebf81bc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -297,6 +297,20 @@ const struct attribute_group *coresight_tmc_groups[] = {
 	NULL,
 };
 
+/* Detect and initialise the capabilities of a TMC ETR */
+static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
+			     u32 devid, void *dev_caps)
+{
+	/* Set the unadvertised capabilities */
+	tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
+
+	/*
+	 * ETR configuration uses a 40-bit AXI master in place of
+	 * the embedded SRAM of ETB/ETF.
+	 */
+	return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(40));
+}
+
 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
@@ -368,11 +382,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;
-		/*
-		 * ETR configuration uses a 40-bit AXI master in place of
-		 * the embedded SRAM of ETB/ETF.
-		 */
-		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+		ret = tmc_etr_setup_caps(drvdata, devid, id->data);
 		if (ret)
 			goto out;
 		break;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index c78de00..b2ebcef 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -105,6 +105,8 @@ enum tmc_mem_intf_width {
  * @config_type: TMC variant, must be of type @tmc_config_type.
  * @memwidth:	width of the memory interface databus, in bytes.
  * @trigger_cntr: amount of words to store after a trigger.
+ * @etr_caps:	Bitmask of capabilities of the TMC ETR, inferred from the
+ * 		device configuration register (DEVID)
  */
 struct tmc_drvdata {
 	void __iomem		*base;
@@ -122,6 +124,7 @@ struct tmc_drvdata {
 	enum tmc_config_type	config_type;
 	enum tmc_mem_intf_width	memwidth;
 	u32			trigger_cntr;
+	u32			etr_caps;
 };
 
 /* Generic functions */
@@ -158,4 +161,21 @@ TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
 
+/* Initialise the caps from unadvertised static capabilities of the device */
+static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
+{
+	WARN_ON(drvdata->etr_caps);
+	drvdata->etr_caps = dev_caps;
+}
+
+static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
+{
+	drvdata->etr_caps |= cap;
+}
+
+static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
+{
+	return !!(drvdata->etr_caps & cap);
+}
+
 #endif
-- 
2.7.5

[PATCH v3 12/18] coresight tmc: Detect support for scatter gather

[Suzuki K Poulose]

The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
 drivers/hwtracing/coresight/coresight-tmc.h | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index ebf81bc..a1de265 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -304,6 +304,8 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
 	/* Set the unadvertised capabilities */
 	tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 
+	if (!(devid & TMC_DEVID_NOSCAT))
+		tmc_etr_set_cap(drvdata, TMC_ETR_SG);
 	/*
 	 * ETR configuration uses a 40-bit AXI master in place of
 	 * the embedded SRAM of ETB/ETF.
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index b2ebcef..bc94550 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -70,6 +70,8 @@
 #define TMC_FFCR_STOP_ON_FLUSH	BIT(12)
 
 
+#define TMC_DEVID_NOSCAT	BIT(24)
+
 enum tmc_config_type {
 	TMC_CONFIG_TYPE_ETB,
 	TMC_CONFIG_TYPE_ETR,
@@ -89,6 +91,9 @@ enum tmc_mem_intf_width {
 	TMC_MEM_INTF_WIDTH_256BITS	= 8,
 };
 
+/* TMC ETR Capability bit definitions */
+#define TMC_ETR_SG			(0x1U << 0)
+
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
  * @base:	memory mapped base address for this component.
-- 
2.7.5

[PATCH v3 13/18] coresight tmc etr: Detect address width at runtime

[Suzuki K Poulose]

TMC in Coresight SoC-600 advertises the AXI address width
in the device configuration register.

Bit 16 - AXIAW_VALID
 0 - AXI Address Width not valid
 1 - Valid AXI Address width in Bits[23-17]

Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then
 0x20 - 32bit AXI address bus
 0x28 - 40bit AXI address bus
 0x2c - 44bit AXI address bus
 0x30 - 48bit AXI address bus
 0x34 - 52bit AXI address bus

Use the address bits from the device configuration register, if
available. Otherwise, default to 40bit.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 26 +++++++++++++++++++++++---
 drivers/hwtracing/coresight/coresight-tmc.h |  4 ++++
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index a1de265..32e88ec 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -301,16 +301,36 @@ const struct attribute_group *coresight_tmc_groups[] = {
 static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
 			     u32 devid, void *dev_caps)
 {
+	u32 dma_mask = 0;
+
 	/* Set the unadvertised capabilities */
 	tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 
 	if (!(devid & TMC_DEVID_NOSCAT))
 		tmc_etr_set_cap(drvdata, TMC_ETR_SG);
+
+	/* Check if the AXI address width is available */
+	if (devid & TMC_DEVID_AXIAW_VALID)
+		dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
+				TMC_DEVID_AXIAW_MASK);
+
 	/*
-	 * ETR configuration uses a 40-bit AXI master in place of
-	 * the embedded SRAM of ETB/ETF.
+	 * Unless specified in the device configuration, ETR uses a 40-bit
+	 * AXI master in place of the embedded SRAM of ETB/ETF.
 	 */
-	return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(40));
+	switch (dma_mask) {
+	case 32:
+	case 40:
+	case 44:
+	case 48:
+	case 52:
+		dev_info(drvdata->dev, "Detected dma mask %dbits\n", dma_mask);
+		break;
+	default:
+		dma_mask = 40;
+	}
+
+	return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask));
 }
 
 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index bc94550..a0668f6 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -72,6 +72,10 @@
 
 #define TMC_DEVID_NOSCAT	BIT(24)
 
+#define TMC_DEVID_AXIAW_VALID	BIT(16)
+#define TMC_DEVID_AXIAW_SHIFT	17
+#define TMC_DEVID_AXIAW_MASK	0x7f
+
 enum tmc_config_type {
 	TMC_CONFIG_TYPE_ETB,
 	TMC_CONFIG_TYPE_ETR,
-- 
2.7.5

[PATCH v3 14/18] coresight tmc etr: Cleanup AXICTL register handling

[Suzuki K Poulose]

This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++-------
 drivers/hwtracing/coresight/coresight-tmc.h     | 17 ++++++++++++++++-
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index ff11b92..4aa5d36 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 
 	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
-	axictl |= TMC_AXICTL_WR_BURST_16;
-	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
-	axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
-	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
-	axictl = (axictl &
-		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
-		  TMC_AXICTL_PROT_CTL_B1;
+	axictl &= ~TMC_AXICTL_CLEAR_MASK;
+	axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
+	axictl |= TMC_AXICTL_AxCACHE_OS;
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 	tmc_write_dba(drvdata, drvdata->paddr);
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index a0668f6..5d6d7e5 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -55,11 +55,26 @@
 #define TMC_STS_TMCREADY_BIT	2
 #define TMC_STS_FULL		BIT(0)
 #define TMC_STS_TRIGGERED	BIT(1)
-/* TMC_AXICTL - 0x110 */
+/*
+ * TMC_AXICTL - 0x110
+ *
+ * TMC AXICTL format for SoC-400
+ * 	Bits [0-1]	: ProtCtrlBit0-1
+ * 	Bits [2-5]	: CacheCtrlBits 0-3 (AxCACHE)
+ * 	Bit  6		: Reserved
+ * 	Bit  7		: ScatterGatherMode
+ * 	Bits [8-11]	: WrBurstLen
+ * 	Bits [12-31]	: Reserved.
+ */
+#define TMC_AXICTL_CLEAR_MASK 0xfbf
+
 #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
 #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
 #define TMC_AXICTL_SCT_GAT_MODE	BIT(7)
 #define TMC_AXICTL_WR_BURST_16	0xF00
+/* Write-back Read and Write-allocate */
+#define TMC_AXICTL_AxCACHE_OS	(0xf << 2)
+
 /* TMC_FFCR - 0x304 */
 #define TMC_FFCR_FLUSHMAN_BIT	6
 #define TMC_FFCR_EN_FMT		BIT(0)
-- 
2.7.5

[PATCH v3 15/18] coresigh tmc etr: Setup AXI cache encoding for read transfers

[Suzuki K Poulose]

If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++++++
 drivers/hwtracing/coresight/coresight-tmc.h     | 9 +++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4aa5d36..d5f51cb 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -39,6 +39,12 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 	axictl &= ~TMC_AXICTL_CLEAR_MASK;
 	axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
 	axictl |= TMC_AXICTL_AxCACHE_OS;
+
+	if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) {
+		axictl &= ~TMC_AXICTL_ARCACHE_MASK;
+		axictl |= TMC_AXICTL_ARCACHE_OS;
+	}
+
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 	tmc_write_dba(drvdata, drvdata->paddr);
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 5d6d7e5..de92011 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -65,8 +65,14 @@
  * 	Bit  7		: ScatterGatherMode
  * 	Bits [8-11]	: WrBurstLen
  * 	Bits [12-31]	: Reserved.
+ *
+ * TMC AXICTL format for SoC-600, as above except:
+ * 	Bits [2-5]	: AXI WCACHE
+ * 	Bits [16-19]	: AXI RCACHE
+ * 	Bits [20-31]	: Reserved
  */
 #define TMC_AXICTL_CLEAR_MASK 0xfbf
+#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
 
 #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
 #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
@@ -74,6 +80,7 @@
 #define TMC_AXICTL_WR_BURST_16	0xF00
 /* Write-back Read and Write-allocate */
 #define TMC_AXICTL_AxCACHE_OS	(0xf << 2)
+#define TMC_AXICTL_ARCACHE_OS	(0xf << 16)
 
 /* TMC_FFCR - 0x304 */
 #define TMC_FFCR_FLUSHMAN_BIT	6
@@ -112,6 +119,8 @@ enum tmc_mem_intf_width {
 
 /* TMC ETR Capability bit definitions */
 #define TMC_ETR_SG			(0x1U << 0)
+/* ETR has separate read/write cache encodings */
+#define TMC_ETR_AXI_ARCACHE		(0x1U << 1)
 
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
-- 
2.7.5

[PATCH v3 16/18] coresight tmc: Support for save-restore in ETR

[Suzuki K Poulose]

The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.Full register.
This can be later exploited for proper save-restore of ETR
trace contexts (e.g, perf).

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 ++++++++++++-
 drivers/hwtracing/coresight/coresight-tmc.h     |  9 +++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index d5f51cb..a69d1c4 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -22,7 +22,7 @@
 
 static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 {
-	u32 axictl;
+	u32 axictl, sts;
 
 	/* Zero out the memory to help with debug */
 	memset(drvdata->vaddr, 0, drvdata->size);
@@ -47,6 +47,17 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 	tmc_write_dba(drvdata, drvdata->paddr);
+	/*
+	 * If the TMC pointers must be programmed before the session,
+	 * we have to set it properly (i.e, RRP/RWP to base address and
+	 * STS to "not full").
+	 */
+	if (tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE)) {
+		tmc_write_rrp(drvdata, drvdata->paddr);
+		tmc_write_rwp(drvdata, drvdata->paddr);
+		sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL;
+		writel_relaxed(sts, drvdata->base + TMC_STS);
+	}
 
 	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index de92011..5032d8e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -121,6 +121,15 @@ enum tmc_mem_intf_width {
 #define TMC_ETR_SG			(0x1U << 0)
 /* ETR has separate read/write cache encodings */
 #define TMC_ETR_AXI_ARCACHE		(0x1U << 1)
+/*
+ * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
+ * retained when TMC leaves Disabled state, allowing us to continue
+ * the tracing from a point where we stopped. This also implies that
+ * the RRP/RWP/STS.Full should always be programmed to the correct
+ * value. Unfortunately this is not advertised by the hardware,
+ * so we have to rely on PID of the IP to detect the functionality.
+ */
+#define TMC_ETR_SAVE_RESTORE		(0x1U << 2)
 
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
-- 
2.7.5

[PATCH v3 17/18] coresight tmc: Add support for Coresight SoC 600 TMC

[Suzuki K Poulose]

The coresight SoC 600 supports ETR save-restore which allows us
to restore a trace session by retaining the RRP/RWP/STS.Full values
when the TMC leaves the Disabled state. However, the TMC doesn't
have a scatter-gather unit in built.

Also, TMCs have different PIDs in different configurations (ETF,
ETB & ETR), unlike the previous generation.

While the DEVID exposes some of the features/changes in the TMC,
it doesn't explicitly advertises the new save-restore feature
as described above.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 16 ++++++++++++++++
 drivers/hwtracing/coresight/coresight-tmc.h |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 32e88ec..bf4970d 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -440,6 +440,22 @@ static struct amba_id tmc_ids[] = {
 		.id     = 0x000bb961,
 		.mask   = 0x000fffff,
 	},
+	{
+		/* Coresight SoC 600 TMC-ETR/ETS */
+		.id	= 0x000bb9e8,
+		.mask	= 0x000fffff,
+		.data	= (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
+	},
+	{
+		/* Coresight SoC 600 TMC-ETB */
+		.id	= 0x000bb9e9,
+		.mask	= 0x000fffff,
+	},
+	{
+		/* Coresight SoC 600 TMC-ETF */
+		.id	= 0x000bb9ea,
+		.mask	= 0x000fffff,
+	},
 	{ 0, 0},
 };
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 5032d8e..503c219 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -131,6 +131,10 @@ enum tmc_mem_intf_width {
  */
 #define TMC_ETR_SAVE_RESTORE		(0x1U << 2)
 
+/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
+#define CORESIGHT_SOC_600_ETR_CAPS	\
+	(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
+
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
  * @base:	memory mapped base address for this component.
-- 
2.7.5

[PATCH v3 18/18] coresight: Add support for Coresight SoC 600 components

[Suzuki K Poulose]

Add the peripheral ids for the Coresight SoC 600 TPIU, replicator
and funnel.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 5 +++++
 drivers/hwtracing/coresight/coresight-funnel.c             | 5 +++++
 drivers/hwtracing/coresight/coresight-tpiu.c               | 5 +++++
 3 files changed, 15 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
index 4df4726..8f93a00 100644
--- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
@@ -201,6 +201,11 @@ static struct amba_id replicator_ids[] = {
 		.id     = 0x000bb909,
 		.mask   = 0x000fffff,
 	},
+	{
+		/* Coresight SoC-600 */
+		.id     = 0x000bb9ec,
+		.mask   = 0x000fffff,
+	},
 	{ 0, 0 },
 };
 
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 6f7f3d3..df1cf73 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -251,6 +251,11 @@ static struct amba_id funnel_ids[] = {
 		.id     = 0x000bb908,
 		.mask   = 0x000fffff,
 	},
+	{
+		/* Coresight SoC-600 */
+		.id     = 0x000bb9eb,
+		.mask   = 0x000fffff,
+	},
 	{ 0, 0},
 };
 
diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index 59c1510..eda5d5a 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -201,6 +201,11 @@ static struct amba_id tpiu_ids[] = {
 		.id	= 0x0004b912,
 		.mask	= 0x0007ffff,
 	},
+	{
+		/* Coresight SoC-600 */
+		.id	= 0x000bb9e7,
+		.mask	= 0x000fffff,
+	},
 	{ 0, 0},
 };
 
-- 
2.7.5

Re: [PATCH v3 02/18] arm64: juno: dts: Use the new coresight replicator string

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:07PM +0100, Suzuki K Poulose wrote:
> Use the new compatible for ATB programmable replicator in Juno.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index bfe7d68..c82c706 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -373,7 +373,7 @@
>  	};
>  
>  	replicator@20120000 {
> -		compatible = "qcom,coresight-replicator1x", "arm,primecell";
> +		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
>  		reg = <0 0x20120000 0 0x1000>;
>  
>  		clocks = <&soc_smc50mhz>;

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> -- 
> 2.7.5
> 

Re: [PATCH v3 03/18] arm: qcom-msm8974: dts: Update coresight replicator

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:08PM +0100, Suzuki K Poulose wrote:
> Replace the obsolete compatible string for Coresight programmable
> replicator with the new one.
> 
> Cc: Andy Gross <andy.gross@linaro.org>
> Cc: David Brown <david.brown@linaro.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 307bf6a..3c7c6b9 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -729,7 +729,7 @@
>  		};
>  
>  		replicator@fc31c000 {
> -			compatible = "qcom,coresight-replicator1x", "arm,primecell";
> +			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
>  			reg = <0xfc31c000 0x1000>;
>  
>  			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> -- 
> 2.7.5
> 

Re: [PATCH v3 04/18] arm64: qcom-msm8916: dts: Update coresight replicator

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:09PM +0100, Suzuki K Poulose wrote:
> Replace the obsolete compatible string for Coresight programmable
> replicator with the new one.
> 
> Cc: Andy Gross <andy.gross@linaro.org>
> Cc: David Brown <david.brown@linaro.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 17691ab..a0db8c6 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -994,7 +994,7 @@
>  		};
>  
>  		replicator@824000 {
> -			compatible = "qcom,coresight-replicator1x", "arm,primecell";
> +			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
>  			reg = <0x824000 0x1000>;
>  
>  			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> -- 
> 2.7.5
> 

Re: [PATCH v3 14/18] coresight tmc etr: Cleanup AXICTL register handling

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:19PM +0100, Suzuki K Poulose wrote:
> This patch cleans up how we setup the AXICTL register on
> TMC ETR. At the moment we don't set the CacheCtrl bits, which
> drives the arcache and awcache bits on AXI bus specifying the
> cacheablitiy. Set this to Write-back Read and Write-allocate.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++-------
>  drivers/hwtracing/coresight/coresight-tmc.h     | 17 ++++++++++++++++-
>  2 files changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index ff11b92..4aa5d36 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
>  	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
>  
>  	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
> -	axictl |= TMC_AXICTL_WR_BURST_16;
> -	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
> -	axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
> -	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
> -	axictl = (axictl &
> -		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
> -		  TMC_AXICTL_PROT_CTL_B1;
> +	axictl &= ~TMC_AXICTL_CLEAR_MASK;
> +	axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
> +	axictl |= TMC_AXICTL_AxCACHE_OS;
>  	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>  	tmc_write_dba(drvdata, drvdata->paddr);
>  
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index a0668f6..5d6d7e5 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -55,11 +55,26 @@
>  #define TMC_STS_TMCREADY_BIT	2
>  #define TMC_STS_FULL		BIT(0)
>  #define TMC_STS_TRIGGERED	BIT(1)
> -/* TMC_AXICTL - 0x110 */
> +/*
> + * TMC_AXICTL - 0x110
> + *
> + * TMC AXICTL format for SoC-400
> + * 	Bits [0-1]	: ProtCtrlBit0-1
> + * 	Bits [2-5]	: CacheCtrlBits 0-3 (AxCACHE)
> + * 	Bit  6		: Reserved
> + * 	Bit  7		: ScatterGatherMode
> + * 	Bits [8-11]	: WrBurstLen
> + * 	Bits [12-31]	: Reserved.
> + */
> +#define TMC_AXICTL_CLEAR_MASK 0xfbf
> +
>  #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
>  #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
>  #define TMC_AXICTL_SCT_GAT_MODE	BIT(7)
>  #define TMC_AXICTL_WR_BURST_16	0xF00
> +/* Write-back Read and Write-allocate */
> +#define TMC_AXICTL_AxCACHE_OS	(0xf << 2)

Please use a capital 'x' here.

Also this patch is giving me a few checkpatch.pl warnings.

> +
>  /* TMC_FFCR - 0x304 */
>  #define TMC_FFCR_FLUSHMAN_BIT	6
>  #define TMC_FFCR_EN_FMT		BIT(0)
> -- 
> 2.7.5
> 

Re: [PATCH v3 01/18] coresight replicator: Cleanup programmable replicator naming

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:06PM +0100, Suzuki K Poulose wrote:
> The Linux coresight drivers define the programmable ATB replicator as
> Qualcomm replicator, while this is designed by ARM. This can cause confusion
> to a user selecting the driver. Cleanup all references to make it
>  explicitly clear. This patch :
> 
>  1) Replace the compatible string for the replicator :
> 	qcom,coresight-replicator1x => arm,coresight-dynamic-replicator
>  2) Changes the Kconfig symbol (since this is not part of any defconfigs)
> 	 CORESIGHT_QCOM_REPLICATOR => CORESIGHT_DYNAMIC_REPLICATOR
>  3) Improves the help message in the Kconfig.
>  4) Changes the name of the driver and the file :
> 	coresight-replicator-qcom => coresight-dynamic-replicator
> 
> Cc: Pratik Patel <pratikp@codeaurora.org>
> Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: devicetree@vger.kernel.org
> Cc: Mark Rutland <mark.rutland@arm.com>
> Acked-by: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since V1:
>  - Since the driver doesn't use the compatible string, change the
>    recommended compatible string.
>  - Rename the driver file to coresight-dynamic-replicator.c
> ---
>  .../devicetree/bindings/arm/coresight.txt          |   4 +-
>  drivers/hwtracing/coresight/Kconfig                |  10 +-
>  drivers/hwtracing/coresight/Makefile               |   2 +-
>  .../coresight/coresight-dynamic-replicator.c       | 195 ++++++++++++++++++++
>  .../coresight/coresight-replicator-qcom.c          | 196 ---------------------
>  5 files changed, 203 insertions(+), 204 deletions(-)
>  create mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c
>  delete mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index fcbae6a..15ac8e8 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -34,8 +34,8 @@ its hardware characteristcs.
>  		- Embedded Trace Macrocell (version 4.x):
>  			"arm,coresight-etm4x", "arm,primecell";
>  
> -		- Qualcomm Configurable Replicator (version 1.x):
> -			"qcom,coresight-replicator1x", "arm,primecell";
> +		- Coresight programmable Replicator :
> +			"arm,coresight-dynamic-replicator", "arm,primecell";
>  
>  		- System Trace Macrocell:
>  			"arm,coresight-stm", "arm,primecell"; [1]
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 8d55d6d..ef9cb3c 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -70,13 +70,13 @@ config CORESIGHT_SOURCE_ETM4X
>  	  for instruction level tracing. Depending on the implemented version
>  	  data tracing may also be available.
>  
> -config CORESIGHT_QCOM_REPLICATOR
> -	bool "Qualcomm CoreSight Replicator driver"
> +config CORESIGHT_DYNAMIC_REPLICATOR
> +	bool "CoreSight Programmable Replicator driver"
>  	depends on CORESIGHT_LINKS_AND_SINKS
>  	help
> -	  This enables support for Qualcomm CoreSight link driver. The
> -	  programmable ATB replicator sends the ATB trace stream from the
> -	  ETB/ETF to the TPIUi and ETR.
> +	  This enables support for dynamic CoreSight replicator link driver.
> +	  The programmable ATB replicator allows independent filtering of the
> +	  trace data based on the traceid.
>  
>  config CORESIGHT_STM
>  	bool "CoreSight System Trace Macrocell driver"
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 433d590..5bae90ce 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -14,6 +14,6 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
>  					coresight-etm3x-sysfs.o
>  obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
>  					coresight-etm4x-sysfs.o
> -obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
> +obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o
>  obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
> new file mode 100644
> index 0000000..1675031
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
> @@ -0,0 +1,195 @@
> +/*
> + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/amba/bus.h>
> +#include <linux/clk.h>
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +
> +#include "coresight-priv.h"
> +
> +#define REPLICATOR_IDFILTER0		0x000
> +#define REPLICATOR_IDFILTER1		0x004
> +
> +/**
> + * struct replicator_state - specifics associated to a replicator component
> + * @base:	memory mapped base address for this component.
> + * @dev:	the device entity associated with this component
> + * @atclk:	optional clock for the core parts of the replicator.
> + * @csdev:	component vitals needed by the framework
> + */
> +struct replicator_state {
> +	void __iomem		*base;
> +	struct device		*dev;
> +	struct clk		*atclk;
> +	struct coresight_device	*csdev;
> +};
> +
> +static int replicator_enable(struct coresight_device *csdev, int inport,
> +			      int outport)
> +{
> +	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> +	CS_UNLOCK(drvdata->base);
> +
> +	/*
> +	 * Ensure that the other port is disabled
> +	 * 0x00 - passing through the replicator unimpeded
> +	 * 0xff - disable (or impede) the flow of ATB data
> +	 */
> +	if (outport == 0) {
> +		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
> +	} else {
> +		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
> +	}
> +
> +	CS_LOCK(drvdata->base);
> +
> +	dev_info(drvdata->dev, "REPLICATOR enabled\n");
> +	return 0;
> +}
> +
> +static void replicator_disable(struct coresight_device *csdev, int inport,
> +				int outport)
> +{
> +	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> +	CS_UNLOCK(drvdata->base);
> +
> +	/* disable the flow of ATB data through port */
> +	if (outport == 0)
> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
> +	else
> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
> +
> +	CS_LOCK(drvdata->base);
> +
> +	dev_info(drvdata->dev, "REPLICATOR disabled\n");
> +}
> +
> +static const struct coresight_ops_link replicator_link_ops = {
> +	.enable		= replicator_enable,
> +	.disable	= replicator_disable,
> +};
> +
> +static const struct coresight_ops replicator_cs_ops = {
> +	.link_ops	= &replicator_link_ops,
> +};
> +
> +static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> +	int ret;
> +	struct device *dev = &adev->dev;
> +	struct resource *res = &adev->res;
> +	struct coresight_platform_data *pdata = NULL;
> +	struct replicator_state *drvdata;
> +	struct coresight_desc desc = { 0 };
> +	struct device_node *np = adev->dev.of_node;
> +	void __iomem *base;
> +
> +	if (np) {
> +		pdata = of_get_coresight_platform_data(dev, np);
> +		if (IS_ERR(pdata))
> +			return PTR_ERR(pdata);
> +		adev->dev.platform_data = pdata;
> +	}
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (!drvdata)
> +		return -ENOMEM;
> +
> +	drvdata->dev = &adev->dev;
> +	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
> +	if (!IS_ERR(drvdata->atclk)) {
> +		ret = clk_prepare_enable(drvdata->atclk);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* Validity for the resource is already checked by the AMBA core */
> +	base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	drvdata->base = base;
> +	dev_set_drvdata(dev, drvdata);
> +	pm_runtime_put(&adev->dev);
> +
> +	desc.type = CORESIGHT_DEV_TYPE_LINK;
> +	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
> +	desc.ops = &replicator_cs_ops;
> +	desc.pdata = adev->dev.platform_data;
> +	desc.dev = &adev->dev;
> +	drvdata->csdev = coresight_register(&desc);
> +	if (IS_ERR(drvdata->csdev))
> +		return PTR_ERR(drvdata->csdev);
> +
> +	dev_info(dev, "initialized\n");

Was it intentional to remove the original string?  If so please remove the
entire output as it doesn't give any information about the HW itself.

> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int replicator_runtime_suspend(struct device *dev)
> +{
> +	struct replicator_state *drvdata = dev_get_drvdata(dev);
> +
> +	if (drvdata && !IS_ERR(drvdata->atclk))
> +		clk_disable_unprepare(drvdata->atclk);
> +
> +	return 0;
> +}
> +
> +static int replicator_runtime_resume(struct device *dev)
> +{
> +	struct replicator_state *drvdata = dev_get_drvdata(dev);
> +
> +	if (drvdata && !IS_ERR(drvdata->atclk))
> +		clk_prepare_enable(drvdata->atclk);
> +
> +	return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops replicator_dev_pm_ops = {
> +	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
> +			   replicator_runtime_resume,
> +			   NULL)
> +};
> +
> +static struct amba_id replicator_ids[] = {
> +	{
> +		.id     = 0x0003b909,
> +		.mask   = 0x0003ffff,
> +	},
> +	{ 0, 0 },
> +};
> +
> +static struct amba_driver replicator_driver = {
> +	.drv = {
> +		.name	= "coresight-dynamic-replicator",
> +		.pm	= &replicator_dev_pm_ops,
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe		= replicator_probe,
> +	.id_table	= replicator_ids,
> +};
> +builtin_amba_driver(replicator_driver);
> diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
> deleted file mode 100644
> index 0a3d15f..0000000
> --- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -/*
> - * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -
> -#include <linux/amba/bus.h>
> -#include <linux/clk.h>
> -#include <linux/coresight.h>
> -#include <linux/device.h>
> -#include <linux/err.h>
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/kernel.h>
> -#include <linux/of.h>
> -#include <linux/pm_runtime.h>
> -#include <linux/slab.h>
> -
> -#include "coresight-priv.h"
> -
> -#define REPLICATOR_IDFILTER0		0x000
> -#define REPLICATOR_IDFILTER1		0x004
> -
> -/**
> - * struct replicator_state - specifics associated to a replicator component
> - * @base:	memory mapped base address for this component.
> - * @dev:	the device entity associated with this component
> - * @atclk:	optional clock for the core parts of the replicator.
> - * @csdev:	component vitals needed by the framework
> - */
> -struct replicator_state {
> -	void __iomem		*base;
> -	struct device		*dev;
> -	struct clk		*atclk;
> -	struct coresight_device	*csdev;
> -};
> -
> -static int replicator_enable(struct coresight_device *csdev, int inport,
> -			      int outport)
> -{
> -	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
> -
> -	CS_UNLOCK(drvdata->base);
> -
> -	/*
> -	 * Ensure that the other port is disabled
> -	 * 0x00 - passing through the replicator unimpeded
> -	 * 0xff - disable (or impede) the flow of ATB data
> -	 */
> -	if (outport == 0) {
> -		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
> -	} else {
> -		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
> -	}
> -
> -	CS_LOCK(drvdata->base);
> -
> -	dev_info(drvdata->dev, "REPLICATOR enabled\n");
> -	return 0;
> -}
> -
> -static void replicator_disable(struct coresight_device *csdev, int inport,
> -				int outport)
> -{
> -	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
> -
> -	CS_UNLOCK(drvdata->base);
> -
> -	/* disable the flow of ATB data through port */
> -	if (outport == 0)
> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
> -	else
> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
> -
> -	CS_LOCK(drvdata->base);
> -
> -	dev_info(drvdata->dev, "REPLICATOR disabled\n");
> -}
> -
> -static const struct coresight_ops_link replicator_link_ops = {
> -	.enable		= replicator_enable,
> -	.disable	= replicator_disable,
> -};
> -
> -static const struct coresight_ops replicator_cs_ops = {
> -	.link_ops	= &replicator_link_ops,
> -};
> -
> -static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
> -{
> -	int ret;
> -	struct device *dev = &adev->dev;
> -	struct resource *res = &adev->res;
> -	struct coresight_platform_data *pdata = NULL;
> -	struct replicator_state *drvdata;
> -	struct coresight_desc desc = { 0 };
> -	struct device_node *np = adev->dev.of_node;
> -	void __iomem *base;
> -
> -	if (np) {
> -		pdata = of_get_coresight_platform_data(dev, np);
> -		if (IS_ERR(pdata))
> -			return PTR_ERR(pdata);
> -		adev->dev.platform_data = pdata;
> -	}
> -
> -	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> -	if (!drvdata)
> -		return -ENOMEM;
> -
> -	drvdata->dev = &adev->dev;
> -	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
> -	if (!IS_ERR(drvdata->atclk)) {
> -		ret = clk_prepare_enable(drvdata->atclk);
> -		if (ret)
> -			return ret;
> -	}
> -
> -	/* Validity for the resource is already checked by the AMBA core */
> -	base = devm_ioremap_resource(dev, res);
> -	if (IS_ERR(base))
> -		return PTR_ERR(base);
> -
> -	drvdata->base = base;
> -	dev_set_drvdata(dev, drvdata);
> -	pm_runtime_put(&adev->dev);
> -
> -	desc.type = CORESIGHT_DEV_TYPE_LINK;
> -	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
> -	desc.ops = &replicator_cs_ops;
> -	desc.pdata = adev->dev.platform_data;
> -	desc.dev = &adev->dev;
> -	drvdata->csdev = coresight_register(&desc);
> -	if (IS_ERR(drvdata->csdev))
> -		return PTR_ERR(drvdata->csdev);
> -
> -	dev_info(dev, "%s initialized\n", (char *)id->data);
> -	return 0;
> -}
> -
> -#ifdef CONFIG_PM
> -static int replicator_runtime_suspend(struct device *dev)
> -{
> -	struct replicator_state *drvdata = dev_get_drvdata(dev);
> -
> -	if (drvdata && !IS_ERR(drvdata->atclk))
> -		clk_disable_unprepare(drvdata->atclk);
> -
> -	return 0;
> -}
> -
> -static int replicator_runtime_resume(struct device *dev)
> -{
> -	struct replicator_state *drvdata = dev_get_drvdata(dev);
> -
> -	if (drvdata && !IS_ERR(drvdata->atclk))
> -		clk_prepare_enable(drvdata->atclk);
> -
> -	return 0;
> -}
> -#endif
> -
> -static const struct dev_pm_ops replicator_dev_pm_ops = {
> -	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
> -			   replicator_runtime_resume,
> -			   NULL)
> -};
> -
> -static struct amba_id replicator_ids[] = {
> -	{
> -		.id     = 0x0003b909,
> -		.mask   = 0x0003ffff,
> -		.data	= "REPLICATOR 1.0",
> -	},
> -	{ 0, 0 },
> -};
> -
> -static struct amba_driver replicator_driver = {
> -	.drv = {
> -		.name	= "coresight-replicator-qcom",
> -		.pm	= &replicator_dev_pm_ops,
> -		.suppress_bind_attrs = true,
> -	},
> -	.probe		= replicator_probe,
> -	.id_table	= replicator_ids,
> -};
> -builtin_amba_driver(replicator_driver);
> -- 
> 2.7.5
> 

Re: [PATCH v3 00/16] coresight: Support for ARM Coresight SoC-600

[Mathieu Poirier]

On Fri, Jul 14, 2017 at 02:04:05PM +0100, Suzuki K Poulose wrote:
> This series adds support for ARM Coresight SoC-600 IP, which implements
> Coresight V3 architecture. It also does some clean up of the replicator
> driver namings used in the driver to prevent confusions to the user.
> 
> The SoC-600 comes with an improved TMC which supports new features,
> including Save-Restore and Software FIFO2 mode (for streaming the trace
> data over functional I/O like USB/PCI).
> 
> This series only supports Save-Restore feature of the new ETR by reusing
> the driver to perform additional setups required in case we are dealing
> with an IP which supports it. Towards this we keep track of the capabilities
> of the given TMC ETR. Some of the features are advertised via DEVID
> register (address width, scatter gather support), while some are not
> (save-restore). So we attach a static capability mask with the device
> PID for the unadvertised features and detect the rest at device probe.
> 
> Tested on Juno (with Coresight SoC 400) and an FPGA based system
> for SoC 600. Applies on Mathieu's coresight/next.
> 
> Changes since V2:
>  - Fix typos in masks for ETM3.
>  - Fix all dts for obsoleted compatible string for replicator.
>  - Detect advertised capabilities at runtime.
>  - Add support for detecting the address width at runtime, new
>    feature in SoC-600.
>  - Add support for split ARCACHE/WCACHE encoding for AXI transactions
> 
> Changes since V1
>  - Rename coresight-replicator-qcom.c => coresight-dynamic-replicator.c
>  - Fix PIDR2 codings for ETB-10, ETM3x
>  - Fix cosmetic issues pointed out by  Mathieu
>  - Fix commit description for
> 	 "coresight tmc: Handle configuration types properly"
>  - Drop SWFIFO2 from the capability of SoC-600 TMC
> 
> 
> Suzuki K Poulose (18):
>   coresight replicator: Cleanup programmable replicator naming
>   arm64: juno: dts:  Use the new coresight replicator string
>   arm: qcom-msm8974: dts: Update coresight replicator
>   arm64: qcom-msm8916: dts: Update coresight replicator
>   coresight: Extend the PIDR mask to cover relevant bits in PIDR2
>   coresight: Add support for reading 64bit registers
>   coresight tmc: Add helpers for accessing 64bit registers
>   coresight tmc: Expose DBA and AXICTL
>   coresight replicator: Expose replicator management registers
>   coresight tmc: Handle configuration types properly
>   coresight tmc etr: Add capabilitiy information
>   coresight tmc: Detect support for scatter gather
>   coresight tmc etr: Detect address width at runtime
>   coresight tmc etr: Cleanup AXICTL register handling
>   coresigh tmc etr: Setup AXI cache encoding for read transfers
>   coresight tmc: Support for save-restore in ETR
>   coresight tmc: Add support for Coresight SoC 600 TMC
>   coresight: Add support for Coresight SoC 600 components
> 
>  .../devicetree/bindings/arm/coresight.txt          |   4 +-
>  arch/arm/boot/dts/qcom-msm8974.dtsi                |   2 +-
>  arch/arm64/boot/dts/arm/juno-base.dtsi             |   2 +-
>  arch/arm64/boot/dts/qcom/msm8916.dtsi              |   2 +-
>  drivers/hwtracing/coresight/Kconfig                |  10 +-
>  drivers/hwtracing/coresight/Makefile               |   2 +-
>  .../coresight/coresight-dynamic-replicator.c       | 221 +++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-etb10.c      |   4 +-
>  drivers/hwtracing/coresight/coresight-etm3x.c      |  24 +--
>  drivers/hwtracing/coresight/coresight-funnel.c     |   9 +-
>  drivers/hwtracing/coresight/coresight-priv.h       |  35 +++-
>  .../coresight/coresight-replicator-qcom.c          | 196 ------------------
>  drivers/hwtracing/coresight/coresight-stm.c        |   8 +-
>  drivers/hwtracing/coresight/coresight-tmc-etf.c    |   8 +-
>  drivers/hwtracing/coresight/coresight-tmc-etr.c    |  37 ++--
>  drivers/hwtracing/coresight/coresight-tmc.c        |  84 ++++++--
>  drivers/hwtracing/coresight/coresight-tmc.h        |  87 +++++++-
>  drivers/hwtracing/coresight/coresight-tpiu.c       |   9 +-
>  18 files changed, 481 insertions(+), 263 deletions(-)
>  create mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c
>  delete mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c

Good day,

I'm good with the code in this set - but I need it to be rebased on
4.13-rc1 and the checkpatch errors addressed.

There's also an extra line in 07 that isn't detected by checkpatch.

Thanks,
Mathieu


> 
> -- 
> 2.7.5
> 

Re: [PATCH v3 14/18] coresight tmc etr: Cleanup AXICTL register handling

[Suzuki K Poulose]

On 17/07/17 18:06, Mathieu Poirier wrote:
> On Fri, Jul 14, 2017 at 02:04:19PM +0100, Suzuki K Poulose wrote:
>> This patch cleans up how we setup the AXICTL register on
>> TMC ETR. At the moment we don't set the CacheCtrl bits, which
>> drives the arcache and awcache bits on AXI bus specifying the
>> cacheablitiy. Set this to Write-back Read and Write-allocate.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>>  drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++-------
>>  drivers/hwtracing/coresight/coresight-tmc.h     | 17 ++++++++++++++++-
>>  2 files changed, 19 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> index ff11b92..4aa5d36 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> @@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
>>  	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
>>
>>  	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
>> -	axictl |= TMC_AXICTL_WR_BURST_16;
>> -	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>> -	axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
>> -	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>> -	axictl = (axictl &
>> -		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
>> -		  TMC_AXICTL_PROT_CTL_B1;
>> +	axictl &= ~TMC_AXICTL_CLEAR_MASK;
>> +	axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
>> +	axictl |= TMC_AXICTL_AxCACHE_OS;
>>  	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>>  	tmc_write_dba(drvdata, drvdata->paddr);
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
>> index a0668f6..5d6d7e5 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.h
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
>> @@ -55,11 +55,26 @@
>>  #define TMC_STS_TMCREADY_BIT	2
>>  #define TMC_STS_FULL		BIT(0)
>>  #define TMC_STS_TRIGGERED	BIT(1)
>> -/* TMC_AXICTL - 0x110 */
>> +/*
>> + * TMC_AXICTL - 0x110
>> + *
>> + * TMC AXICTL format for SoC-400
>> + * 	Bits [0-1]	: ProtCtrlBit0-1
>> + * 	Bits [2-5]	: CacheCtrlBits 0-3 (AxCACHE)
>> + * 	Bit  6		: Reserved
>> + * 	Bit  7		: ScatterGatherMode
>> + * 	Bits [8-11]	: WrBurstLen
>> + * 	Bits [12-31]	: Reserved.
>> + */
>> +#define TMC_AXICTL_CLEAR_MASK 0xfbf
>> +
>>  #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
>>  #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
>>  #define TMC_AXICTL_SCT_GAT_MODE	BIT(7)
>>  #define TMC_AXICTL_WR_BURST_16	0xF00
>> +/* Write-back Read and Write-allocate */
>> +#define TMC_AXICTL_AxCACHE_OS	(0xf << 2)
>
> Please use a capital 'x' here.

Sure, fixed in the next version.

>
> Also this patch is giving me a few checkpatch.pl warnings.
>

Thats because of the space before the TABs in the comment section
above describing the bits. I have fixed it now, though I am not sure
if it checkpatch should really complain about it.

Cheers
Suzuki

>> +
>>  /* TMC_FFCR - 0x304 */
>>  #define TMC_FFCR_FLUSHMAN_BIT	6
>>  #define TMC_FFCR_EN_FMT		BIT(0)
>> --
>> 2.7.5
>>

Re: [PATCH v3 01/18] coresight replicator: Cleanup programmable replicator naming

[Suzuki K Poulose]

On 17/07/17 18:45, Mathieu Poirier wrote:
> On Fri, Jul 14, 2017 at 02:04:06PM +0100, Suzuki K Poulose wrote:
>> The Linux coresight drivers define the programmable ATB replicator as
>> Qualcomm replicator, while this is designed by ARM. This can cause confusion
>> to a user selecting the driver. Cleanup all references to make it
>>  explicitly clear. This patch :
>>
>>  1) Replace the compatible string for the replicator :
>> 	qcom,coresight-replicator1x => arm,coresight-dynamic-replicator
>>  2) Changes the Kconfig symbol (since this is not part of any defconfigs)
>> 	 CORESIGHT_QCOM_REPLICATOR => CORESIGHT_DYNAMIC_REPLICATOR
>>  3) Improves the help message in the Kconfig.
>>  4) Changes the name of the driver and the file :
>> 	coresight-replicator-qcom => coresight-dynamic-replicator
>>
>> Cc: Pratik Patel <pratikp@codeaurora.org>
>> Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: devicetree@vger.kernel.org
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Acked-by: Rob Herring <robh+dt@kernel.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> Changes since V1:
>>  - Since the driver doesn't use the compatible string, change the
>>    recommended compatible string.
>>  - Rename the driver file to coresight-dynamic-replicator.c
>> ---
>>  .../devicetree/bindings/arm/coresight.txt          |   4 +-
>>  drivers/hwtracing/coresight/Kconfig                |  10 +-
>>  drivers/hwtracing/coresight/Makefile               |   2 +-
>>  .../coresight/coresight-dynamic-replicator.c       | 195 ++++++++++++++++++++
>>  .../coresight/coresight-replicator-qcom.c          | 196 ---------------------
>>  5 files changed, 203 insertions(+), 204 deletions(-)
>>  create mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c
>>  delete mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
>> index fcbae6a..15ac8e8 100644
>> --- a/Documentation/devicetree/bindings/arm/coresight.txt
>> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
>> @@ -34,8 +34,8 @@ its hardware characteristcs.
>>  		- Embedded Trace Macrocell (version 4.x):
>>  			"arm,coresight-etm4x", "arm,primecell";
>>
>> -		- Qualcomm Configurable Replicator (version 1.x):
>> -			"qcom,coresight-replicator1x", "arm,primecell";
>> +		- Coresight programmable Replicator :
>> +			"arm,coresight-dynamic-replicator", "arm,primecell";
>>
>>  		- System Trace Macrocell:
>>  			"arm,coresight-stm", "arm,primecell"; [1]
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index 8d55d6d..ef9cb3c 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -70,13 +70,13 @@ config CORESIGHT_SOURCE_ETM4X
>>  	  for instruction level tracing. Depending on the implemented version
>>  	  data tracing may also be available.
>>
>> -config CORESIGHT_QCOM_REPLICATOR
>> -	bool "Qualcomm CoreSight Replicator driver"
>> +config CORESIGHT_DYNAMIC_REPLICATOR
>> +	bool "CoreSight Programmable Replicator driver"
>>  	depends on CORESIGHT_LINKS_AND_SINKS
>>  	help
>> -	  This enables support for Qualcomm CoreSight link driver. The
>> -	  programmable ATB replicator sends the ATB trace stream from the
>> -	  ETB/ETF to the TPIUi and ETR.
>> +	  This enables support for dynamic CoreSight replicator link driver.
>> +	  The programmable ATB replicator allows independent filtering of the
>> +	  trace data based on the traceid.
>>
>>  config CORESIGHT_STM
>>  	bool "CoreSight System Trace Macrocell driver"
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>> index 433d590..5bae90ce 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -14,6 +14,6 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
>>  					coresight-etm3x-sysfs.o
>>  obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
>>  					coresight-etm4x-sysfs.o
>> -obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
>> +obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o
>>  obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>> diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
>> new file mode 100644
>> index 0000000..1675031
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c
>> @@ -0,0 +1,195 @@
>> +/*
>> + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/amba/bus.h>
>> +#include <linux/clk.h>
>> +#include <linux/coresight.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/slab.h>
>> +
>> +#include "coresight-priv.h"
>> +
>> +#define REPLICATOR_IDFILTER0		0x000
>> +#define REPLICATOR_IDFILTER1		0x004
>> +
>> +/**
>> + * struct replicator_state - specifics associated to a replicator component
>> + * @base:	memory mapped base address for this component.
>> + * @dev:	the device entity associated with this component
>> + * @atclk:	optional clock for the core parts of the replicator.
>> + * @csdev:	component vitals needed by the framework
>> + */
>> +struct replicator_state {
>> +	void __iomem		*base;
>> +	struct device		*dev;
>> +	struct clk		*atclk;
>> +	struct coresight_device	*csdev;
>> +};
>> +
>> +static int replicator_enable(struct coresight_device *csdev, int inport,
>> +			      int outport)
>> +{
>> +	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> +	CS_UNLOCK(drvdata->base);
>> +
>> +	/*
>> +	 * Ensure that the other port is disabled
>> +	 * 0x00 - passing through the replicator unimpeded
>> +	 * 0xff - disable (or impede) the flow of ATB data
>> +	 */
>> +	if (outport == 0) {
>> +		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
>> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
>> +	} else {
>> +		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
>> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
>> +	}
>> +
>> +	CS_LOCK(drvdata->base);
>> +
>> +	dev_info(drvdata->dev, "REPLICATOR enabled\n");
>> +	return 0;
>> +}
>> +
>> +static void replicator_disable(struct coresight_device *csdev, int inport,
>> +				int outport)
>> +{
>> +	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> +	CS_UNLOCK(drvdata->base);
>> +
>> +	/* disable the flow of ATB data through port */
>> +	if (outport == 0)
>> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
>> +	else
>> +		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
>> +
>> +	CS_LOCK(drvdata->base);
>> +
>> +	dev_info(drvdata->dev, "REPLICATOR disabled\n");
>> +}
>> +
>> +static const struct coresight_ops_link replicator_link_ops = {
>> +	.enable		= replicator_enable,
>> +	.disable	= replicator_disable,
>> +};
>> +
>> +static const struct coresight_ops replicator_cs_ops = {
>> +	.link_ops	= &replicator_link_ops,
>> +};
>> +
>> +static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
>> +{
>> +	int ret;
>> +	struct device *dev = &adev->dev;
>> +	struct resource *res = &adev->res;
>> +	struct coresight_platform_data *pdata = NULL;
>> +	struct replicator_state *drvdata;
>> +	struct coresight_desc desc = { 0 };
>> +	struct device_node *np = adev->dev.of_node;
>> +	void __iomem *base;
>> +
>> +	if (np) {
>> +		pdata = of_get_coresight_platform_data(dev, np);
>> +		if (IS_ERR(pdata))
>> +			return PTR_ERR(pdata);
>> +		adev->dev.platform_data = pdata;
>> +	}
>> +
>> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> +	if (!drvdata)
>> +		return -ENOMEM;
>> +
>> +	drvdata->dev = &adev->dev;
>> +	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
>> +	if (!IS_ERR(drvdata->atclk)) {
>> +		ret = clk_prepare_enable(drvdata->atclk);
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	/* Validity for the resource is already checked by the AMBA core */
>> +	base = devm_ioremap_resource(dev, res);
>> +	if (IS_ERR(base))
>> +		return PTR_ERR(base);
>> +
>> +	drvdata->base = base;
>> +	dev_set_drvdata(dev, drvdata);
>> +	pm_runtime_put(&adev->dev);
>> +
>> +	desc.type = CORESIGHT_DEV_TYPE_LINK;
>> +	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
>> +	desc.ops = &replicator_cs_ops;
>> +	desc.pdata = adev->dev.platform_data;
>> +	desc.dev = &adev->dev;
>> +	drvdata->csdev = coresight_register(&desc);
>> +	if (IS_ERR(drvdata->csdev))
>> +		return PTR_ERR(drvdata->csdev);
>> +
>> +	dev_info(dev, "initialized\n");
>
> Was it intentional to remove the original string?  If so please remove the

Yes, it doesn't make sense to display REPLICATOR 1.0, which isn't really any
formal name of the product of family.

> entire output as it doesn't give any information about the HW itself.

Sure, I can remove it.

Cheers
Suzuki

>
>> +	return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int replicator_runtime_suspend(struct device *dev)
>> +{
>> +	struct replicator_state *drvdata = dev_get_drvdata(dev);
>> +
>> +	if (drvdata && !IS_ERR(drvdata->atclk))
>> +		clk_disable_unprepare(drvdata->atclk);
>> +
>> +	return 0;
>> +}
>> +
>> +static int replicator_runtime_resume(struct device *dev)
>> +{
>> +	struct replicator_state *drvdata = dev_get_drvdata(dev);
>> +
>> +	if (drvdata && !IS_ERR(drvdata->atclk))
>> +		clk_prepare_enable(drvdata->atclk);
>> +
>> +	return 0;
>> +}
>> +#endif
>> +
>> +static const struct dev_pm_ops replicator_dev_pm_ops = {
>> +	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
>> +			   replicator_runtime_resume,
>> +			   NULL)
>> +};
>> +
>> +static struct amba_id replicator_ids[] = {
>> +	{
>> +		.id     = 0x0003b909,
>> +		.mask   = 0x0003ffff,
>> +	},
>> +	{ 0, 0 },
>> +};
>> +
>> +static struct amba_driver replicator_driver = {
>> +	.drv = {
>> +		.name	= "coresight-dynamic-replicator",
>> +		.pm	= &replicator_dev_pm_ops,
>> +		.suppress_bind_attrs = true,
>> +	},
>> +	.probe		= replicator_probe,
>> +	.id_table	= replicator_ids,
>> +};
>> +builtin_amba_driver(replicator_driver);
>> diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
>> deleted file mode 100644
>> index 0a3d15f..0000000
>> --- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
>> +++ /dev/null
>> @@ -1,196 +0,0 @@
>> -/*
>> - * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 and
>> - * only version 2 as published by the Free Software Foundation.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> - * GNU General Public License for more details.
>> - */
>> -
>> -#include <linux/amba/bus.h>
>> -#include <linux/clk.h>
>> -#include <linux/coresight.h>
>> -#include <linux/device.h>
>> -#include <linux/err.h>
>> -#include <linux/init.h>
>> -#include <linux/io.h>
>> -#include <linux/kernel.h>
>> -#include <linux/of.h>
>> -#include <linux/pm_runtime.h>
>> -#include <linux/slab.h>
>> -
>> -#include "coresight-priv.h"
>> -
>> -#define REPLICATOR_IDFILTER0		0x000
>> -#define REPLICATOR_IDFILTER1		0x004
>> -
>> -/**
>> - * struct replicator_state - specifics associated to a replicator component
>> - * @base:	memory mapped base address for this component.
>> - * @dev:	the device entity associated with this component
>> - * @atclk:	optional clock for the core parts of the replicator.
>> - * @csdev:	component vitals needed by the framework
>> - */
>> -struct replicator_state {
>> -	void __iomem		*base;
>> -	struct device		*dev;
>> -	struct clk		*atclk;
>> -	struct coresight_device	*csdev;
>> -};
>> -
>> -static int replicator_enable(struct coresight_device *csdev, int inport,
>> -			      int outport)
>> -{
>> -	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
>> -
>> -	CS_UNLOCK(drvdata->base);
>> -
>> -	/*
>> -	 * Ensure that the other port is disabled
>> -	 * 0x00 - passing through the replicator unimpeded
>> -	 * 0xff - disable (or impede) the flow of ATB data
>> -	 */
>> -	if (outport == 0) {
>> -		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0);
>> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
>> -	} else {
>> -		writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1);
>> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
>> -	}
>> -
>> -	CS_LOCK(drvdata->base);
>> -
>> -	dev_info(drvdata->dev, "REPLICATOR enabled\n");
>> -	return 0;
>> -}
>> -
>> -static void replicator_disable(struct coresight_device *csdev, int inport,
>> -				int outport)
>> -{
>> -	struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
>> -
>> -	CS_UNLOCK(drvdata->base);
>> -
>> -	/* disable the flow of ATB data through port */
>> -	if (outport == 0)
>> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
>> -	else
>> -		writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
>> -
>> -	CS_LOCK(drvdata->base);
>> -
>> -	dev_info(drvdata->dev, "REPLICATOR disabled\n");
>> -}
>> -
>> -static const struct coresight_ops_link replicator_link_ops = {
>> -	.enable		= replicator_enable,
>> -	.disable	= replicator_disable,
>> -};
>> -
>> -static const struct coresight_ops replicator_cs_ops = {
>> -	.link_ops	= &replicator_link_ops,
>> -};
>> -
>> -static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
>> -{
>> -	int ret;
>> -	struct device *dev = &adev->dev;
>> -	struct resource *res = &adev->res;
>> -	struct coresight_platform_data *pdata = NULL;
>> -	struct replicator_state *drvdata;
>> -	struct coresight_desc desc = { 0 };
>> -	struct device_node *np = adev->dev.of_node;
>> -	void __iomem *base;
>> -
>> -	if (np) {
>> -		pdata = of_get_coresight_platform_data(dev, np);
>> -		if (IS_ERR(pdata))
>> -			return PTR_ERR(pdata);
>> -		adev->dev.platform_data = pdata;
>> -	}
>> -
>> -	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> -	if (!drvdata)
>> -		return -ENOMEM;
>> -
>> -	drvdata->dev = &adev->dev;
>> -	drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
>> -	if (!IS_ERR(drvdata->atclk)) {
>> -		ret = clk_prepare_enable(drvdata->atclk);
>> -		if (ret)
>> -			return ret;
>> -	}
>> -
>> -	/* Validity for the resource is already checked by the AMBA core */
>> -	base = devm_ioremap_resource(dev, res);
>> -	if (IS_ERR(base))
>> -		return PTR_ERR(base);
>> -
>> -	drvdata->base = base;
>> -	dev_set_drvdata(dev, drvdata);
>> -	pm_runtime_put(&adev->dev);
>> -
>> -	desc.type = CORESIGHT_DEV_TYPE_LINK;
>> -	desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT;
>> -	desc.ops = &replicator_cs_ops;
>> -	desc.pdata = adev->dev.platform_data;
>> -	desc.dev = &adev->dev;
>> -	drvdata->csdev = coresight_register(&desc);
>> -	if (IS_ERR(drvdata->csdev))
>> -		return PTR_ERR(drvdata->csdev);
>> -
>> -	dev_info(dev, "%s initialized\n", (char *)id->data);
>> -	return 0;
>> -}
>> -
>> -#ifdef CONFIG_PM
>> -static int replicator_runtime_suspend(struct device *dev)
>> -{
>> -	struct replicator_state *drvdata = dev_get_drvdata(dev);
>> -
>> -	if (drvdata && !IS_ERR(drvdata->atclk))
>> -		clk_disable_unprepare(drvdata->atclk);
>> -
>> -	return 0;
>> -}
>> -
>> -static int replicator_runtime_resume(struct device *dev)
>> -{
>> -	struct replicator_state *drvdata = dev_get_drvdata(dev);
>> -
>> -	if (drvdata && !IS_ERR(drvdata->atclk))
>> -		clk_prepare_enable(drvdata->atclk);
>> -
>> -	return 0;
>> -}
>> -#endif
>> -
>> -static const struct dev_pm_ops replicator_dev_pm_ops = {
>> -	SET_RUNTIME_PM_OPS(replicator_runtime_suspend,
>> -			   replicator_runtime_resume,
>> -			   NULL)
>> -};
>> -
>> -static struct amba_id replicator_ids[] = {
>> -	{
>> -		.id     = 0x0003b909,
>> -		.mask   = 0x0003ffff,
>> -		.data	= "REPLICATOR 1.0",
>> -	},
>> -	{ 0, 0 },
>> -};
>> -
>> -static struct amba_driver replicator_driver = {
>> -	.drv = {
>> -		.name	= "coresight-replicator-qcom",
>> -		.pm	= &replicator_dev_pm_ops,
>> -		.suppress_bind_attrs = true,
>> -	},
>> -	.probe		= replicator_probe,
>> -	.id_table	= replicator_ids,
>> -};
>> -builtin_amba_driver(replicator_driver);
>> --
>> 2.7.5
>>