From: Joerg Roedel <joro@8bytes.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>, "H . Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Linus Torvalds <torvalds@linux-foundation.org>,
Andy Lutomirski <luto@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>, Jiri Kosina <jkosina@suse.cz>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Brian Gerst <brgerst@gmail.com>,
David Laight <David.Laight@aculab.com>,
Denys Vlasenko <dvlasenk@redhat.com>,
Eduardo Valentin <eduval@amazon.com>,
Greg KH <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
aliguori@amazon.com, daniel.gruss@iaik.tugraz.at,
hughd@google.com, keescook@google.com,
Andrea Arcangeli <aarcange@redhat.com>,
Waiman Long <llong@redhat.com>, Pavel Machek <pavel@ucw.cz>,
"David H . Gutteridge" <dhgutteridge@sympatico.ca>,
jroedel@suse.de, joro@8bytes.org
Subject: [PATCH 04/37] x86/entry/32: Put ESPFIX code into a macro
Date: Mon, 23 Apr 2018 17:47:07 +0200 [thread overview]
Message-ID: <1524498460-25530-5-git-send-email-joro@8bytes.org> (raw)
In-Reply-To: <1524498460-25530-1-git-send-email-joro@8bytes.org>
From: Joerg Roedel <jroedel@suse.de>
This makes it easier to split up the shared iret code path.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
arch/x86/entry/entry_32.S | 97 ++++++++++++++++++++++++-----------------------
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S
index ec288be..118420b 100644
--- a/arch/x86/entry/entry_32.S
+++ b/arch/x86/entry/entry_32.S
@@ -221,6 +221,54 @@
POP_GS_EX
.endm
+.macro CHECK_AND_APPLY_ESPFIX
+#ifdef CONFIG_X86_ESPFIX32
+#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8)
+
+ ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
+
+ movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
+ /*
+ * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
+ * are returning to the kernel.
+ * See comments in process.c:copy_thread() for details.
+ */
+ movb PT_OLDSS(%esp), %ah
+ movb PT_CS(%esp), %al
+ andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
+ cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
+ jne .Lend_\@ # returning to user-space with LDT SS
+
+ /*
+ * Setup and switch to ESPFIX stack
+ *
+ * We're returning to userspace with a 16 bit stack. The CPU will not
+ * restore the high word of ESP for us on executing iret... This is an
+ * "official" bug of all the x86-compatible CPUs, which we can work
+ * around to make dosemu and wine happy. We do this by preloading the
+ * high word of ESP with the high word of the userspace ESP while
+ * compensating for the offset by changing to the ESPFIX segment with
+ * a base address that matches for the difference.
+ */
+ mov %esp, %edx /* load kernel esp */
+ mov PT_OLDESP(%esp), %eax /* load userspace esp */
+ mov %dx, %ax /* eax: new kernel esp */
+ sub %eax, %edx /* offset (low word is 0) */
+ shr $16, %edx
+ mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
+ mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
+ pushl $__ESPFIX_SS
+ pushl %eax /* new kernel esp */
+ /*
+ * Disable interrupts, but do not irqtrace this section: we
+ * will soon execute iret and the tracer was already set to
+ * the irqstate after the IRET:
+ */
+ DISABLE_INTERRUPTS(CLBR_ANY)
+ lss (%esp), %esp /* switch to espfix segment */
+.Lend_\@:
+#endif /* CONFIG_X86_ESPFIX32 */
+.endm
/*
* %eax: prev task
* %edx: next task
@@ -547,21 +595,7 @@ ENTRY(entry_INT80_32)
restore_all:
TRACE_IRQS_IRET
.Lrestore_all_notrace:
-#ifdef CONFIG_X86_ESPFIX32
- ALTERNATIVE "jmp .Lrestore_nocheck", "", X86_BUG_ESPFIX
-
- movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
- /*
- * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
- * are returning to the kernel.
- * See comments in process.c:copy_thread() for details.
- */
- movb PT_OLDSS(%esp), %ah
- movb PT_CS(%esp), %al
- andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
- cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
- je .Lldt_ss # returning to user-space with LDT SS
-#endif
+ CHECK_AND_APPLY_ESPFIX
.Lrestore_nocheck:
RESTORE_REGS 4 # skip orig_eax/error_code
.Lirq_return:
@@ -579,39 +613,6 @@ ENTRY(iret_exc )
jmp common_exception
.previous
_ASM_EXTABLE(.Lirq_return, iret_exc)
-
-#ifdef CONFIG_X86_ESPFIX32
-.Lldt_ss:
-/*
- * Setup and switch to ESPFIX stack
- *
- * We're returning to userspace with a 16 bit stack. The CPU will not
- * restore the high word of ESP for us on executing iret... This is an
- * "official" bug of all the x86-compatible CPUs, which we can work
- * around to make dosemu and wine happy. We do this by preloading the
- * high word of ESP with the high word of the userspace ESP while
- * compensating for the offset by changing to the ESPFIX segment with
- * a base address that matches for the difference.
- */
-#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8)
- mov %esp, %edx /* load kernel esp */
- mov PT_OLDESP(%esp), %eax /* load userspace esp */
- mov %dx, %ax /* eax: new kernel esp */
- sub %eax, %edx /* offset (low word is 0) */
- shr $16, %edx
- mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
- mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
- pushl $__ESPFIX_SS
- pushl %eax /* new kernel esp */
- /*
- * Disable interrupts, but do not irqtrace this section: we
- * will soon execute iret and the tracer was already set to
- * the irqstate after the IRET:
- */
- DISABLE_INTERRUPTS(CLBR_ANY)
- lss (%esp), %esp /* switch to espfix segment */
- jmp .Lrestore_nocheck
-#endif
ENDPROC(entry_INT80_32)
.macro FIXUP_ESPFIX_STACK
--
2.7.4
next prev parent reply other threads:[~2018-04-23 15:47 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-23 15:47 [PATCH 00/37 v6] PTI support for x86-32 Joerg Roedel
2018-04-23 15:47 ` [PATCH 01/37] x86/asm-offsets: Move TSS_sp0 and TSS_sp1 to asm-offsets.c Joerg Roedel
2018-04-23 15:47 ` [PATCH 02/37] x86/entry/32: Rename TSS_sysenter_sp0 to TSS_entry_stack Joerg Roedel
2018-04-23 15:47 ` [PATCH 03/37] x86/entry/32: Load task stack from x86_tss.sp1 in SYSENTER handler Joerg Roedel
2018-04-23 15:47 ` Joerg Roedel [this message]
2018-04-23 15:47 ` [PATCH 05/37] x86/entry/32: Unshare NMI return path Joerg Roedel
2018-04-23 15:47 ` [PATCH 06/37] x86/entry/32: Split off return-to-kernel path Joerg Roedel
2018-04-23 15:47 ` [PATCH 07/37] x86/entry/32: Enter the kernel via trampoline stack Joerg Roedel
2018-04-23 15:47 ` [PATCH 08/37] x86/entry/32: Leave " Joerg Roedel
2018-04-23 15:47 ` [PATCH 09/37] x86/entry/32: Introduce SAVE_ALL_NMI and RESTORE_ALL_NMI Joerg Roedel
2018-04-23 15:47 ` [PATCH 10/37] x86/entry/32: Handle Entry from Kernel-Mode on Entry-Stack Joerg Roedel
2018-04-23 15:47 ` [PATCH 11/37] x86/entry/32: Simplify debug entry point Joerg Roedel
2018-04-23 15:47 ` [PATCH 12/37] x86/32: Use tss.sp1 as cpu_current_top_of_stack Joerg Roedel
2018-04-23 15:47 ` [PATCH 13/37] x86/entry/32: Add PTI cr3 switch to non-NMI entry/exit points Joerg Roedel
2018-04-23 15:47 ` [PATCH 14/37] x86/entry/32: Add PTI cr3 switches to NMI handler code Joerg Roedel
2018-04-23 15:47 ` [PATCH 15/37] x86/pgtable: Rename pti_set_user_pgd to pti_set_user_pgtbl Joerg Roedel
2018-04-23 15:47 ` [PATCH 16/37] x86/pgtable/pae: Unshare kernel PMDs when PTI is enabled Joerg Roedel
2018-04-23 15:47 ` [PATCH 17/37] x86/pgtable/32: Allocate 8k page-tables " Joerg Roedel
2018-04-23 15:47 ` [PATCH 18/37] x86/pgtable: Move pgdp kernel/user conversion functions to pgtable.h Joerg Roedel
2018-04-23 15:47 ` [PATCH 19/37] x86/pgtable: Move pti_set_user_pgtbl() " Joerg Roedel
2018-04-23 15:47 ` [PATCH 20/37] x86/pgtable: Move two more functions from pgtable_64.h " Joerg Roedel
2018-04-23 15:47 ` [PATCH 21/37] x86/mm/pae: Populate valid user PGD entries Joerg Roedel
2018-04-23 15:47 ` [PATCH 22/37] x86/mm/pae: Populate the user page-table with user pgd's Joerg Roedel
2018-04-23 15:47 ` [PATCH 23/37] x86/mm/legacy: " Joerg Roedel
2018-04-23 15:47 ` [PATCH 24/37] x86/mm/pti: Add an overflow check to pti_clone_pmds() Joerg Roedel
2018-04-23 15:47 ` [PATCH 25/37] x86/mm/pti: Define X86_CR3_PTI_PCID_USER_BIT on x86_32 Joerg Roedel
2018-04-23 15:47 ` [PATCH 26/37] x86/mm/pti: Clone CPU_ENTRY_AREA on PMD level " Joerg Roedel
2018-04-23 15:47 ` [PATCH 27/37] x86/mm/pti: Keep permissions when cloning kernel text in pti_clone_kernel_text() Joerg Roedel
2018-04-23 17:06 ` Kees Cook
2018-04-23 18:00 ` Joerg Roedel
2018-04-23 15:47 ` [PATCH 28/37] x86/mm/pti: Map kernel-text to user-space on 32 bit kernels Joerg Roedel
2018-04-23 17:09 ` Kees Cook
2018-04-23 17:48 ` Joerg Roedel
2018-04-23 15:47 ` [PATCH 29/37] x86/mm/dump_pagetables: Define INIT_PGD Joerg Roedel
2018-04-23 15:47 ` [PATCH 30/37] x86/pgtable/pae: Use separate kernel PMDs for user page-table Joerg Roedel
2018-04-23 15:47 ` [PATCH 31/37] x86/ldt: Reserve address-space range on 32 bit for the LDT Joerg Roedel
2018-04-23 15:47 ` [PATCH 32/37] x86/ldt: Define LDT_END_ADDR Joerg Roedel
2018-04-23 15:47 ` [PATCH 33/37] x86/ldt: Split out sanity check in map_ldt_struct() Joerg Roedel
2018-04-23 15:47 ` [PATCH 34/37] x86/ldt: Enable LDT user-mapping for PAE Joerg Roedel
2018-04-23 15:47 ` [PATCH 35/37] x86/pti: Allow CONFIG_PAGE_TABLE_ISOLATION for x86_32 Joerg Roedel
2018-04-23 15:47 ` [PATCH 36/37] x86/mm/pti: Add Warning when booting on a PCID capable CPU Joerg Roedel
2018-04-23 15:47 ` [PATCH 37/37] x86/entry/32: Add debug code to check entry/exit cr3 Joerg Roedel
2018-04-23 16:45 ` [PATCH 00/37 v6] PTI support for x86-32 Linus Torvalds
2018-04-23 17:45 ` Joerg Roedel
2018-04-23 17:49 ` Linus Torvalds
2018-04-23 19:38 ` Pavel Machek
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