* [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings
2018-06-28 10:45 [PATCH v3 0/5] Add system timer driver for Mediatek SoCs Stanley Chu
@ 2018-06-28 10:45 ` Stanley Chu
2018-06-28 14:08 ` Daniel Lezcano
2018-06-28 10:45 ` [PATCH v3 2/5] clocksource/drivers/timer-mediatek: Rename mtk_timer to timer-mediatek Stanley Chu
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Stanley Chu @ 2018-06-28 10:45 UTC (permalink / raw)
To: Matthias Brugger, Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream, Stanley Chu
This patch fixes bindings of existed "General Purpose Timer",
and then add bindings of new "System Timer" on Mediatek SoCs.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
.../bindings/timer/mediatek,mtk-timer.txt | 38 ++++++++++++++++----
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index b1fe7e9..d42247b 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -1,5 +1,14 @@
-Mediatek MT6577, MT6572 and MT6589 Timers
----------------------------------------
+Mediatek Timers
+---------------
+
+Mediatek SoCs have two different timers on different platforms,
+- GPT (General Purpose Timer)
+- SYST (System Timer)
+
+Please bind correct timers in each platforms.
+
+
+** General Purpose Timer (GPT)
Required properties:
- compatible should contain:
@@ -11,9 +20,8 @@ Required properties:
* "mediatek,mt8135-timer" for MT8135 compatible timers
* "mediatek,mt8173-timer" for MT8173 compatible timers
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers
-- reg: Should contain location and length for timers register.
-- clocks: Clocks driving the timer hardware. This list should include two
- clocks. The order is system clock and as second clock the RTC clock.
+- reg: Should contain location and length for GPT register.
+- clocks: GPT is drived by system clock.
Examples:
@@ -21,5 +29,23 @@ Examples:
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&system_clk>, <&rtc_clk>;
+ clocks = <&system_clk>;
+ };
+
+
+** System Timer (SYST)
+
+Required properties:
+- compatible: Should contain
+ * "mediatek,mt6765-systimer" for MT6765 compatible timers
+- reg: Should contain the location and length for system timer registers.
+- clocks: System timer is drived by system clock.
+
+Examples:
+
+ systimer@10017000 {
+ compatible = "mediatek,mt6765-systimer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&system_clk>;
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings
2018-06-28 10:45 ` [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings Stanley Chu
@ 2018-06-28 14:08 ` Daniel Lezcano
2018-06-29 0:15 ` Stanley Chu
0 siblings, 1 reply; 12+ messages in thread
From: Daniel Lezcano @ 2018-06-28 14:08 UTC (permalink / raw)
To: Stanley Chu, Matthias Brugger, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream
On 28/06/2018 12:45, Stanley Chu wrote:
> This patch fixes bindings of existed "General Purpose Timer",
> and then add bindings of new "System Timer" on Mediatek SoCs.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
> .../bindings/timer/mediatek,mtk-timer.txt | 38 ++++++++++++++++----
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> index b1fe7e9..d42247b 100644
> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> @@ -1,5 +1,14 @@
> -Mediatek MT6577, MT6572 and MT6589 Timers
> ----------------------------------------
> +Mediatek Timers
> +---------------
> +
> +Mediatek SoCs have two different timers on different platforms,
> +- GPT (General Purpose Timer)
> +- SYST (System Timer)
> +
> +Please bind correct timers in each platforms.
> +
> +
> +** General Purpose Timer (GPT)
>
> Required properties:
> - compatible should contain:
> @@ -11,9 +20,8 @@ Required properties:
> * "mediatek,mt8135-timer" for MT8135 compatible timers
> * "mediatek,mt8173-timer" for MT8173 compatible timers
> * "mediatek,mt6577-timer" for MT6577 and all above compatible timers
> -- reg: Should contain location and length for timers register.
> -- clocks: Clocks driving the timer hardware. This list should include two
> - clocks. The order is system clock and as second clock the RTC clock.
> +- reg: Should contain location and length for GPT register.
> +- clocks: GPT is drived by system clock.
>
> Examples:
>
> @@ -21,5 +29,23 @@ Examples:
> compatible = "mediatek,mt6577-timer";
> reg = <0x10008000 0x80>;
> interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&system_clk>, <&rtc_clk>;
> + clocks = <&system_clk>;
> + };
> +
> +
> +** System Timer (SYST)
> +
> +Required properties:
> +- compatible: Should contain
> + * "mediatek,mt6765-systimer" for MT6765 compatible timers
> +- reg: Should contain the location and length for system timer registers.
> +- clocks: System timer is drived by system clock.
> +
> +Examples:
> +
> + systimer@10017000 {
> + compatible = "mediatek,mt6765-systimer";
why not "mediatek,mt6765-timer" ? for consistency.
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&system_clk>;
> };
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings
2018-06-28 14:08 ` Daniel Lezcano
@ 2018-06-29 0:15 ` Stanley Chu
0 siblings, 0 replies; 12+ messages in thread
From: Stanley Chu @ 2018-06-29 0:15 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Matthias Brugger, Thomas Gleixner, Rob Herring, linux-kernel,
linux-mediatek, devicetree, wsd_upstream
On Thu, 2018-06-28 at 16:08 +0200, Daniel Lezcano wrote:
> > +** System Timer (SYST)
> > +
> > +Required properties:
> > +- compatible: Should contain
> > + * "mediatek,mt6765-systimer" for MT6765 compatible timers
> > +- reg: Should contain the location and length for system timer registers.
> > +- clocks: System timer is drived by system clock.
> > +
> > +Examples:
> > +
> > + systimer@10017000 {
> > + compatible = "mediatek,mt6765-systimer";
>
> why not "mediatek,mt6765-timer" ? for consistency.
>
Hi Daniel,
The original thought is to remind user to notice that different timer
will be used.
However it looks more clean if we use consistent name.
Will fix it in v4.
> > + reg = <0 0x10017000 0 0x1000>;
> > + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&system_clk>;
> > };
> >
>
>
Thanks.
Stanley Chu
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/5] clocksource/drivers/timer-mediatek: Rename mtk_timer to timer-mediatek
2018-06-28 10:45 [PATCH v3 0/5] Add system timer driver for Mediatek SoCs Stanley Chu
2018-06-28 10:45 ` [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings Stanley Chu
@ 2018-06-28 10:45 ` Stanley Chu
2018-06-28 10:45 ` [PATCH v3 3/5] clocksource/drivers/timer-mediatek: Rename function prefix Stanley Chu
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Stanley Chu @ 2018-06-28 10:45 UTC (permalink / raw)
To: Matthias Brugger, Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream, Stanley Chu
Rename mtk_timer to timer-mediatek to apply new naming convention
in clocksource folder.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/clocksource/Makefile | 2 +-
drivers/clocksource/mtk_timer.c | 268 ----------------------------------
drivers/clocksource/timer-mediatek.c | 268 ++++++++++++++++++++++++++++++++++
3 files changed, 269 insertions(+), 269 deletions(-)
delete mode 100644 drivers/clocksource/mtk_timer.c
create mode 100644 drivers/clocksource/timer-mediatek.c
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 00caf37..c070cc7 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -49,7 +49,7 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o
obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
-obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
+obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
deleted file mode 100644
index f9b724f..0000000
--- a/drivers/clocksource/mtk_timer.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Mediatek SoCs General-Purpose Timer handling.
- *
- * Copyright (C) 2014 Matthias Brugger
- *
- * Matthias Brugger <matthias.bgg@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqreturn.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/sched_clock.h>
-#include <linux/slab.h>
-
-#define GPT_IRQ_EN_REG 0x00
-#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
-#define GPT_IRQ_ACK_REG 0x08
-#define GPT_IRQ_ACK(val) BIT((val) - 1)
-
-#define TIMER_CTRL_REG(val) (0x10 * (val))
-#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
-#define TIMER_CTRL_OP_ONESHOT (0)
-#define TIMER_CTRL_OP_REPEAT (1)
-#define TIMER_CTRL_OP_FREERUN (3)
-#define TIMER_CTRL_CLEAR (2)
-#define TIMER_CTRL_ENABLE (1)
-#define TIMER_CTRL_DISABLE (0)
-
-#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
-#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
-#define TIMER_CLK_SRC_SYS13M (0)
-#define TIMER_CLK_SRC_RTC32K (1)
-#define TIMER_CLK_DIV1 (0x0)
-#define TIMER_CLK_DIV2 (0x1)
-
-#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
-#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
-
-#define GPT_CLK_EVT 1
-#define GPT_CLK_SRC 2
-
-struct mtk_clock_event_device {
- void __iomem *gpt_base;
- u32 ticks_per_jiffy;
- struct clock_event_device dev;
-};
-
-static void __iomem *gpt_sched_reg __read_mostly;
-
-static u64 notrace mtk_read_sched_clock(void)
-{
- return readl_relaxed(gpt_sched_reg);
-}
-
-static inline struct mtk_clock_event_device *to_mtk_clk(
- struct clock_event_device *c)
-{
- return container_of(c, struct mtk_clock_event_device, dev);
-}
-
-static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
-{
- u32 val;
-
- val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
- writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
- TIMER_CTRL_REG(timer));
-}
-
-static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
- unsigned long delay, u8 timer)
-{
- writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
-}
-
-static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
- bool periodic, u8 timer)
-{
- u32 val;
-
- /* Acknowledge interrupt */
- writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
-
- val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
-
- /* Clear 2 bit timer operation mode field */
- val &= ~TIMER_CTRL_OP(0x3);
-
- if (periodic)
- val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
- else
- val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
-
- writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
- evt->gpt_base + TIMER_CTRL_REG(timer));
-}
-
-static int mtk_clkevt_shutdown(struct clock_event_device *clk)
-{
- mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
- return 0;
-}
-
-static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
-{
- struct mtk_clock_event_device *evt = to_mtk_clk(clk);
-
- mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
- mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
- return 0;
-}
-
-static int mtk_clkevt_next_event(unsigned long event,
- struct clock_event_device *clk)
-{
- struct mtk_clock_event_device *evt = to_mtk_clk(clk);
-
- mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
- mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
-
- return 0;
-}
-
-static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
-{
- struct mtk_clock_event_device *evt = dev_id;
-
- /* Acknowledge timer0 irq */
- writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
- evt->dev.event_handler(&evt->dev);
-
- return IRQ_HANDLED;
-}
-
-static void
-__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
-{
- writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
-
- writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
- evt->gpt_base + TIMER_CLK_REG(timer));
-
- writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
-
- writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
-}
-
-static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
-{
- u32 val;
-
- /* Disable all interrupts */
- writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
-
- /* Acknowledge all spurious pending interrupts */
- writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
-
- val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
- writel(val | GPT_IRQ_ENABLE(timer),
- evt->gpt_base + GPT_IRQ_EN_REG);
-}
-
-static int __init mtk_timer_init(struct device_node *node)
-{
- struct mtk_clock_event_device *evt;
- struct resource res;
- unsigned long rate = 0;
- struct clk *clk;
-
- evt = kzalloc(sizeof(*evt), GFP_KERNEL);
- if (!evt)
- return -ENOMEM;
-
- evt->dev.name = "mtk_tick";
- evt->dev.rating = 300;
- evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
- evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
- evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
- evt->dev.tick_resume = mtk_clkevt_shutdown;
- evt->dev.set_next_event = mtk_clkevt_next_event;
- evt->dev.cpumask = cpu_possible_mask;
-
- evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
- if (IS_ERR(evt->gpt_base)) {
- pr_err("Can't get resource\n");
- goto err_kzalloc;
- }
-
- evt->dev.irq = irq_of_parse_and_map(node, 0);
- if (evt->dev.irq <= 0) {
- pr_err("Can't parse IRQ\n");
- goto err_mem;
- }
-
- clk = of_clk_get(node, 0);
- if (IS_ERR(clk)) {
- pr_err("Can't get timer clock\n");
- goto err_irq;
- }
-
- if (clk_prepare_enable(clk)) {
- pr_err("Can't prepare clock\n");
- goto err_clk_put;
- }
- rate = clk_get_rate(clk);
-
- if (request_irq(evt->dev.irq, mtk_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
- pr_err("failed to setup irq %d\n", evt->dev.irq);
- goto err_clk_disable;
- }
-
- evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-
- /* Configure clock source */
- mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
- clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
- node->name, rate, 300, 32, clocksource_mmio_readl_up);
- gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
- sched_clock_register(mtk_read_sched_clock, 32, rate);
-
- /* Configure clock event */
- mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
- clockevents_config_and_register(&evt->dev, rate, 0x3,
- 0xffffffff);
-
- mtk_timer_enable_irq(evt, GPT_CLK_EVT);
-
- return 0;
-
-err_clk_disable:
- clk_disable_unprepare(clk);
-err_clk_put:
- clk_put(clk);
-err_irq:
- irq_dispose_mapping(evt->dev.irq);
-err_mem:
- iounmap(evt->gpt_base);
- of_address_to_resource(node, 0, &res);
- release_mem_region(res.start, resource_size(&res));
-err_kzalloc:
- kfree(evt);
-
- return -EINVAL;
-}
-TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
new file mode 100644
index 0000000..f9b724f
--- /dev/null
+++ b/drivers/clocksource/timer-mediatek.c
@@ -0,0 +1,268 @@
+/*
+ * Mediatek SoCs General-Purpose Timer handling.
+ *
+ * Copyright (C) 2014 Matthias Brugger
+ *
+ * Matthias Brugger <matthias.bgg@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+
+#define GPT_IRQ_EN_REG 0x00
+#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
+#define GPT_IRQ_ACK_REG 0x08
+#define GPT_IRQ_ACK(val) BIT((val) - 1)
+
+#define TIMER_CTRL_REG(val) (0x10 * (val))
+#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
+#define TIMER_CTRL_OP_ONESHOT (0)
+#define TIMER_CTRL_OP_REPEAT (1)
+#define TIMER_CTRL_OP_FREERUN (3)
+#define TIMER_CTRL_CLEAR (2)
+#define TIMER_CTRL_ENABLE (1)
+#define TIMER_CTRL_DISABLE (0)
+
+#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
+#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
+#define TIMER_CLK_SRC_SYS13M (0)
+#define TIMER_CLK_SRC_RTC32K (1)
+#define TIMER_CLK_DIV1 (0x0)
+#define TIMER_CLK_DIV2 (0x1)
+
+#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
+#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
+
+#define GPT_CLK_EVT 1
+#define GPT_CLK_SRC 2
+
+struct mtk_clock_event_device {
+ void __iomem *gpt_base;
+ u32 ticks_per_jiffy;
+ struct clock_event_device dev;
+};
+
+static void __iomem *gpt_sched_reg __read_mostly;
+
+static u64 notrace mtk_read_sched_clock(void)
+{
+ return readl_relaxed(gpt_sched_reg);
+}
+
+static inline struct mtk_clock_event_device *to_mtk_clk(
+ struct clock_event_device *c)
+{
+ return container_of(c, struct mtk_clock_event_device, dev);
+}
+
+static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+{
+ u32 val;
+
+ val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+ writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
+ TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
+ unsigned long delay, u8 timer)
+{
+ writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
+ bool periodic, u8 timer)
+{
+ u32 val;
+
+ /* Acknowledge interrupt */
+ writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
+
+ val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+
+ /* Clear 2 bit timer operation mode field */
+ val &= ~TIMER_CTRL_OP(0x3);
+
+ if (periodic)
+ val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
+ else
+ val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
+
+ writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
+ evt->gpt_base + TIMER_CTRL_REG(timer));
+}
+
+static int mtk_clkevt_shutdown(struct clock_event_device *clk)
+{
+ mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
+ return 0;
+}
+
+static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
+{
+ struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+ mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+ mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
+ mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
+ return 0;
+}
+
+static int mtk_clkevt_next_event(unsigned long event,
+ struct clock_event_device *clk)
+{
+ struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+ mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+ mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
+ mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+
+ return 0;
+}
+
+static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
+{
+ struct mtk_clock_event_device *evt = dev_id;
+
+ /* Acknowledge timer0 irq */
+ writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
+ evt->dev.event_handler(&evt->dev);
+
+ return IRQ_HANDLED;
+}
+
+static void
+__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
+{
+ writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
+ evt->gpt_base + TIMER_CTRL_REG(timer));
+
+ writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
+ evt->gpt_base + TIMER_CLK_REG(timer));
+
+ writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
+
+ writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
+ evt->gpt_base + TIMER_CTRL_REG(timer));
+}
+
+static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
+{
+ u32 val;
+
+ /* Disable all interrupts */
+ writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
+
+ /* Acknowledge all spurious pending interrupts */
+ writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
+
+ val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
+ writel(val | GPT_IRQ_ENABLE(timer),
+ evt->gpt_base + GPT_IRQ_EN_REG);
+}
+
+static int __init mtk_timer_init(struct device_node *node)
+{
+ struct mtk_clock_event_device *evt;
+ struct resource res;
+ unsigned long rate = 0;
+ struct clk *clk;
+
+ evt = kzalloc(sizeof(*evt), GFP_KERNEL);
+ if (!evt)
+ return -ENOMEM;
+
+ evt->dev.name = "mtk_tick";
+ evt->dev.rating = 300;
+ evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+ evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
+ evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
+ evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
+ evt->dev.tick_resume = mtk_clkevt_shutdown;
+ evt->dev.set_next_event = mtk_clkevt_next_event;
+ evt->dev.cpumask = cpu_possible_mask;
+
+ evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
+ if (IS_ERR(evt->gpt_base)) {
+ pr_err("Can't get resource\n");
+ goto err_kzalloc;
+ }
+
+ evt->dev.irq = irq_of_parse_and_map(node, 0);
+ if (evt->dev.irq <= 0) {
+ pr_err("Can't parse IRQ\n");
+ goto err_mem;
+ }
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk)) {
+ pr_err("Can't get timer clock\n");
+ goto err_irq;
+ }
+
+ if (clk_prepare_enable(clk)) {
+ pr_err("Can't prepare clock\n");
+ goto err_clk_put;
+ }
+ rate = clk_get_rate(clk);
+
+ if (request_irq(evt->dev.irq, mtk_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
+ pr_err("failed to setup irq %d\n", evt->dev.irq);
+ goto err_clk_disable;
+ }
+
+ evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
+
+ /* Configure clock source */
+ mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
+ clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
+ node->name, rate, 300, 32, clocksource_mmio_readl_up);
+ gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
+ sched_clock_register(mtk_read_sched_clock, 32, rate);
+
+ /* Configure clock event */
+ mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ clockevents_config_and_register(&evt->dev, rate, 0x3,
+ 0xffffffff);
+
+ mtk_timer_enable_irq(evt, GPT_CLK_EVT);
+
+ return 0;
+
+err_clk_disable:
+ clk_disable_unprepare(clk);
+err_clk_put:
+ clk_put(clk);
+err_irq:
+ irq_dispose_mapping(evt->dev.irq);
+err_mem:
+ iounmap(evt->gpt_base);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+err_kzalloc:
+ kfree(evt);
+
+ return -EINVAL;
+}
+TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 3/5] clocksource/drivers/timer-mediatek: Rename function prefix
2018-06-28 10:45 [PATCH v3 0/5] Add system timer driver for Mediatek SoCs Stanley Chu
2018-06-28 10:45 ` [PATCH v3 1/5] clocksource/drivers/timer-mediatek: Add system timer bindings Stanley Chu
2018-06-28 10:45 ` [PATCH v3 2/5] clocksource/drivers/timer-mediatek: Rename mtk_timer to timer-mediatek Stanley Chu
@ 2018-06-28 10:45 ` Stanley Chu
2018-06-28 10:45 ` [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of Stanley Chu
2018-06-28 10:45 ` [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer Stanley Chu
4 siblings, 0 replies; 12+ messages in thread
From: Stanley Chu @ 2018-06-28 10:45 UTC (permalink / raw)
To: Matthias Brugger, Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream, Stanley Chu
Add prefix to specify the name of supported timer hardware:
"General Purpose Timer (GPT)".
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/clocksource/timer-mediatek.c | 60 +++++++++++++++++-----------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
index f9b724f..ff284f2 100644
--- a/drivers/clocksource/timer-mediatek.c
+++ b/drivers/clocksource/timer-mediatek.c
@@ -64,7 +64,7 @@ struct mtk_clock_event_device {
static void __iomem *gpt_sched_reg __read_mostly;
-static u64 notrace mtk_read_sched_clock(void)
+static u64 notrace mtk_gpt_read_sched_clock(void)
{
return readl_relaxed(gpt_sched_reg);
}
@@ -75,7 +75,7 @@ static inline struct mtk_clock_event_device *to_mtk_clk(
return container_of(c, struct mtk_clock_event_device, dev);
}
-static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
{
u32 val;
@@ -84,13 +84,13 @@ static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
TIMER_CTRL_REG(timer));
}
-static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
+static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt,
unsigned long delay, u8 timer)
{
writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
}
-static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
+static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt,
bool periodic, u8 timer)
{
u32 val;
@@ -112,35 +112,35 @@ static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
evt->gpt_base + TIMER_CTRL_REG(timer));
}
-static int mtk_clkevt_shutdown(struct clock_event_device *clk)
+static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
{
- mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
return 0;
}
-static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
+static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
{
struct mtk_clock_event_device *evt = to_mtk_clk(clk);
- mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
- mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_start(evt, true, GPT_CLK_EVT);
return 0;
}
-static int mtk_clkevt_next_event(unsigned long event,
+static int mtk_gpt_clkevt_next_event(unsigned long event,
struct clock_event_device *clk)
{
struct mtk_clock_event_device *evt = to_mtk_clk(clk);
- mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
- mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_setup(evt, event, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_start(evt, false, GPT_CLK_EVT);
return 0;
}
-static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
{
struct mtk_clock_event_device *evt = dev_id;
@@ -152,7 +152,7 @@ static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
}
static void
-__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
+__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
{
writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
evt->gpt_base + TIMER_CTRL_REG(timer));
@@ -166,7 +166,7 @@ __init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
evt->gpt_base + TIMER_CTRL_REG(timer));
}
-static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
+static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
{
u32 val;
@@ -181,7 +181,7 @@ static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
evt->gpt_base + GPT_IRQ_EN_REG);
}
-static int __init mtk_timer_init(struct device_node *node)
+static int __init mtk_gpt_init(struct device_node *node)
{
struct mtk_clock_event_device *evt;
struct resource res;
@@ -195,14 +195,14 @@ static int __init mtk_timer_init(struct device_node *node)
evt->dev.name = "mtk_tick";
evt->dev.rating = 300;
evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
- evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
- evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
- evt->dev.tick_resume = mtk_clkevt_shutdown;
- evt->dev.set_next_event = mtk_clkevt_next_event;
+ evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown;
+ evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic;
+ evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown;
+ evt->dev.tick_resume = mtk_gpt_clkevt_shutdown;
+ evt->dev.set_next_event = mtk_gpt_clkevt_next_event;
evt->dev.cpumask = cpu_possible_mask;
- evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
+ evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt");
if (IS_ERR(evt->gpt_base)) {
pr_err("Can't get resource\n");
goto err_kzalloc;
@@ -226,7 +226,7 @@ static int __init mtk_timer_init(struct device_node *node)
}
rate = clk_get_rate(clk);
- if (request_irq(evt->dev.irq, mtk_timer_interrupt,
+ if (request_irq(evt->dev.irq, mtk_gpt_interrupt,
IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
pr_err("failed to setup irq %d\n", evt->dev.irq);
goto err_clk_disable;
@@ -235,18 +235,18 @@ static int __init mtk_timer_init(struct device_node *node)
evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
/* Configure clock source */
- mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
+ mtk_gpt_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
node->name, rate, 300, 32, clocksource_mmio_readl_up);
gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
- sched_clock_register(mtk_read_sched_clock, 32, rate);
+ sched_clock_register(mtk_gpt_read_sched_clock, 32, rate);
/* Configure clock event */
- mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ mtk_gpt_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
clockevents_config_and_register(&evt->dev, rate, 0x3,
0xffffffff);
- mtk_timer_enable_irq(evt, GPT_CLK_EVT);
+ mtk_gpt_enable_irq(evt, GPT_CLK_EVT);
return 0;
@@ -265,4 +265,4 @@ static int __init mtk_timer_init(struct device_node *node)
return -EINVAL;
}
-TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
+TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of
2018-06-28 10:45 [PATCH v3 0/5] Add system timer driver for Mediatek SoCs Stanley Chu
` (2 preceding siblings ...)
2018-06-28 10:45 ` [PATCH v3 3/5] clocksource/drivers/timer-mediatek: Rename function prefix Stanley Chu
@ 2018-06-28 10:45 ` Stanley Chu
2018-06-28 14:03 ` Daniel Lezcano
2018-06-28 10:45 ` [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer Stanley Chu
4 siblings, 1 reply; 12+ messages in thread
From: Stanley Chu @ 2018-06-28 10:45 UTC (permalink / raw)
To: Matthias Brugger, Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream, Stanley Chu
Convert the driver to use the timer_of helpers.
This allows to remove custom proprietary structure,
factors out and simplifies the code.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/clocksource/timer-mediatek.c | 222 ++++++++++++++++------------------
1 file changed, 104 insertions(+), 118 deletions(-)
diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
index ff284f2..d94d8e1 100644
--- a/drivers/clocksource/timer-mediatek.c
+++ b/drivers/clocksource/timer-mediatek.c
@@ -18,16 +18,13 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/clk.h>
#include <linux/clockchips.h>
+#include <linux/clocksource.h>
#include <linux/interrupt.h>
-#include <linux/irq.h>
#include <linux/irqreturn.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
+#include "timer-of.h"
#define GPT_IRQ_EN_REG 0x00
#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
@@ -56,49 +53,57 @@
#define GPT_CLK_EVT 1
#define GPT_CLK_SRC 2
-struct mtk_clock_event_device {
- void __iomem *gpt_base;
- u32 ticks_per_jiffy;
- struct clock_event_device dev;
+struct mtk_timer_private {
+ unsigned long ticks_per_jiffy;
};
static void __iomem *gpt_sched_reg __read_mostly;
-static u64 notrace mtk_gpt_read_sched_clock(void)
+static void mtk_timer_of_priv_set(struct timer_of *to, u32 ticks_per_jiffy)
{
- return readl_relaxed(gpt_sched_reg);
+ struct mtk_timer_private *pd = to->private_data;
+
+ pd->ticks_per_jiffy = ticks_per_jiffy;
+}
+
+static void mtk_timer_of_priv_get(struct timer_of *to,
+ unsigned long *ticks_per_jiffy)
+{
+ struct mtk_timer_private *pd = to->private_data;
+
+ if (ticks_per_jiffy)
+ *ticks_per_jiffy = pd->ticks_per_jiffy;
}
-static inline struct mtk_clock_event_device *to_mtk_clk(
- struct clock_event_device *c)
+static u64 notrace mtk_gpt_read_sched_clock(void)
{
- return container_of(c, struct mtk_clock_event_device, dev);
+ return readl_relaxed(gpt_sched_reg);
}
-static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
{
u32 val;
- val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
- writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
- TIMER_CTRL_REG(timer));
+ val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer));
+ writel(val & ~TIMER_CTRL_ENABLE, timer_of_base(to) +
+ TIMER_CTRL_REG(timer));
}
-static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt,
- unsigned long delay, u8 timer)
+static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
+ unsigned long delay, u8 timer)
{
- writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
+ writel(delay, timer_of_base(to) + TIMER_CMP_REG(timer));
}
-static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt,
- bool periodic, u8 timer)
+static void mtk_gpt_clkevt_time_start(struct timer_of *to,
+ bool periodic, u8 timer)
{
u32 val;
/* Acknowledge interrupt */
- writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
+ writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
- val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+ val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer));
/* Clear 2 bit timer operation mode field */
val &= ~TIMER_CTRL_OP(0x3);
@@ -109,160 +114,141 @@ static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt,
val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
- evt->gpt_base + TIMER_CTRL_REG(timer));
+ timer_of_base(to) + TIMER_CTRL_REG(timer));
}
static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
{
- mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to_timer_of(clk), GPT_CLK_EVT);
return 0;
}
static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
{
- struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+ struct timer_of *to = to_timer_of(clk);
+ unsigned long ticks_per_jiffy;
- mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_start(evt, true, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT);
+ mtk_timer_of_priv_get(to, &ticks_per_jiffy);
+ mtk_gpt_clkevt_time_setup(to, ticks_per_jiffy, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_start(to, true, GPT_CLK_EVT);
return 0;
}
static int mtk_gpt_clkevt_next_event(unsigned long event,
- struct clock_event_device *clk)
+ struct clock_event_device *clk)
{
- struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+ struct timer_of *to = to_timer_of(clk);
- mtk_gpt_clkevt_time_stop(evt, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_setup(evt, event, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_start(evt, false, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_setup(to, event, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_start(to, false, GPT_CLK_EVT);
return 0;
}
static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
{
- struct mtk_clock_event_device *evt = dev_id;
+ struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
+ struct timer_of *to = to_timer_of(clkevt);
/* Acknowledge timer0 irq */
- writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
- evt->dev.event_handler(&evt->dev);
+ writel(GPT_IRQ_ACK(GPT_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
+ clkevt->event_handler(clkevt);
return IRQ_HANDLED;
}
static void
-__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
+__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
{
writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
+ timer_of_base(to) + TIMER_CTRL_REG(timer));
writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
- evt->gpt_base + TIMER_CLK_REG(timer));
+ timer_of_base(to) + TIMER_CLK_REG(timer));
- writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
+ writel(0x0, timer_of_base(to) + TIMER_CMP_REG(timer));
writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
- evt->gpt_base + TIMER_CTRL_REG(timer));
+ timer_of_base(to) + TIMER_CTRL_REG(timer));
}
-static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
+static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
{
u32 val;
/* Disable all interrupts */
- writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
+ writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
/* Acknowledge all spurious pending interrupts */
- writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
+ writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
- val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
+ val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
writel(val | GPT_IRQ_ENABLE(timer),
- evt->gpt_base + GPT_IRQ_EN_REG);
+ timer_of_base(to) + GPT_IRQ_EN_REG);
}
-static int __init mtk_gpt_init(struct device_node *node)
-{
- struct mtk_clock_event_device *evt;
- struct resource res;
- unsigned long rate = 0;
- struct clk *clk;
-
- evt = kzalloc(sizeof(*evt), GFP_KERNEL);
- if (!evt)
- return -ENOMEM;
-
- evt->dev.name = "mtk_tick";
- evt->dev.rating = 300;
- evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown;
- evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic;
- evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown;
- evt->dev.tick_resume = mtk_gpt_clkevt_shutdown;
- evt->dev.set_next_event = mtk_gpt_clkevt_next_event;
- evt->dev.cpumask = cpu_possible_mask;
-
- evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt");
- if (IS_ERR(evt->gpt_base)) {
- pr_err("Can't get resource\n");
- goto err_kzalloc;
- }
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
- evt->dev.irq = irq_of_parse_and_map(node, 0);
- if (evt->dev.irq <= 0) {
- pr_err("Can't parse IRQ\n");
- goto err_mem;
- }
-
- clk = of_clk_get(node, 0);
- if (IS_ERR(clk)) {
- pr_err("Can't get timer clock\n");
- goto err_irq;
- }
+ .clkevt = {
+ .name = "mtk-clkevt",
+ .rating = 300,
+ .cpumask = cpu_possible_mask,
+ },
- if (clk_prepare_enable(clk)) {
- pr_err("Can't prepare clock\n");
- goto err_clk_put;
- }
- rate = clk_get_rate(clk);
+ .of_irq = {
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
- if (request_irq(evt->dev.irq, mtk_gpt_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
- pr_err("failed to setup irq %d\n", evt->dev.irq);
- goto err_clk_disable;
+static int __init mtk_gpt_init(struct device_node *node)
+{
+ int ret;
+
+ to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+ to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
+ to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
+ to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
+ to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
+ to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
+ to.of_irq.handler = mtk_gpt_interrupt;
+
+ ret = timer_of_init(node, &to);
+ if (ret)
+ goto err;
+
+ to.private_data = kzalloc(sizeof(struct mtk_timer_private),
+ GFP_KERNEL);
+
+ if (!to.private_data) {
+ ret = -ENOMEM;
+ goto deinit;
}
- evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
+ mtk_timer_of_priv_set(&to, DIV_ROUND_UP(timer_of_rate(&to), HZ));
/* Configure clock source */
- mtk_gpt_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
- clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
- node->name, rate, 300, 32, clocksource_mmio_readl_up);
- gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
- sched_clock_register(mtk_gpt_read_sched_clock, 32, rate);
+ mtk_gpt_setup(&to, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
+ clocksource_mmio_init(timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC),
+ node->name, timer_of_rate(&to), 300, 32,
+ clocksource_mmio_readl_up);
+ gpt_sched_reg = timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC);
+ sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
/* Configure clock event */
- mtk_gpt_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
- clockevents_config_and_register(&evt->dev, rate, 0x3,
+ mtk_gpt_setup(&to, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 0x3,
0xffffffff);
- mtk_gpt_enable_irq(evt, GPT_CLK_EVT);
+ mtk_gpt_enable_irq(&to, GPT_CLK_EVT);
return 0;
-err_clk_disable:
- clk_disable_unprepare(clk);
-err_clk_put:
- clk_put(clk);
-err_irq:
- irq_dispose_mapping(evt->dev.irq);
-err_mem:
- iounmap(evt->gpt_base);
- of_address_to_resource(node, 0, &res);
- release_mem_region(res.start, resource_size(&res));
-err_kzalloc:
- kfree(evt);
-
- return -EINVAL;
+deinit:
+ timer_of_cleanup(&to);
+err:
+ return ret;
}
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of
2018-06-28 10:45 ` [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of Stanley Chu
@ 2018-06-28 14:03 ` Daniel Lezcano
2018-06-29 0:10 ` Stanley Chu
0 siblings, 1 reply; 12+ messages in thread
From: Daniel Lezcano @ 2018-06-28 14:03 UTC (permalink / raw)
To: Stanley Chu, Matthias Brugger, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream
On 28/06/2018 12:45, Stanley Chu wrote:
> Convert the driver to use the timer_of helpers.
> This allows to remove custom proprietary structure,
> factors out and simplifies the code.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
> drivers/clocksource/timer-mediatek.c | 222 ++++++++++++++++------------------
> 1 file changed, 104 insertions(+), 118 deletions(-)
>
> diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
> index ff284f2..d94d8e1 100644
> --- a/drivers/clocksource/timer-mediatek.c
> +++ b/drivers/clocksource/timer-mediatek.c
> @@ -18,16 +18,13 @@
>
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> -#include <linux/clk.h>
> #include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> #include <linux/interrupt.h>
> -#include <linux/irq.h>
> #include <linux/irqreturn.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> -#include <linux/of_irq.h>
> #include <linux/sched_clock.h>
> #include <linux/slab.h>
> +#include "timer-of.h"
>
> #define GPT_IRQ_EN_REG 0x00
> #define GPT_IRQ_ENABLE(val) BIT((val) - 1)
> @@ -56,49 +53,57 @@
> #define GPT_CLK_EVT 1
> #define GPT_CLK_SRC 2
>
> -struct mtk_clock_event_device {
> - void __iomem *gpt_base;
> - u32 ticks_per_jiffy;
> - struct clock_event_device dev;
> +struct mtk_timer_private {
> + unsigned long ticks_per_jiffy;
> };
This private structure is not needed. There is timer_of_clk->period
cf.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clocksource/timer-of.c#n144
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of
2018-06-28 14:03 ` Daniel Lezcano
@ 2018-06-29 0:10 ` Stanley Chu
0 siblings, 0 replies; 12+ messages in thread
From: Stanley Chu @ 2018-06-29 0:10 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Matthias Brugger, Thomas Gleixner, Rob Herring, linux-kernel,
linux-mediatek, devicetree, wsd_upstream
On Thu, 2018-06-28 at 16:03 +0200, Daniel Lezcano wrote:
> >
> > -struct mtk_clock_event_device {
> > - void __iomem *gpt_base;
> > - u32 ticks_per_jiffy;
> > - struct clock_event_device dev;
> > +struct mtk_timer_private {
> > + unsigned long ticks_per_jiffy;
> > };
>
> This private structure is not needed. There is timer_of_clk->period
>
> cf.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clocksource/timer-of.c#n144
>
>
Hi Daniel,
Thanks for remind:)
Will fix it in v4.
Thanks.
Stanley Chu
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer
2018-06-28 10:45 [PATCH v3 0/5] Add system timer driver for Mediatek SoCs Stanley Chu
` (3 preceding siblings ...)
2018-06-28 10:45 ` [PATCH v3 4/5] clocksource/drivers/timer-mediatek: Convert the driver to timer-of Stanley Chu
@ 2018-06-28 10:45 ` Stanley Chu
2018-06-28 14:08 ` Daniel Lezcano
4 siblings, 1 reply; 12+ messages in thread
From: Stanley Chu @ 2018-06-28 10:45 UTC (permalink / raw)
To: Matthias Brugger, Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream, Stanley Chu
This patch adds a new "System Timer" on the Mediatek SoCs.
The System Timer is introduced as an always-on timer being
clockevent device for tick-broadcasting.
For clock, it is driven by 13 MHz system clock.
The implementation uses the system clock with no clock
source divider.
For interrupt, the clock event timer can be used by all cores.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
drivers/clocksource/timer-mediatek.c | 225 +++++++++++++++++++++++++---------
1 file changed, 167 insertions(+), 58 deletions(-)
diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
index d94d8e1..6878736 100644
--- a/drivers/clocksource/timer-mediatek.c
+++ b/drivers/clocksource/timer-mediatek.c
@@ -26,32 +26,46 @@
#include <linux/slab.h>
#include "timer-of.h"
-#define GPT_IRQ_EN_REG 0x00
-#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
-#define GPT_IRQ_ACK_REG 0x08
-#define GPT_IRQ_ACK(val) BIT((val) - 1)
-
-#define TIMER_CTRL_REG(val) (0x10 * (val))
-#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
-#define TIMER_CTRL_OP_ONESHOT (0)
-#define TIMER_CTRL_OP_REPEAT (1)
-#define TIMER_CTRL_OP_FREERUN (3)
-#define TIMER_CTRL_CLEAR (2)
-#define TIMER_CTRL_ENABLE (1)
-#define TIMER_CTRL_DISABLE (0)
-
-#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
-#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
-#define TIMER_CLK_SRC_SYS13M (0)
-#define TIMER_CLK_SRC_RTC32K (1)
-#define TIMER_CLK_DIV1 (0x0)
-#define TIMER_CLK_DIV2 (0x1)
-
-#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
-#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
-
-#define GPT_CLK_EVT 1
-#define GPT_CLK_SRC 2
+#define TIMER_CLK_EVT (1)
+#define TIMER_CLK_SRC (2)
+
+#define TIMER_SYNC_TICKS (3)
+
+/* gpt */
+#define GPT_IRQ_EN_REG 0x00
+#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
+#define GPT_IRQ_ACK_REG 0x08
+#define GPT_IRQ_ACK(val) BIT((val) - 1)
+
+#define GPT_CTRL_REG(val) (0x10 * (val))
+#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
+#define GPT_CTRL_OP_ONESHOT (0)
+#define GPT_CTRL_OP_REPEAT (1)
+#define GPT_CTRL_OP_FREERUN (3)
+#define GPT_CTRL_CLEAR (2)
+#define GPT_CTRL_ENABLE (1)
+#define GPT_CTRL_DISABLE (0)
+
+#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
+#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
+#define GPT_CLK_SRC_SYS13M (0)
+#define GPT_CLK_SRC_RTC32K (1)
+#define GPT_CLK_DIV1 (0x0)
+#define GPT_CLK_DIV2 (0x1)
+
+#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
+#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
+
+/* system timer */
+#define SYST_CON (0x0)
+#define SYST_VAL (0x4)
+
+#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
+#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
+
+#define SYST_CON_EN BIT(0)
+#define SYST_CON_IRQ_EN BIT(1)
+#define SYST_CON_IRQ_CLR BIT(4)
struct mtk_timer_private {
unsigned long ticks_per_jiffy;
@@ -75,6 +89,71 @@ static void mtk_timer_of_priv_get(struct timer_of *to,
*ticks_per_jiffy = pd->ticks_per_jiffy;
}
+static void mtk_syst_reset(struct timer_of *to)
+{
+ /* clear and disable interrupt */
+ writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
+
+ /* reset counter */
+ writel(0, SYST_VAL_REG(to));
+
+ /* disable timer */
+ writel(0, SYST_CON_REG(to));
+}
+
+static void mtk_syst_ack_irq(struct timer_of *to)
+{
+ mtk_syst_reset(to);
+}
+
+static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
+{
+ struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
+ struct timer_of *to = to_timer_of(clkevt);
+
+ mtk_syst_ack_irq(to);
+ clkevt->event_handler(clkevt);
+
+ return IRQ_HANDLED;
+}
+
+static int mtk_syst_clkevt_next_event(unsigned long ticks,
+ struct clock_event_device *clkevt)
+{
+ struct timer_of *to = to_timer_of(clkevt);
+
+ /*
+ * reset timer first because we do not expect interrupt is triggered
+ * by old compare value.
+ */
+ mtk_syst_reset(to);
+
+ writel(SYST_CON_EN, SYST_CON_REG(to));
+
+ writel(ticks, SYST_VAL_REG(to));
+
+ writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
+
+ return 0;
+}
+
+static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
+{
+ mtk_syst_reset(to_timer_of(clkevt));
+
+ return 0;
+}
+
+static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
+{
+ return mtk_syst_clkevt_shutdown(clkevt);
+}
+
+static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
+{
+ return 0;
+}
+
static u64 notrace mtk_gpt_read_sched_clock(void)
{
return readl_relaxed(gpt_sched_reg);
@@ -84,15 +163,15 @@ static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
{
u32 val;
- val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer));
- writel(val & ~TIMER_CTRL_ENABLE, timer_of_base(to) +
- TIMER_CTRL_REG(timer));
+ val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
+ writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
+ GPT_CTRL_REG(timer));
}
static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
unsigned long delay, u8 timer)
{
- writel(delay, timer_of_base(to) + TIMER_CMP_REG(timer));
+ writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
}
static void mtk_gpt_clkevt_time_start(struct timer_of *to,
@@ -103,23 +182,23 @@ static void mtk_gpt_clkevt_time_start(struct timer_of *to,
/* Acknowledge interrupt */
writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
- val = readl(timer_of_base(to) + TIMER_CTRL_REG(timer));
+ val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
/* Clear 2 bit timer operation mode field */
- val &= ~TIMER_CTRL_OP(0x3);
+ val &= ~GPT_CTRL_OP(0x3);
if (periodic)
- val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
+ val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
else
- val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
+ val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
- writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
- timer_of_base(to) + TIMER_CTRL_REG(timer));
+ writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
+ timer_of_base(to) + GPT_CTRL_REG(timer));
}
static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
{
- mtk_gpt_clkevt_time_stop(to_timer_of(clk), GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
return 0;
}
@@ -128,10 +207,10 @@ static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
struct timer_of *to = to_timer_of(clk);
unsigned long ticks_per_jiffy;
- mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
mtk_timer_of_priv_get(to, &ticks_per_jiffy);
- mtk_gpt_clkevt_time_setup(to, ticks_per_jiffy, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_start(to, true, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_setup(to, ticks_per_jiffy, TIMER_CLK_EVT);
+ mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
return 0;
}
@@ -140,9 +219,9 @@ static int mtk_gpt_clkevt_next_event(unsigned long event,
{
struct timer_of *to = to_timer_of(clk);
- mtk_gpt_clkevt_time_stop(to, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_setup(to, event, GPT_CLK_EVT);
- mtk_gpt_clkevt_time_start(to, false, GPT_CLK_EVT);
+ mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
+ mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
+ mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
return 0;
}
@@ -153,7 +232,7 @@ static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
struct timer_of *to = to_timer_of(clkevt);
/* Acknowledge timer0 irq */
- writel(GPT_IRQ_ACK(GPT_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
+ writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
clkevt->event_handler(clkevt);
return IRQ_HANDLED;
@@ -162,16 +241,16 @@ static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
static void
__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
{
- writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
- timer_of_base(to) + TIMER_CTRL_REG(timer));
+ writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
+ timer_of_base(to) + GPT_CTRL_REG(timer));
- writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
- timer_of_base(to) + TIMER_CLK_REG(timer));
+ writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
+ timer_of_base(to) + GPT_CLK_REG(timer));
- writel(0x0, timer_of_base(to) + TIMER_CMP_REG(timer));
+ writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
- writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
- timer_of_base(to) + TIMER_CTRL_REG(timer));
+ writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
+ timer_of_base(to) + GPT_CTRL_REG(timer));
}
static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
@@ -186,7 +265,7 @@ static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
writel(val | GPT_IRQ_ENABLE(timer),
- timer_of_base(to) + GPT_IRQ_EN_REG);
+ timer_of_base(to) + GPT_IRQ_EN_REG);
}
static struct timer_of to = {
@@ -203,6 +282,35 @@ static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
},
};
+static int __init mtk_syst_init(struct device_node *node)
+{
+ int ret;
+
+ to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
+ to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
+ to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
+ to.clkevt.tick_resume = mtk_syst_clkevt_resume;
+ to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
+ to.of_irq.handler = mtk_syst_handler;
+
+ ret = timer_of_init(node, &to);
+ if (ret)
+ goto err;
+
+ mtk_syst_reset(&to);
+
+ clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
+ TIMER_SYNC_TICKS, 0xffffffff);
+
+ pr_info("irq=%d, rate=%lu, max_ns: %llu, min_ns: %llu\n",
+ timer_of_irq(&to), timer_of_rate(&to),
+ to.clkevt.max_delta_ns, to.clkevt.min_delta_ns);
+
+ return 0;
+err:
+ return ret;
+}
+
static int __init mtk_gpt_init(struct device_node *node)
{
int ret;
@@ -230,25 +338,26 @@ static int __init mtk_gpt_init(struct device_node *node)
mtk_timer_of_priv_set(&to, DIV_ROUND_UP(timer_of_rate(&to), HZ));
/* Configure clock source */
- mtk_gpt_setup(&to, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
- clocksource_mmio_init(timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC),
+ mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
+ clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
node->name, timer_of_rate(&to), 300, 32,
clocksource_mmio_readl_up);
- gpt_sched_reg = timer_of_base(&to) + TIMER_CNT_REG(GPT_CLK_SRC);
+ gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
/* Configure clock event */
- mtk_gpt_setup(&to, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
+ mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 0x3,
0xffffffff);
- mtk_gpt_enable_irq(&to, GPT_CLK_EVT);
+ mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
return 0;
-
deinit:
timer_of_cleanup(&to);
err:
return ret;
}
+
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
+TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-systimer", mtk_syst_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer
2018-06-28 10:45 ` [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer Stanley Chu
@ 2018-06-28 14:08 ` Daniel Lezcano
2018-06-29 0:16 ` Stanley Chu
0 siblings, 1 reply; 12+ messages in thread
From: Daniel Lezcano @ 2018-06-28 14:08 UTC (permalink / raw)
To: Stanley Chu, Matthias Brugger, Thomas Gleixner, Rob Herring
Cc: linux-kernel, linux-mediatek, devicetree, wsd_upstream
On 28/06/2018 12:45, Stanley Chu wrote:
> This patch adds a new "System Timer" on the Mediatek SoCs.
>
> The System Timer is introduced as an always-on timer being
> clockevent device for tick-broadcasting.
>
> For clock, it is driven by 13 MHz system clock.
> The implementation uses the system clock with no clock
> source divider.
>
> For interrupt, the clock event timer can be used by all cores.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
Please do the GPT prefix in patch 3/5, so this patch will contain 'syst'
addition only.
> drivers/clocksource/timer-mediatek.c | 225 +++++++++++++++++++++++++---------
> 1 file changed, 167 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
> index d94d8e1..6878736 100644
> --- a/drivers/clocksource/timer-mediatek.c
> +++ b/drivers/clocksource/timer-mediatek.c
> @@ -26,32 +26,46 @@
> #include <linux/slab.h>
> #include "timer-of.h"
>
> -#define GPT_IRQ_EN_REG 0x00
> -#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
> -#define GPT_IRQ_ACK_REG 0x08
> -#define GPT_IRQ_ACK(val) BIT((val) - 1)
> -
> -#define TIMER_CTRL_REG(val) (0x10 * (val))
> -#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
> -#define TIMER_CTRL_OP_ONESHOT (0)
> -#define TIMER_CTRL_OP_REPEAT (1)
> -#define TIMER_CTRL_OP_FREERUN (3)
> -#define TIMER_CTRL_CLEAR (2)
> -#define TIMER_CTRL_ENABLE (1)
> -#define TIMER_CTRL_DISABLE (0)
> -
> -#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
> -#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
> -#define TIMER_CLK_SRC_SYS13M (0)
> -#define TIMER_CLK_SRC_RTC32K (1)
> -#define TIMER_CLK_DIV1 (0x0)
> -#define TIMER_CLK_DIV2 (0x1)
> -
> -#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
> -#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
> -
> -#define GPT_CLK_EVT 1
> -#define GPT_CLK_SRC 2
> +#define TIMER_CLK_EVT (1)
> +#define TIMER_CLK_SRC (2)
> +
> +#define TIMER_SYNC_TICKS (3)
> +
> +/* gpt */
> +#define GPT_IRQ_EN_REG 0x00
> +#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
> +#define GPT_IRQ_ACK_REG 0x08
> +#define GPT_IRQ_ACK(val) BIT((val) - 1)
> +
> +#define GPT_CTRL_REG(val) (0x10 * (val))
> +#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
> +#define GPT_CTRL_OP_ONESHOT (0)
> +#define GPT_CTRL_OP_REPEAT (1)
> +#define GPT_CTRL_OP_FREERUN (3)
> +#define GPT_CTRL_CLEAR (2)
> +#define GPT_CTRL_ENABLE (1)
> +#define GPT_CTRL_DISABLE (0)
> +
> +#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
> +#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
> +#define GPT_CLK_SRC_SYS13M (0)
> +#define GPT_CLK_SRC_RTC32K (1)
> +#define GPT_CLK_DIV1 (0x0)
> +#define GPT_CLK_DIV2 (0x1)
> +
> +#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
> +#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
Please do the GPT prefix in patch 3/5, so this patch will contain 'syst'
addition only and will make review easier.
Thanks.
--
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 5/5] clocksource/drivers/timer-mediatek: Add support for system timer
2018-06-28 14:08 ` Daniel Lezcano
@ 2018-06-29 0:16 ` Stanley Chu
0 siblings, 0 replies; 12+ messages in thread
From: Stanley Chu @ 2018-06-29 0:16 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Matthias Brugger, Thomas Gleixner, Rob Herring, linux-kernel,
linux-mediatek, devicetree, wsd_upstream
On Thu, 2018-06-28 at 16:08 +0200, Daniel Lezcano wrote:
> On 28/06/2018 12:45, Stanley Chu wrote:
> > This patch adds a new "System Timer" on the Mediatek SoCs.
> >
> > The System Timer is introduced as an always-on timer being
> > clockevent device for tick-broadcasting.
> >
> > For clock, it is driven by 13 MHz system clock.
> > The implementation uses the system clock with no clock
> > source divider.
> >
> > For interrupt, the clock event timer can be used by all cores.
> >
> > Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> > ---
>
> Please do the GPT prefix in patch 3/5, so this patch will contain 'syst'
> addition only.
>
Hi Daniel,
Sure! Will re-arrange patches in v4.
Thanks.
Stanley Chu
^ permalink raw reply [flat|nested] 12+ messages in thread