[PATCH v3 0/3] Add display clock controller driver for SDM845

[PATCH v3 0/3] Add display clock controller driver for SDM845

[Taniya Das]

 [v3]
  * Move frequency table macro to common file,
    add the patch along to maintain dependency.

 [v2]
  * Removed unused header file includes.
  * Moved the frequency table macro to a common file [1].
  * Move to pll config to probe.
  * Update SoC name in device tree binding and
    also update the Kconfig.

Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.

Taniya Das (3):
  clk: qcom: Move frequency table macro to common file
  dt-bindings: clock: Introduce QCOM Display clock bindings
  clk: qcom: Add display clock controller driver for SDM845

 .../devicetree/bindings/clock/qcom,dispcc.txt      |  19 +
 drivers/clk/qcom/Kconfig                           |  10 +
 drivers/clk/qcom/Makefile                          |   1 +
 drivers/clk/qcom/clk-rcg.h                         |   2 +
 drivers/clk/qcom/dispcc-sdm845.c                   | 674 +++++++++++++++++++++
 drivers/clk/qcom/gcc-apq8084.c                     |   2 -
 drivers/clk/qcom/gcc-ipq4019.c                     |   2 -
 drivers/clk/qcom/gcc-ipq8074.c                     |   2 -
 drivers/clk/qcom/gcc-msm8916.c                     |   2 -
 drivers/clk/qcom/gcc-msm8974.c                     |   2 -
 drivers/clk/qcom/gcc-msm8994.c                     |   2 -
 drivers/clk/qcom/gcc-msm8996.c                     |   2 -
 drivers/clk/qcom/gcc-msm8998.c                     |   2 -
 drivers/clk/qcom/gcc-sdm845.c                      |   2 -
 drivers/clk/qcom/mmcc-apq8084.c                    |   2 -
 drivers/clk/qcom/mmcc-msm8974.c                    |   2 -
 drivers/clk/qcom/mmcc-msm8996.c                    |   2 -
 drivers/clk/qcom/videocc-sdm845.c                  |   2 -
 include/dt-bindings/clock/qcom,dispcc-sdm845.h     |  45 ++
 19 files changed, 751 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.txt
 create mode 100644 drivers/clk/qcom/dispcc-sdm845.c
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sdm845.h

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v3 1/3] clk: qcom: Move frequency table macro to common file

[Taniya Das]

Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/clk-rcg.h        | 2 ++
 drivers/clk/qcom/gcc-apq8084.c    | 2 --
 drivers/clk/qcom/gcc-ipq4019.c    | 2 --
 drivers/clk/qcom/gcc-ipq8074.c    | 2 --
 drivers/clk/qcom/gcc-msm8916.c    | 2 --
 drivers/clk/qcom/gcc-msm8974.c    | 2 --
 drivers/clk/qcom/gcc-msm8994.c    | 2 --
 drivers/clk/qcom/gcc-msm8996.c    | 2 --
 drivers/clk/qcom/gcc-msm8998.c    | 2 --
 drivers/clk/qcom/gcc-sdm845.c     | 2 --
 drivers/clk/qcom/mmcc-apq8084.c   | 2 --
 drivers/clk/qcom/mmcc-msm8974.c   | 2 --
 drivers/clk/qcom/mmcc-msm8996.c   | 2 --
 drivers/clk/qcom/videocc-sdm845.c | 2 --
 14 files changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b209a2f..dbd5a9e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -7,6 +7,8 @@
 #include <linux/clk-provider.h>
 #include "clk-regmap.h"

+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
 struct freq_tbl {
 	unsigned long freq;
 	u8 src;
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 486d961..9c99a71 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -106,8 +106,6 @@ enum {
 	"sleep_clk_src",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_pll gpll0 = {
 	.l_reg = 0x0004,
 	.m_reg = 0x0008,
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 46cb256..8902ad4 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -179,8 +179,6 @@ struct clk_fepll {
 	"ddrpllapss",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
 	F(48000000, P_XO, 1, 0, 0),
 	F(200000000, P_FEPLL200, 1, 0, 0),
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 0462f4a..505c626 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -32,8 +32,6 @@
 #include "clk-regmap-mux.h"
 #include "reset.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_XO,
 	P_GPLL0,
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index d6c7f50..ac2b0aa 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -264,8 +264,6 @@ enum {
 	"sleep_clk",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_pll gpll0 = {
 	.l_reg = 0x21004,
 	.m_reg = 0x21008,
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 348e30d..08e2900d 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -62,8 +62,6 @@ enum {
 	"gpll4_vote",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_pll gpll0 = {
 	.l_reg = 0x0004,
 	.m_reg = 0x0008,
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 1e38efc..53f0f36 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -57,8 +57,6 @@ enum {
 	"gpll4",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_fixed_factor xo = {
 	.mult = 1,
 	.div = 1,
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 9f35b3f..9d3756c 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -32,8 +32,6 @@
 #include "reset.h"
 #include "gdsc.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_XO,
 	P_GPLL0,
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 78d87f5..9f0ae40 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -25,8 +25,6 @@
 #include "reset.h"
 #include "gdsc.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_AUD_REF_CLK,
 	P_CORE_BI_PLL_TEST_SE,
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index e78e6f5..19b470f 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -25,8 +25,6 @@
 #include "gdsc.h"
 #include "reset.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_BI_TCXO,
 	P_AUD_REF_CLK,
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 30777f9..4ce1d7c 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -219,8 +219,6 @@ enum {
 	"sleep_clk_src",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_pll mmpll0 = {
 	.l_reg = 0x0004,
 	.m_reg = 0x0008,
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 715e7cd..9181851 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -184,8 +184,6 @@ enum {
 	"dsi1pllbyte",
 };

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 static struct clk_pll mmpll0 = {
 	.l_reg = 0x0004,
 	.m_reg = 0x0008,
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 1a25ee4..60f08b3 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -34,8 +34,6 @@
 #include "reset.h"
 #include "gdsc.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_XO,
 	P_MMPLL0,
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
index 9073b7a..5d6a772 100644
--- a/drivers/clk/qcom/videocc-sdm845.c
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -18,8 +18,6 @@
 #include "clk-pll.h"
 #include "gdsc.h"

-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
 enum {
 	P_BI_TCXO,
 	P_CORE_BI_PLL_TEST_SE,
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v3 2/3] dt-bindings: clock: Introduce QCOM Display clock bindings

[Taniya Das]

Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/clock/qcom,dispcc.txt      | 19 +++++++++
 include/dt-bindings/clock/qcom,dispcc-sdm845.h     | 45 ++++++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.txt
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sdm845.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
new file mode 100644
index 0000000..d639e18
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
@@ -0,0 +1,19 @@
+Qualcomm Technologies, Inc. Display Clock Controller Binding
+------------------------------------------------------------
+
+Required properties :
+
+- compatible : shall contain "qcom,sdm845-dispcc"
+- reg : shall contain base register location and length.
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,sdm845-dispcc";
+		reg = <0xaf00000 0x100000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+	};
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index 0000000..11eed4b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK					0
+#define DISP_CC_MDSS_AXI_CLK					1
+#define DISP_CC_MDSS_BYTE0_CLK					2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				4
+#define DISP_CC_MDSS_BYTE1_CLK					5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				7
+#define DISP_CC_MDSS_ESC0_CLK					8
+#define DISP_CC_MDSS_ESC0_CLK_SRC				9
+#define DISP_CC_MDSS_ESC1_CLK					10
+#define DISP_CC_MDSS_ESC1_CLK_SRC				11
+#define DISP_CC_MDSS_MDP_CLK					12
+#define DISP_CC_MDSS_MDP_CLK_SRC				13
+#define DISP_CC_MDSS_MDP_LUT_CLK				14
+#define DISP_CC_MDSS_PCLK0_CLK					15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				16
+#define DISP_CC_MDSS_PCLK1_CLK					17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				18
+#define DISP_CC_MDSS_ROT_CLK					19
+#define DISP_CC_MDSS_ROT_CLK_SRC				20
+#define DISP_CC_MDSS_RSCC_AHB_CLK				21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
+#define DISP_CC_MDSS_VSYNC_CLK					23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				24
+#define DISP_CC_PLL0						25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR					0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+
+#endif
-- 
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/Kconfig         |  10 +
 drivers/clk/qcom/Makefile        |   1 +
 drivers/clk/qcom/dispcc-sdm845.c | 674 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 685 insertions(+)
 create mode 100644 drivers/clk/qcom/dispcc-sdm845.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9c3480d..7300574 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -245,6 +245,16 @@ config SDM_VIDEOCC_845
 	  Say Y if you want to support video devices and functionality such as
 	  video encode and decode.
 
+config SDM_DISPCC_845
+	tristate "SDM845 Display Clock Controller"
+	select SDM_GCC_845
+	depends on COMMON_CLK_QCOM
+	help
+	  Support for the display clock controller on Qualcomm Technologies, Inc
+	  SDM845 devices.
+	  Say Y if you want to support display devices and functionality such as
+	  splash screen.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 762c011..2b041b2d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
 obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
new file mode 100644
index 0000000..af437e0
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+	P_BI_TCXO,
+	P_CORE_BI_PLL_TEST_SE,
+	P_DISP_CC_PLL0_OUT_MAIN,
+	P_DSI0_PHY_PLL_OUT_BYTECLK,
+	P_DSI0_PHY_PLL_OUT_DSICLK,
+	P_DSI1_PHY_PLL_OUT_BYTECLK,
+	P_DSI1_PHY_PLL_OUT_DSICLK,
+	P_GPLL0_OUT_MAIN,
+	P_GPLL0_OUT_MAIN_DIV,
+};
+
+static const struct parent_map disp_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
+	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const disp_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"dsi0_phy_pll_out_byteclk",
+	"dsi1_phy_pll_out_byteclk",
+	"core_bi_pll_test_se",
+};
+
+static const struct parent_map disp_cc_parent_map_2[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const disp_cc_parent_names_2[] = {
+	"bi_tcxo",
+	"core_bi_pll_test_se",
+};
+
+static const struct parent_map disp_cc_parent_map_3[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GPLL0_OUT_MAIN, 4 },
+	{ P_GPLL0_OUT_MAIN_DIV, 5 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const disp_cc_parent_names_3[] = {
+	"bi_tcxo",
+	"disp_cc_pll0",
+	"gcc_disp_gpll0_clk_src",
+	"gcc_disp_gpll0_div_clk_src",
+	"core_bi_pll_test_se",
+};
+
+static const struct parent_map disp_cc_parent_map_4[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
+	{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const disp_cc_parent_names_4[] = {
+	"bi_tcxo",
+	"dsi0_phy_pll_out_dsiclk",
+	"dsi1_phy_pll_out_dsiclk",
+	"core_bi_pll_test_se",
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+	.offset = 0x0,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_pll0",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_fabia_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+	.cmd_rcgr = 0x20d0,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_byte0_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+		.ops = &clk_byte2_ops,
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+	.cmd_rcgr = 0x20ec,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_byte1_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+		.ops = &clk_byte2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
+	.cmd_rcgr = 0x2108,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_esc0_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = 4,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
+	.cmd_rcgr = 0x2120,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_esc1_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = 4,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
+	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
+	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+	F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+	F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
+	.cmd_rcgr = 0x2088,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_3,
+	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_mdp_clk_src",
+		.parent_names = disp_cc_parent_names_3,
+		.num_parents = 5,
+		.ops = &clk_rcg2_shared_ops,
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
+	.cmd_rcgr = 0x2058,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_4,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_pclk0_clk_src",
+		.parent_names = disp_cc_parent_names_4,
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+		.ops = &clk_pixel_ops,
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
+	.cmd_rcgr = 0x2070,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_4,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_pclk1_clk_src",
+		.parent_names = disp_cc_parent_names_4,
+		.num_parents = 4,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+		.ops = &clk_pixel_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
+	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+	F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+	F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
+	.cmd_rcgr = 0x20a0,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_3,
+	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_rot_clk_src",
+		.parent_names = disp_cc_parent_names_3,
+		.num_parents = 5,
+		.ops = &clk_rcg2_shared_ops,
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
+	.cmd_rcgr = 0x20b8,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_2,
+	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_vsync_clk_src",
+		.parent_names = disp_cc_parent_names_2,
+		.num_parents = 2,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch disp_cc_mdss_ahb_clk = {
+	.halt_reg = 0x4004,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x4004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_axi_clk = {
+	.halt_reg = 0x4008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x4008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_axi_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte0_clk = {
+	.halt_reg = 0x2028,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2028,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
+	.reg = 0x20e8,
+	.shift = 0,
+	.width = 2,
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte0_div_clk_src",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_GET_RATE_NOCACHE,
+			.ops = &clk_regmap_div_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
+	.halt_reg = 0x202c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x202c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte0_intf_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte0_div_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte1_clk = {
+	.halt_reg = 0x2030,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte1_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte1_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
+	.reg = 0x2104,
+	.shift = 0,
+	.width = 2,
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte1_div_clk_src",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte1_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_GET_RATE_NOCACHE,
+			.ops = &clk_regmap_div_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
+	.halt_reg = 0x2034,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte1_intf_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte1_div_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_esc0_clk = {
+	.halt_reg = 0x2038,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_esc0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_esc0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_esc1_clk = {
+	.halt_reg = 0x203c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x203c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_esc1_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_esc1_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_mdp_clk = {
+	.halt_reg = 0x200c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x200c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_mdp_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_mdp_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
+	.halt_reg = 0x201c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x201c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_mdp_lut_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_mdp_clk_src",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_pclk0_clk = {
+	.halt_reg = 0x2004,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_pclk0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_pclk0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_pclk1_clk = {
+	.halt_reg = 0x2008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_pclk1_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_pclk1_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rot_clk = {
+	.halt_reg = 0x2014,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rot_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_rot_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
+	.halt_reg = 0x5004,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x5004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rscc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
+	.halt_reg = 0x5008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x5008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rscc_vsync_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_vsync_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_vsync_clk = {
+	.halt_reg = 0x2024,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_vsync_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_vsync_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct gdsc mdss_gdsc = {
+	.gdscr = 0x3000,
+	.pd = {
+		.name = "mdss_gdsc",
+	},
+	.pwrsts = PWRSTS_OFF_ON,
+	.flags = HW_CTRL | POLL_CFG_GDSCR,
+};
+
+static struct clk_regmap *disp_cc_sdm845_clocks[] = {
+	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
+	[DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
+	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
+	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
+	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
+					&disp_cc_mdss_byte0_div_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
+	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
+	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
+					&disp_cc_mdss_byte1_div_clk_src.clkr,
+	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
+	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
+	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
+	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
+	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
+	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
+	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
+	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
+	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
+	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
+	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
+	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
+	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
+	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
+	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
+	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
+	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
+	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
+};
+
+static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
+	[DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
+};
+
+static struct gdsc *disp_cc_sdm845_gdscs[] = {
+	[MDSS_GDSC] = &mdss_gdsc,
+};
+
+static const struct regmap_config disp_cc_sdm845_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x10000,
+	.fast_io	= true,
+};
+
+static const struct qcom_cc_desc disp_cc_sdm845_desc = {
+	.config = &disp_cc_sdm845_regmap_config,
+	.clks = disp_cc_sdm845_clocks,
+	.num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
+	.resets = disp_cc_sdm845_resets,
+	.num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
+	.gdscs = disp_cc_sdm845_gdscs,
+	.num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
+};
+
+static const struct of_device_id disp_cc_sdm845_match_table[] = {
+	{ .compatible = "qcom,sdm845-dispcc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
+
+static int disp_cc_sdm845_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	struct alpha_pll_config disp_cc_pll0_config = {
+		.l = 0x2c,
+		.alpha = 0xcaaa,
+	};
+
+	regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+
+	/* Enable hardware clock gating for DSI and MDP clocks */
+	regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
+
+	return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
+}
+
+static struct platform_driver disp_cc_sdm845_driver = {
+	.probe		= disp_cc_sdm845_probe,
+	.driver		= {
+		.name	= "disp_cc-sdm845",
+		.of_match_table = disp_cc_sdm845_match_table,
+	},
+};
+
+static int __init disp_cc_sdm845_init(void)
+{
+	return platform_driver_register(&disp_cc_sdm845_driver);
+}
+subsys_initcall(disp_cc_sdm845_init);
+
+static void __exit disp_cc_sdm845_exit(void)
+{
+	platform_driver_unregister(&disp_cc_sdm845_driver);
+}
+module_exit(disp_cc_sdm845_exit);
+
+MODULE_LICENSE("GPL v2");
-- 
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Re: [PATCH v3 1/3] clk: qcom: Move frequency table macro to common file

[Stephen Boyd]

Quoting Taniya Das (2018-06-23 07:19:25)
> Frequency table macro is used by multiple clock drivers, move frequency
> table macro to common header file.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---

Applied to clk-next

Re: [PATCH v3 2/3] dt-bindings: clock: Introduce QCOM Display clock bindings

[Stephen Boyd]

Quoting Taniya Das (2018-06-23 07:19:26)
> Add device tree bindings for display clock controller for Qualcomm
> Technology Inc's SDM845 SoCs.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---

Applied to clk-next

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting Taniya Das (2018-06-23 07:19:27)
> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
> new file mode 100644
> index 0000000..af437e0
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-sdm845.c
> @@ -0,0 +1,674 @@
> +// SPDX-License-Identifier: GPL-2.0
[...]
> +static struct clk_alpha_pll disp_cc_pll0 = {
> +       .offset = 0x0,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
> +       .clkr = {
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "disp_cc_pll0",
> +                       .parent_names = (const char *[]){ "bi_tcxo" },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_fabia_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
> +       .cmd_rcgr = 0x20d0,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = disp_cc_parent_map_0,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "disp_cc_mdss_byte0_clk_src",
> +               .parent_names = disp_cc_parent_names_0,
> +               .num_parents = 4,
> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

Why is there the no cache flag? Last time I asked I don't think I got
any answer, and there isn't a comment here so please at least add a
comment to the code so we don't forget.

> +               .ops = &clk_byte2_ops,
> +       },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
> +       .cmd_rcgr = 0x20ec,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = disp_cc_parent_map_0,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "disp_cc_mdss_byte1_clk_src",
> +               .parent_names = disp_cc_parent_names_0,
> +               .num_parents = 4,
> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> +               .ops = &clk_byte2_ops,
> +       },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
> +       F(19200000, P_BI_TCXO, 1, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
> +       .cmd_rcgr = 0x2108,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = disp_cc_parent_map_0,
> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "disp_cc_mdss_esc0_clk_src",
> +               .parent_names = disp_cc_parent_names_0,
> +               .num_parents = 4,
> +               .ops = &clk_rcg2_ops,
> +       },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
> +       .cmd_rcgr = 0x2120,
> +       .mnd_width = 0,
> +       .hid_width = 5,
> +       .parent_map = disp_cc_parent_map_0,
> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "disp_cc_mdss_esc1_clk_src",
> +               .parent_names = disp_cc_parent_names_0,
> +               .num_parents = 4,
> +               .ops = &clk_rcg2_ops,
> +       },
> +};
> +
[...]
> +
> +MODULE_LICENSE("GPL v2");

MODULE_DESCRIPTION?

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

Hello Stephen,

Thanks for your review comments.

On 7/9/2018 5:24 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-06-23 07:19:27)
>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
>> new file mode 100644
>> index 0000000..af437e0
>> --- /dev/null
>> +++ b/drivers/clk/qcom/dispcc-sdm845.c
>> @@ -0,0 +1,674 @@
>> +// SPDX-License-Identifier: GPL-2.0
> [...]
>> +static struct clk_alpha_pll disp_cc_pll0 = {
>> +       .offset = 0x0,
>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> +       .clkr = {
>> +               .hw.init = &(struct clk_init_data){
>> +                       .name = "disp_cc_pll0",
>> +                       .parent_names = (const char *[]){ "bi_tcxo" },
>> +                       .num_parents = 1,
>> +                       .ops = &clk_alpha_pll_fabia_ops,
>> +               },
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
>> +       .cmd_rcgr = 0x20d0,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_byte0_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> 
> Why is there the no cache flag? Last time I asked I don't think I got
> any answer, and there isn't a comment here so please at least add a
> comment to the code so we don't forget.
>

I think you missed my comment from the earlier email. I would add the 
comment and submit again.

 > Why is the nocache flag needed? Applies to all clks in this file.
 >

This flag is required for all RCGs whose PLLs are controlled outside the 
clock controller. The display code would require the recalculated rate 
always.

>> +               .ops = &clk_byte2_ops,
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
>> +       .cmd_rcgr = 0x20ec,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_byte1_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
>> +               .ops = &clk_byte2_ops,
>> +       },
>> +};
>> +
>> +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
>> +       F(19200000, P_BI_TCXO, 1, 0, 0),
>> +       { }
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
>> +       .cmd_rcgr = 0x2108,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_esc0_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
>> +       .cmd_rcgr = 0x2120,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_esc1_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
> [...]
>> +
>> +MODULE_LICENSE("GPL v2");
> 
> MODULE_DESCRIPTION?
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting Taniya Das (2018-07-08 20:38:03)
> Hello Stephen,
> 
> Thanks for your review comments.
> 
> On 7/9/2018 5:24 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-06-23 07:19:27)
> >> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
> >> new file mode 100644
> >> index 0000000..af437e0
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/dispcc-sdm845.c
> >> @@ -0,0 +1,674 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> > [...]
> >> +static struct clk_alpha_pll disp_cc_pll0 = {
> >> +       .offset = 0x0,
> >> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
> >> +       .clkr = {
> >> +               .hw.init = &(struct clk_init_data){
> >> +                       .name = "disp_cc_pll0",
> >> +                       .parent_names = (const char *[]){ "bi_tcxo" },
> >> +                       .num_parents = 1,
> >> +                       .ops = &clk_alpha_pll_fabia_ops,
> >> +               },
> >> +       },
> >> +};
> >> +
> >> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
> >> +       .cmd_rcgr = 0x20d0,
> >> +       .mnd_width = 0,
> >> +       .hid_width = 5,
> >> +       .parent_map = disp_cc_parent_map_0,
> >> +       .clkr.hw.init = &(struct clk_init_data){
> >> +               .name = "disp_cc_mdss_byte0_clk_src",
> >> +               .parent_names = disp_cc_parent_names_0,
> >> +               .num_parents = 4,
> >> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> > 
> > Why is there the no cache flag? Last time I asked I don't think I got
> > any answer, and there isn't a comment here so please at least add a
> > comment to the code so we don't forget.
> >
> 
> I think you missed my comment from the earlier email. I would add the 
> comment and submit again.

Hmm.. ok.

> 
>  > Why is the nocache flag needed? Applies to all clks in this file.
>  >
> 
> This flag is required for all RCGs whose PLLs are controlled outside the 
> clock controller. The display code would require the recalculated rate 
> always.

Right. Why is the PLL controlled outside of the clock controller? The
rate should propagate upward to the PLL from here, so who's going
outside of that?

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-08 20:38:03)
>> Hello Stephen,
>>
>> Thanks for your review comments.
>>
>> On 7/9/2018 5:24 AM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2018-06-23 07:19:27)
>>>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
>>>> new file mode 100644
>>>> index 0000000..af437e0
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/dispcc-sdm845.c
>>>> @@ -0,0 +1,674 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>> [...]
>>>> +static struct clk_alpha_pll disp_cc_pll0 = {
>>>> +       .offset = 0x0,
>>>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>>>> +       .clkr = {
>>>> +               .hw.init = &(struct clk_init_data){
>>>> +                       .name = "disp_cc_pll0",
>>>> +                       .parent_names = (const char *[]){ "bi_tcxo" },
>>>> +                       .num_parents = 1,
>>>> +                       .ops = &clk_alpha_pll_fabia_ops,
>>>> +               },
>>>> +       },
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
>>>> +       .cmd_rcgr = 0x20d0,
>>>> +       .mnd_width = 0,
>>>> +       .hid_width = 5,
>>>> +       .parent_map = disp_cc_parent_map_0,
>>>> +       .clkr.hw.init = &(struct clk_init_data){
>>>> +               .name = "disp_cc_mdss_byte0_clk_src",
>>>> +               .parent_names = disp_cc_parent_names_0,
>>>> +               .num_parents = 4,
>>>> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
>>>
>>> Why is there the no cache flag? Last time I asked I don't think I got
>>> any answer, and there isn't a comment here so please at least add a
>>> comment to the code so we don't forget.
>>>
>>
>> I think you missed my comment from the earlier email. I would add the
>> comment and submit again.
> 
> Hmm.. ok.
> 
>>
>>   > Why is the nocache flag needed? Applies to all clks in this file.
>>   >
>>
>> This flag is required for all RCGs whose PLLs are controlled outside the
>> clock controller. The display code would require the recalculated rate
>> always.
> 
> Right. Why is the PLL controlled outside of the clock controller? The
> rate should propagate upward to the PLL from here, so who's going
> outside of that?
> 
The DSI0/1 PLL are not part of the display clock controller, but in the 
display subsystem which are managed by the DRM drivers. When DRM drivers
query for the rate clock driver should always return the non cached rates.
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting Taniya Das (2018-07-09 00:07:21)
> 
> 
> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> >>
> >>   > Why is the nocache flag needed? Applies to all clks in this file.
> >>   >
> >>
> >> This flag is required for all RCGs whose PLLs are controlled outside the
> >> clock controller. The display code would require the recalculated rate
> >> always.
> > 
> > Right. Why is the PLL controlled outside of the clock controller? The
> > rate should propagate upward to the PLL from here, so who's going
> > outside of that?
> > 
> The DSI0/1 PLL are not part of the display clock controller, but in the 
> display subsystem which are managed by the DRM drivers. When DRM drivers
> query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going
through the clk APIs to do so?

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-09 00:07:21)
>>
>>
>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
>>>>
>>>>    > Why is the nocache flag needed? Applies to all clks in this file.
>>>>    >
>>>>
>>>> This flag is required for all RCGs whose PLLs are controlled outside the
>>>> clock controller. The display code would require the recalculated rate
>>>> always.
>>>
>>> Right. Why is the PLL controlled outside of the clock controller? The
>>> rate should propagate upward to the PLL from here, so who's going
>>> outside of that?
>>>
>> The DSI0/1 PLL are not part of the display clock controller, but in the
>> display subsystem which are managed by the DRM drivers. When DRM drivers
>> query for the rate clock driver should always return the non cached rates.
> 
> Why? Is the DSI PLL changing rate all the time, randomly, without going
> through the clk APIs to do so?
>

Hmm, I am afraid I do not have an answer for this, but this was the 
requirement to always return the non cached rates from the clock driver.

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-- 
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--

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting Taniya Das (2018-07-09 02:34:07)
> 
> 
> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-07-09 00:07:21)
> >>
> >>
> >> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> >>>>
> >>>>    > Why is the nocache flag needed? Applies to all clks in this file.
> >>>>    >
> >>>>
> >>>> This flag is required for all RCGs whose PLLs are controlled outside the
> >>>> clock controller. The display code would require the recalculated rate
> >>>> always.
> >>>
> >>> Right. Why is the PLL controlled outside of the clock controller? The
> >>> rate should propagate upward to the PLL from here, so who's going
> >>> outside of that?
> >>>
> >> The DSI0/1 PLL are not part of the display clock controller, but in the
> >> display subsystem which are managed by the DRM drivers. When DRM drivers
> >> query for the rate clock driver should always return the non cached rates.
> > 
> > Why? Is the DSI PLL changing rate all the time, randomly, without going
> > through the clk APIs to do so?
> >
> 
> Hmm, I am afraid I do not have an answer for this, but this was the 
> requirement to always return the non cached rates from the clock driver.
> 

Ok. Who knows about this requirement? Can we add someone from the
display driver to understand more?

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

++ Display driver team,

On 7/9/2018 8:36 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-09 02:34:07)
>>
>>
>> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2018-07-09 00:07:21)
>>>>
>>>>
>>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
>>>>>>
>>>>>>     > Why is the nocache flag needed? Applies to all clks in this file.
>>>>>>     >
>>>>>>
>>>>>> This flag is required for all RCGs whose PLLs are controlled outside the
>>>>>> clock controller. The display code would require the recalculated rate
>>>>>> always.
>>>>>
>>>>> Right. Why is the PLL controlled outside of the clock controller? The
>>>>> rate should propagate upward to the PLL from here, so who's going
>>>>> outside of that?
>>>>>
>>>> The DSI0/1 PLL are not part of the display clock controller, but in the
>>>> display subsystem which are managed by the DRM drivers. When DRM drivers
>>>> query for the rate clock driver should always return the non cached rates.
>>>
>>> Why? Is the DSI PLL changing rate all the time, randomly, without going
>>> through the clk APIs to do so?
>>>
>>
>> Hmm, I am afraid I do not have an answer for this, but this was the
>> requirement to always return the non cached rates from the clock driver.
>>
> 
> Ok. Who knows about this requirement? Can we add someone from the
> display driver to understand more?
> 
As per my discussions offline with the display teams,

There is a use-case where the clock framework is unaware of the PLL VCO 
frequency change and thus the drivers would query to get the actual HW 
frequency rather than the cached one.

Do you think keeping these flags would have any impact other than always 
getting the non-cached rates?

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting Taniya Das (2018-07-12 10:21:33)
> ++ Display driver team,
> 
> On 7/9/2018 8:36 PM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-07-09 02:34:07)
> >>
> >>
> >> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> >>> Quoting Taniya Das (2018-07-09 00:07:21)
> >>>>
> >>>>
> >>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> >>>>>>
> >>>>>>     > Why is the nocache flag needed? Applies to all clks in this file.
> >>>>>>     >
> >>>>>>
> >>>>>> This flag is required for all RCGs whose PLLs are controlled outside the
> >>>>>> clock controller. The display code would require the recalculated rate
> >>>>>> always.
> >>>>>
> >>>>> Right. Why is the PLL controlled outside of the clock controller? The
> >>>>> rate should propagate upward to the PLL from here, so who's going
> >>>>> outside of that?
> >>>>>
> >>>> The DSI0/1 PLL are not part of the display clock controller, but in the
> >>>> display subsystem which are managed by the DRM drivers. When DRM drivers
> >>>> query for the rate clock driver should always return the non cached rates.
> >>>
> >>> Why? Is the DSI PLL changing rate all the time, randomly, without going
> >>> through the clk APIs to do so?
> >>>
> >>
> >> Hmm, I am afraid I do not have an answer for this, but this was the
> >> requirement to always return the non cached rates from the clock driver.
> >>
> > 
> > Ok. Who knows about this requirement? Can we add someone from the
> > display driver to understand more?
> > 
> As per my discussions offline with the display teams,
> 
> There is a use-case where the clock framework is unaware of the PLL VCO 
> frequency change and thus the drivers would query to get the actual HW 
> frequency rather than the cached one.
> 
> Do you think keeping these flags would have any impact other than always 
> getting the non-cached rates?
> 

The flag will make it so clk_get_rate() works in spite of something
changing the frequency behind the framework's back, but I want to
understand what and why it's changing without framework involvement. We
shouldn't need the flag here, because this flag is typically for clks
that are controlled by some other entity that the kernel doesn't have
control over. In this case, it seems like we have full control of the
clk tree for the display PLL down to this clk, so it should be perfectly
fine to not have this flag. The presence of the flag means that the
display driver is doing something wrong.

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[spanda]

On 2018-07-13 01:11, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-12 10:21:33)
>> ++ Display driver team,
>> 
>> On 7/9/2018 8:36 PM, Stephen Boyd wrote:
>> > Quoting Taniya Das (2018-07-09 02:34:07)
>> >>
>> >>
>> >> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
>> >>> Quoting Taniya Das (2018-07-09 00:07:21)
>> >>>>
>> >>>>
>> >>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
>> >>>>>>
>> >>>>>>     > Why is the nocache flag needed? Applies to all clks in this file.
>> >>>>>>     >
>> >>>>>>
>> >>>>>> This flag is required for all RCGs whose PLLs are controlled outside the
>> >>>>>> clock controller. The display code would require the recalculated rate
>> >>>>>> always.
>> >>>>>
>> >>>>> Right. Why is the PLL controlled outside of the clock controller? The
>> >>>>> rate should propagate upward to the PLL from here, so who's going
>> >>>>> outside of that?
>> >>>>>
>> >>>> The DSI0/1 PLL are not part of the display clock controller, but in the
>> >>>> display subsystem which are managed by the DRM drivers. When DRM drivers
>> >>>> query for the rate clock driver should always return the non cached rates.
>> >>>
>> >>> Why? Is the DSI PLL changing rate all the time, randomly, without going
>> >>> through the clk APIs to do so?
>> >>>
>> >>
>> >> Hmm, I am afraid I do not have an answer for this, but this was the
>> >> requirement to always return the non cached rates from the clock driver.
>> >>
>> >
>> > Ok. Who knows about this requirement? Can we add someone from the
>> > display driver to understand more?
>> >
>> As per my discussions offline with the display teams,
>> 
>> There is a use-case where the clock framework is unaware of the PLL 
>> VCO
>> frequency change and thus the drivers would query to get the actual HW
>> frequency rather than the cached one.
>> 
>> Do you think keeping these flags would have any impact other than 
>> always
>> getting the non-cached rates?
>> 
> 
> The flag will make it so clk_get_rate() works in spite of something
> changing the frequency behind the framework's back, but I want to
> understand what and why it's changing without framework involvement. We
> shouldn't need the flag here, because this flag is typically for clks
> that are controlled by some other entity that the kernel doesn't have
> control over. In this case, it seems like we have full control of the
> clk tree for the display PLL down to this clk, so it should be 
> perfectly
> fine to not have this flag. The presence of the flag means that the
> display driver is doing something wrong.

These clocks are sourced from DSI PLL. In dsi command mode there is an 
idle use case when there
is no activity on display, we switch of the source DSI PLL to save power 
by calling clk_disable_unprepare().
In this scenario if some client queries the clk_get_rate(), then if 
NO_CACHE flag is used the clk
driver will return the cached rate which is some non-zero value set when 
we last called clk_set_rate(),
before enabling the clock, whereas actually in HW this clk is disabled. 
So we used the NO_CACHE flag
for the call to land in clk_recalc_rate and we return zero if the PLL is 
disabled.
I remember some customer had scripts that runs through all the clocks 
during idle screen scenario
and call clk_get_rate(), where they complained display clk_get_rate 
returns none zero value.

Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das]

Hello Stephen,

On 7/13/2018 1:55 PM, spanda@codeaurora.org wrote:
> On 2018-07-13 01:11, Stephen Boyd wrote:
>> Quoting Taniya Das (2018-07-12 10:21:33)
>>> ++ Display driver team,
>>>
>>> On 7/9/2018 8:36 PM, Stephen Boyd wrote:
>>> > Quoting Taniya Das (2018-07-09 02:34:07)
>>> >>
>>> >>
>>> >> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
>>> >>> Quoting Taniya Das (2018-07-09 00:07:21)
>>> >>>>
>>> >>>>
>>> >>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
>>> >>>>>>
>>> >>>>>>     > Why is the nocache flag needed? Applies to all clks in 
>>> this file.
>>> >>>>>>     >
>>> >>>>>>
>>> >>>>>> This flag is required for all RCGs whose PLLs are controlled 
>>> outside the
>>> >>>>>> clock controller. The display code would require the 
>>> recalculated rate
>>> >>>>>> always.
>>> >>>>>
>>> >>>>> Right. Why is the PLL controlled outside of the clock 
>>> controller? The
>>> >>>>> rate should propagate upward to the PLL from here, so who's going
>>> >>>>> outside of that?
>>> >>>>>
>>> >>>> The DSI0/1 PLL are not part of the display clock controller, but 
>>> in the
>>> >>>> display subsystem which are managed by the DRM drivers. When DRM 
>>> drivers
>>> >>>> query for the rate clock driver should always return the non 
>>> cached rates.
>>> >>>
>>> >>> Why? Is the DSI PLL changing rate all the time, randomly, without 
>>> going
>>> >>> through the clk APIs to do so?
>>> >>>
>>> >>
>>> >> Hmm, I am afraid I do not have an answer for this, but this was the
>>> >> requirement to always return the non cached rates from the clock 
>>> driver.
>>> >>
>>> >
>>> > Ok. Who knows about this requirement? Can we add someone from the
>>> > display driver to understand more?
>>> >
>>> As per my discussions offline with the display teams,
>>>
>>> There is a use-case where the clock framework is unaware of the PLL VCO
>>> frequency change and thus the drivers would query to get the actual HW
>>> frequency rather than the cached one.
>>>
>>> Do you think keeping these flags would have any impact other than always
>>> getting the non-cached rates?
>>>
>>
>> The flag will make it so clk_get_rate() works in spite of something
>> changing the frequency behind the framework's back, but I want to
>> understand what and why it's changing without framework involvement. We
>> shouldn't need the flag here, because this flag is typically for clks
>> that are controlled by some other entity that the kernel doesn't have
>> control over. In this case, it seems like we have full control of the
>> clk tree for the display PLL down to this clk, so it should be perfectly
>> fine to not have this flag. The presence of the flag means that the
>> display driver is doing something wrong.
> 
> These clocks are sourced from DSI PLL. In dsi command mode there is an 
> idle use case when there
> is no activity on display, we switch of the source DSI PLL to save power 
> by calling clk_disable_unprepare().
> In this scenario if some client queries the clk_get_rate(), then if 
> NO_CACHE flag is used the clk
> driver will return the cached rate which is some non-zero value set when 
> we last called clk_set_rate(),
> before enabling the clock, whereas actually in HW this clk is disabled. 
> So we used the NO_CACHE flag
> for the call to land in clk_recalc_rate and we return zero if the PLL is 
> disabled.
> I remember some customer had scripts that runs through all the clocks 
> during idle screen scenario
> and call clk_get_rate(), where they complained display clk_get_rate 
> returns none zero value.
> 
> 

Do you think the clock driver needs any update for flag for the next series?

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-- 
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Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Stephen Boyd]

Quoting spanda@codeaurora.org (2018-07-13 01:25:49)
> On 2018-07-13 01:11, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-07-12 10:21:33)
> >> ++ Display driver team,
> >> 
> >> On 7/9/2018 8:36 PM, Stephen Boyd wrote:
> >> > Quoting Taniya Das (2018-07-09 02:34:07)
> >> >>
> >> >>
> >> >> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> >> >>> Quoting Taniya Das (2018-07-09 00:07:21)
> >> >>>>
> >> >>>>
> >> >>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> >> >>>>>>
> >> >>>>>>     > Why is the nocache flag needed? Applies to all clks in this file.
> >> >>>>>>     >
> >> >>>>>>
> >> >>>>>> This flag is required for all RCGs whose PLLs are controlled outside the
> >> >>>>>> clock controller. The display code would require the recalculated rate
> >> >>>>>> always.
> >> >>>>>
> >> >>>>> Right. Why is the PLL controlled outside of the clock controller? The
> >> >>>>> rate should propagate upward to the PLL from here, so who's going
> >> >>>>> outside of that?
> >> >>>>>
> >> >>>> The DSI0/1 PLL are not part of the display clock controller, but in the
> >> >>>> display subsystem which are managed by the DRM drivers. When DRM drivers
> >> >>>> query for the rate clock driver should always return the non cached rates.
> >> >>>
> >> >>> Why? Is the DSI PLL changing rate all the time, randomly, without going
> >> >>> through the clk APIs to do so?
> >> >>>
> >> >>
> >> >> Hmm, I am afraid I do not have an answer for this, but this was the
> >> >> requirement to always return the non cached rates from the clock driver.
> >> >>
> >> >
> >> > Ok. Who knows about this requirement? Can we add someone from the
> >> > display driver to understand more?
> >> >
> >> As per my discussions offline with the display teams,
> >> 
> >> There is a use-case where the clock framework is unaware of the PLL 
> >> VCO
> >> frequency change and thus the drivers would query to get the actual HW
> >> frequency rather than the cached one.
> >> 
> >> Do you think keeping these flags would have any impact other than 
> >> always
> >> getting the non-cached rates?
> >> 
> > 
> > The flag will make it so clk_get_rate() works in spite of something
> > changing the frequency behind the framework's back, but I want to
> > understand what and why it's changing without framework involvement. We
> > shouldn't need the flag here, because this flag is typically for clks
> > that are controlled by some other entity that the kernel doesn't have
> > control over. In this case, it seems like we have full control of the
> > clk tree for the display PLL down to this clk, so it should be 
> > perfectly
> > fine to not have this flag. The presence of the flag means that the
> > display driver is doing something wrong.
> 
> These clocks are sourced from DSI PLL. In dsi command mode there is an 
> idle use case when there
> is no activity on display, we switch of the source DSI PLL to save power 
> by calling clk_disable_unprepare().
> In this scenario if some client queries the clk_get_rate(), then if 
> NO_CACHE flag is used the clk
> driver will return the cached rate which is some non-zero value set when 
> we last called clk_set_rate(),
> before enabling the clock, whereas actually in HW this clk is disabled. 

If the clk is disabled in hardware it doesn't mean clk_get_rate() should
return 0 Hz. The frequency of the clk is set to something, so we should
return what that frequency is by reading the hardware.

> So we used the NO_CACHE flag
> for the call to land in clk_recalc_rate and we return zero if the PLL is 
> disabled.

This is super wrong. If the PLL is disabled it still has some frequency
configured.