* [PATCH v6 0/5] Add i.MX8MQ clock driver
@ 2018-08-22 13:48 Abel Vesa
2018-08-22 13:48 ` [PATCH v6 1/5] dt-bindings: add binding for i.MX8MQ CCM Abel Vesa
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw)
To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang
Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa,
Abel Vesa
Fifth version can be found here:
https://lkml.org/lkml/2018/8/20/83
Changes since v5:
* Fixed the predivider and divider register values as
reported by Sascha.
* Changed the commit message of the 4th patch to match
with what the commit is adding
Changes since v4:
* Implemented divider ops and used clk-composite as suggested
by Sascha Hauer.
Changes since v3:
* Added a composite clock type to get rid of some complexity
from clk-imx8mq. This new composite clock type will also be
used by all the imx8 socs that will follow.
* Added back the reviewed-by tag.
Abel Vesa (1):
clk: imx: add imx composite clock
Lucas Stach (4):
dt-bindings: add binding for i.MX8MQ CCM
clk: imx: add fractional PLL output clock
clk: imx: add SCCG PLL type
clk: imx: add clock driver for i.MX8MQ CCM
.../devicetree/bindings/clock/imx8mq-clock.txt | 20 +
drivers/clk/imx/Makefile | 6 +-
drivers/clk/imx/clk-composite.c | 157 +++++
drivers/clk/imx/clk-frac-pll.c | 230 ++++++++
drivers/clk/imx/clk-imx8mq.c | 631 +++++++++++++++++++++
drivers/clk/imx/clk-sccg-pll.c | 231 ++++++++
drivers/clk/imx/clk.h | 57 ++
include/dt-bindings/clock/imx8mq-clock.h | 410 +++++++++++++
8 files changed, 1741 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt
create mode 100644 drivers/clk/imx/clk-composite.c
create mode 100644 drivers/clk/imx/clk-frac-pll.c
create mode 100644 drivers/clk/imx/clk-imx8mq.c
create mode 100644 drivers/clk/imx/clk-sccg-pll.c
create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
--
2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v6 1/5] dt-bindings: add binding for i.MX8MQ CCM 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa @ 2018-08-22 13:48 ` Abel Vesa 2018-08-22 13:48 ` [PATCH v6 2/5] clk: imx: add fractional PLL output clock Abel Vesa ` (3 subsequent siblings) 4 siblings, 0 replies; 15+ messages in thread From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw) To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa, Abel Vesa From: Lucas Stach <l.stach@pengutronix.de> This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/clock/imx8mq-clock.txt | 20 + include/dt-bindings/clock/imx8mq-clock.h | 410 +++++++++++++++++++++ 2 files changed, 430 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt create mode 100644 include/dt-bindings/clock/imx8mq-clock.h diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt new file mode 100644 index 0000000..52de826 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt @@ -0,0 +1,20 @@ +* Clock bindings for NXP i.MX8M Quad + +Required properties: +- compatible: Should be "fsl,imx8mq-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include the following entries: + - "ckil" + - "osc_25m" + - "osc_27m" + - "clk_ext1" + - "clk_ext2" + - "clk_ext3" + - "clk_ext4" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h +for the full list of i.MX8M Quad clock IDs. diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 0000000..0d19bd9 --- /dev/null +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,410 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 115 + +/* AHB */ +#define IMX8MQ_CLK_AHB_SRC 116 +#define IMX8MQ_CLK_AHB_CG 117 +#define IMX8MQ_CLK_AHB_PRE_DIV 118 +#define IMX8MQ_CLK_AHB_DIV 119 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB_SRC 120 +#define IMX8MQ_CLK_AUDIO_AHB_CG 121 +#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 122 +#define IMX8MQ_CLK_AUDIO_AHB_DIV 123 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 124 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 125 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 126 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 127 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 128 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 129 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 130 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 131 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 132 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 133 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 134 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 135 + +#define IMX8MQ_CLK_SAI2 136 + +#define IMX8MQ_CLK_SAI3 137 + +#define IMX8MQ_CLK_SAI4 138 + +#define IMX8MQ_CLK_SAI5 139 + +#define IMX8MQ_CLK_SAI6 140 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 127 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 131 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 135 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 139 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 143 +/* NAND */ +#define IMX8MQ_CLK_NAND 147 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 148 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 149 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 150 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 151 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 152 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 153 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 154 +/* UART1 */ +#define IMX8MQ_CLK_UART1 155 +/* UART2 */ +#define IMX8MQ_CLK_UART2 156 +/* UART3 */ +#define IMX8MQ_CLK_UART3 157 +/* UART4 */ +#define IMX8MQ_CLK_UART4 158 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 159 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 160 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 161 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 162 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 163 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 164 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 165 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 166 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 167 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 168 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 169 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 170 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 171 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 172 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 373 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 374 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 375 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 376 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 377 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 378 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 379 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 380 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 381 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 382 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 383 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 384 +#define IMX8MQ_CLK_DRAM_ROOT 385 +#define IMX8MQ_CLK_ECSPI1_ROOT 386 +#define IMX8MQ_CLK_ECSPI2_ROOT 387 +#define IMX8MQ_CLK_ECSPI3_ROOT 388 +#define IMX8MQ_CLK_ENET1_ROOT 389 +#define IMX8MQ_CLK_GPT1_ROOT 390 +#define IMX8MQ_CLK_I2C1_ROOT 391 +#define IMX8MQ_CLK_I2C2_ROOT 392 +#define IMX8MQ_CLK_I2C3_ROOT 393 +#define IMX8MQ_CLK_I2C4_ROOT 394 +#define IMX8MQ_CLK_M4_ROOT 395 +#define IMX8MQ_CLK_PCIE1_ROOT 396 +#define IMX8MQ_CLK_PCIE2_ROOT 397 +#define IMX8MQ_CLK_PWM1_ROOT 398 +#define IMX8MQ_CLK_PWM2_ROOT 399 +#define IMX8MQ_CLK_PWM3_ROOT 400 +#define IMX8MQ_CLK_PWM4_ROOT 401 +#define IMX8MQ_CLK_QSPI_ROOT 402 +#define IMX8MQ_CLK_SAI1_ROOT 403 +#define IMX8MQ_CLK_SAI2_ROOT 404 +#define IMX8MQ_CLK_SAI3_ROOT 405 +#define IMX8MQ_CLK_SAI4_ROOT 406 +#define IMX8MQ_CLK_SAI5_ROOT 407 +#define IMX8MQ_CLK_SAI6_ROOT 408 +#define IMX8MQ_CLK_UART1_ROOT 409 +#define IMX8MQ_CLK_UART2_ROOT 411 +#define IMX8MQ_CLK_UART3_ROOT 412 +#define IMX8MQ_CLK_UART4_ROOT 413 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 414 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 415 +#define IMX8MQ_CLK_USB1_PHY_ROOT 416 +#define IMX8MQ_CLK_USB2_PHY_ROOT 417 +#define IMX8MQ_CLK_USDHC1_ROOT 418 +#define IMX8MQ_CLK_USDHC2_ROOT 419 +#define IMX8MQ_CLK_WDOG1_ROOT 420 +#define IMX8MQ_CLK_WDOG2_ROOT 421 +#define IMX8MQ_CLK_WDOG3_ROOT 422 +#define IMX8MQ_CLK_GPU_ROOT 423 +#define IMX8MQ_CLK_HEVC_ROOT 424 +#define IMX8MQ_CLK_AVC_ROOT 425 +#define IMX8MQ_CLK_VP9_ROOT 426 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 427 +#define IMX8MQ_CLK_DISP_ROOT 428 +#define IMX8MQ_CLK_HDMI_ROOT 429 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 430 +#define IMX8MQ_CLK_VPU_DEC_ROOT 431 +#define IMX8MQ_CLK_CSI1_ROOT 432 +#define IMX8MQ_CLK_CSI2_ROOT 433 +#define IMX8MQ_CLK_RAWNAND_ROOT 434 +#define IMX8MQ_CLK_SDMA1_ROOT 435 +#define IMX8MQ_CLK_SDMA2_ROOT 436 +#define IMX8MQ_CLK_VPU_G1_ROOT 437 +#define IMX8MQ_CLK_VPU_G2_ROOT 438 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 439 +#define IMX8MQ_SYS2_PLL_OUT 440 +#define IMX8MQ_SYS3_PLL_OUT 441 +#define IMX8MQ_DRAM_PLL_OUT 442 + +#define IMX8MQ_GPT_3M_CLK 443 + +#define IMX8MQ_CLK_IPG_ROOT 444 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 445 +#define IMX8MQ_CLK_SAI1_IPG 446 +#define IMX8MQ_CLK_SAI2_IPG 447 +#define IMX8MQ_CLK_SAI3_IPG 448 +#define IMX8MQ_CLK_SAI4_IPG 449 +#define IMX8MQ_CLK_SAI5_IPG 450 +#define IMX8MQ_CLK_SAI6_IPG 451 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 452 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 453 + +/* VIDEO2 PLL */ +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 454 +#define IMX8MQ_VIDEO2_PLL1_REF_DIV 455 +#define IMX8MQ_VIDEO2_PLL1 456 +#define IMX8MQ_VIDEO2_PLL1_OUT 457 +#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 458 +#define IMX8MQ_VIDEO2_PLL2 459 +#define IMX8MQ_VIDEO2_PLL2_DIV 460 +#define IMX8MQ_VIDEO2_PLL2_OUT 461 +#define IMX8MQ_CLK_TMU_ROOT 462 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 463 +#define IMX8MQ_CLK_DISP_APB_ROOT 464 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 465 + +#define IMX8MQ_CLK_OCOTP_ROOT 476 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 477 +#define IMX8MQ_CLK_DRAM_CORE 478 + +#define IMX8MQ_CLK_MU_ROOT 479 +#define IMX8MQ_VIDEO2_PLL_OUT 480 + +#define IMX8MQ_CLK_CLKO2 481 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 482 + +#define IMX8MQ_CLK_END 483 +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v6 2/5] clk: imx: add fractional PLL output clock 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa 2018-08-22 13:48 ` [PATCH v6 1/5] dt-bindings: add binding for i.MX8MQ CCM Abel Vesa @ 2018-08-22 13:48 ` Abel Vesa 2018-08-22 13:48 ` [PATCH v6 3/5] clk: imx: add SCCG PLL type Abel Vesa ` (2 subsequent siblings) 4 siblings, 0 replies; 15+ messages in thread From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw) To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa, Abel Vesa From: Lucas Stach <l.stach@pengutronix.de> This is a new clock type introduced on i.MX8. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-frac-pll.c | 230 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 3 + 3 files changed, 234 insertions(+) create mode 100644 drivers/clk/imx/clk-frac-pll.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 8c3baa7..4893c1f 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -6,6 +6,7 @@ obj-y += \ clk-cpu.o \ clk-fixup-div.o \ clk-fixup-mux.o \ + clk-frac-pll.o \ clk-gate-exclusive.o \ clk-gate2.o \ clk-pllv1.o \ diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c new file mode 100644 index 0000000..c80c6ed --- /dev/null +++ b/drivers/clk/imx/clk-frac-pll.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP. + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/jiffies.h> +#include <linux/slab.h> + +#include "clk.h" + +#define PLL_CFG0 0x0 +#define PLL_CFG1 0x4 + +#define PLL_LOCK_STATUS BIT(31) +#define PLL_PD 19 +#define PLL_PD_MASK BIT(PLL_PD) +#define PLL_BYPASS 14 +#define PLL_BYPASS_MASK BIT(PLL_BYPASS) +#define PLL_NEWDIV_VAL BIT(12) +#define PLL_NEWDIV_ACK BIT(11) +#define PLL_FRAC_DIV_MASK 0xffffff +#define PLL_INT_DIV_MASK 0x7f +#define PLL_OUTPUT_DIV_MASK 0x1f +#define PLL_FRAC_DENOM 0x1000000 + +struct clk_frac_pll { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw) + +static int clk_wait_lock(struct clk_frac_pll *pll) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(10); + u32 val; + + /* Wait for PLL to lock */ + do { + if (readl_relaxed(pll->base) & PLL_LOCK_STATUS) + break; + if (time_after(jiffies, timeout)) + break; + } while (1); + + return readl_poll_timeout(pll->base, val, + val & PLL_LOCK_STATUS, 0, 1000); +} + +static int clk_wait_ack(struct clk_frac_pll *pll) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(50); + u32 val; + + /* return directly if the pll is in powerdown or in bypass */ + if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) + return 0; + + /* Wait for the pll's divfi and divff to be reloaded */ + do { + if (readl_relaxed(pll->base) & PLL_NEWDIV_ACK) + break; + if (time_after(jiffies, timeout)) + break; + } while (1); + + return readl_poll_timeout(pll->base, val, + val & PLL_NEWDIV_ACK, 0, 1000); +} + +static int clk_pll_prepare(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + + return clk_wait_lock(pll); +} + +static void clk_pll_unprepare(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); +} + +static int clk_pll_is_prepared(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + return (val & PLL_PD_MASK) ? 0 : 1; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val, divff, divfi, divq; + u64 temp64; + + val = readl_relaxed(pll->base + PLL_CFG0); + divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2; + val = readl_relaxed(pll->base + PLL_CFG1); + divff = (val >> 7) & PLL_FRAC_DIV_MASK; + divfi = (val & PLL_INT_DIV_MASK); + + temp64 = (u64)parent_rate * 8; + temp64 *= divff; + do_div(temp64, PLL_FRAC_DENOM); + temp64 /= divq; + + return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64; +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + u32 divff, divfi; + u64 temp64; + + parent_rate *= 8; + rate *= 2; + divfi = rate / parent_rate; + temp64 = (u64)(rate - divfi * parent_rate); + temp64 *= PLL_FRAC_DENOM; + do_div(temp64, parent_rate); + divff = temp64; + + temp64 = (u64)parent_rate; + temp64 *= divff; + do_div(temp64, PLL_FRAC_DENOM); + + return (parent_rate * divfi + (unsigned long)temp64) / 2; +} + +/* + * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero + * (means the PLL output will be divided by 2). So the PLL output can use + * the below formula: + * pllout = parent_rate * 8 / 2 * DIVF_VAL; + * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24. + */ +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val, divfi, divff; + u64 temp64; + int ret; + + parent_rate *= 8; + rate *= 2; + divfi = rate / parent_rate; + temp64 = (u64) (rate - divfi * parent_rate); + temp64 *= PLL_FRAC_DENOM; + do_div(temp64, parent_rate); + divff = temp64; + + val = readl_relaxed(pll->base + PLL_CFG1); + val &= ~((PLL_FRAC_DIV_MASK << 7) | (PLL_INT_DIV_MASK)); + val |= ((divff << 7) | (divfi - 1)); + writel_relaxed(val, pll->base + PLL_CFG1); + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~0x1f; + writel_relaxed(val, pll->base + PLL_CFG0); + + /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */ + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + ret = clk_wait_ack(pll); + + /* clear the NEV_DIV_VAL */ + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + return ret; +} + +static const struct clk_ops clk_frac_pll_ops = { + .prepare = clk_pll_prepare, + .unprepare = clk_pll_unprepare, + .is_prepared = clk_pll_is_prepared, + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, + .set_rate = clk_pll_set_rate, +}; + +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base) +{ + struct clk_init_data init; + struct clk_frac_pll *pll; + struct clk *clk; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + init.name = name; + init.ops = &clk_frac_pll_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 8076ec0..13daf1c 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -27,6 +27,9 @@ struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, struct clk *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base); + enum imx_pllv3_type { IMX_PLLV3_GENERIC, IMX_PLLV3_SYS, -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa 2018-08-22 13:48 ` [PATCH v6 1/5] dt-bindings: add binding for i.MX8MQ CCM Abel Vesa 2018-08-22 13:48 ` [PATCH v6 2/5] clk: imx: add fractional PLL output clock Abel Vesa @ 2018-08-22 13:48 ` Abel Vesa 2018-08-24 7:40 ` Sascha Hauer 2018-08-28 18:47 ` Andrey Smirnov 2018-08-22 13:48 ` [PATCH v6 4/5] clk: imx: add imx composite clock Abel Vesa 2018-08-22 13:48 ` [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa 4 siblings, 2 replies; 15+ messages in thread From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw) To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa, Abel Vesa From: Lucas Stach <l.stach@pengutronix.de> The SCCG is a new PLL type introduced on i.MX8. Add support for this. The driver currently misses the PLL lock check, as the preliminary documentation mentions lock configurations, but is quiet about where to find the actual lock status signal. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-sccg-pll.c | 231 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 ++ 3 files changed, 242 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-sccg-pll.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 4893c1f..b87513c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -12,7 +12,8 @@ obj-y += \ clk-pllv1.o \ clk-pllv2.o \ clk-pllv3.o \ - clk-pfd.o + clk-pfd.o \ + clk-sccg-pll.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c new file mode 100644 index 0000000..886ae03 --- /dev/null +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 NXP. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include "clk.h" + +/* PLL CFGs */ +#define PLL_CFG0 0x0 +#define PLL_CFG1 0x4 +#define PLL_CFG2 0x8 + +#define PLL_DIVF1_SHIFT 13 +#define PLL_DIVF2_SHIFT 7 +#define PLL_DIVF_MASK 0x3f + +#define PLL_DIVR1_SHIFT 25 +#define PLL_DIVR2_SHIFT 19 +#define PLL_DIVR1_MASK 0x3 +#define PLL_DIVR2_MASK 0x3f +#define PLL_REF_SHIFT 0 +#define PLL_REF_MASK 0x3 + +#define PLL_LOCK 31 +#define PLL_PD 7 + +#define OSC_25M 25000000 +#define OSC_27M 27000000 + +struct clk_sccg_pll { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw) + +static int clk_pll1_is_prepared(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + return (val & (1 << PLL_PD)) ? 0 : 1; +} + +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val, divf; + + val = readl_relaxed(pll->base + PLL_CFG2); + divf = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; + + return parent_rate * 2 * (divf + 1); +} + +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + u32 div; + + div = rate / (parent_rate * 2); + + return parent_rate * div * 2; +} + +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + u32 divf; + + divf = rate / (parent_rate * 2); + + val = readl_relaxed(pll->base + PLL_CFG2); + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); + val |= (divf - 1) << PLL_DIVF1_SHIFT; + writel_relaxed(val, pll->base + PLL_CFG2); + + /* FIXME: PLL lock check */ + + return 0; +} + +static int clk_pll1_prepare(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base); + val &= ~(1 << PLL_PD); + writel_relaxed(val, pll->base); + + /* FIXME: PLL lock check */ + + return 0; +} + +static void clk_pll1_unprepare(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base); + val |= (1 << PLL_PD); + writel_relaxed(val, pll->base); +} + +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val, ref, divr1, divf1, divr2, divf2; + u64 temp64; + + val = readl_relaxed(pll->base + PLL_CFG0); + switch ((val >> PLL_REF_SHIFT) & PLL_REF_MASK) { + case 0: + ref = OSC_25M; + break; + case 1: + ref = OSC_27M; + break; + default: + ref = OSC_25M; + break; + } + + val = readl_relaxed(pll->base + PLL_CFG2); + divr1 = (val >> PLL_DIVR1_SHIFT) & PLL_DIVR1_MASK; + divr2 = (val >> PLL_DIVR2_SHIFT) & PLL_DIVR2_MASK; + divf1 = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; + divf2 = (val >> PLL_DIVF2_SHIFT) & PLL_DIVF_MASK; + + temp64 = ref * 2; + temp64 *= (divf1 + 1) * (divf2 + 1); + + do_div(temp64, (divr1 + 1) * (divr2 + 1)); + + return (unsigned long)temp64; +} + +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 div; + unsigned long parent_rate = *prate; + + div = rate / (parent_rate); + + return parent_rate * div; +} + +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + u32 val; + u32 divf; + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + + divf = rate / (parent_rate); + + val = readl_relaxed(pll->base + PLL_CFG2); + val &= ~(PLL_DIVF_MASK << PLL_DIVF2_SHIFT); + val |= (divf - 1) << PLL_DIVF2_SHIFT; + writel_relaxed(val, pll->base + PLL_CFG2); + + /* FIXME: PLL lock check */ + + return 0; +} + +static const struct clk_ops clk_sccg_pll1_ops = { + .is_prepared = clk_pll1_is_prepared, + .recalc_rate = clk_pll1_recalc_rate, + .round_rate = clk_pll1_round_rate, + .set_rate = clk_pll1_set_rate, +}; + +static const struct clk_ops clk_sccg_pll2_ops = { + .prepare = clk_pll1_prepare, + .unprepare = clk_pll1_unprepare, + .recalc_rate = clk_pll2_recalc_rate, + .round_rate = clk_pll2_round_rate, + .set_rate = clk_pll2_set_rate, +}; + +struct clk *imx_clk_sccg_pll(const char *name, + const char *parent_name, + void __iomem *base, + enum imx_sccg_pll_type pll_type) +{ + struct clk_sccg_pll *pll; + struct clk *clk; + struct clk_init_data init; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + init.name = name; + switch (pll_type) { + case SCCG_PLL1: + init.ops = &clk_sccg_pll1_ops; + break; + case SCCG_PLL2: + init.ops = &clk_sccg_pll2_ops; + break; + } + + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 13daf1c..12b3fd6 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -21,6 +21,11 @@ enum imx_pllv1_type { IMX_PLLV1_IMX35, }; +enum imx_sccg_pll_type { + SCCG_PLL1, + SCCG_PLL2, +}; + struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base); @@ -30,6 +35,10 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent, struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, void __iomem *base); +struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, + void __iomem *base, + enum imx_sccg_pll_type pll_type); + enum imx_pllv3_type { IMX_PLLV3_GENERIC, IMX_PLLV3_SYS, -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-22 13:48 ` [PATCH v6 3/5] clk: imx: add SCCG PLL type Abel Vesa @ 2018-08-24 7:40 ` Sascha Hauer 2018-08-28 10:58 ` Abel Vesa 2018-08-28 18:47 ` Andrey Smirnov 1 sibling, 1 reply; 15+ messages in thread From: Sascha Hauer @ 2018-08-24 7:40 UTC (permalink / raw) To: Abel Vesa Cc: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, devicetree, Stephen Boyd, Michael Turquette, linux-kernel, Abel Vesa, linux-imx, Shawn Guo, linux-clk, Andrey Smirnov +Cc Andrey Smirnov who made me aware of this issue. On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > The driver currently misses the PLL lock check, as the preliminary > documentation mentions lock configurations, but is quiet about where > to find the actual lock status signal. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + u32 divf; > + > + divf = rate / (parent_rate * 2); > + > + val = readl_relaxed(pll->base + PLL_CFG2); > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > + writel_relaxed(val, pll->base + PLL_CFG2); > + > + /* FIXME: PLL lock check */ Shouldn't be too hard to add, no? > + > + return 0; > +} > + > +static int clk_pll1_prepare(struct clk_hw *hw) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + > + val = readl_relaxed(pll->base); > + val &= ~(1 << PLL_PD); > + writel_relaxed(val, pll->base); pll->base + PLL_CFG0 please. > +static const struct clk_ops clk_sccg_pll1_ops = { > + .is_prepared = clk_pll1_is_prepared, > + .recalc_rate = clk_pll1_recalc_rate, > + .round_rate = clk_pll1_round_rate, > + .set_rate = clk_pll1_set_rate, > +}; > + > +static const struct clk_ops clk_sccg_pll2_ops = { > + .prepare = clk_pll1_prepare, > + .unprepare = clk_pll1_unprepare, > + .recalc_rate = clk_pll2_recalc_rate, > + .round_rate = clk_pll2_round_rate, > + .set_rate = clk_pll2_set_rate, > +}; So these are two PLLs that share the same enable register. Doing the prepare/unprepare for only one PLL can lead to all kinds of trouble. Finding a good abstraction the properly handles this case with the clock framework is probably also not easy. I could imagine we'll need to track the enable state on both PLLs and only if both are disabled we disable it in hardware. With the current code we disable the PLLs when all consumers are reparented to pll1, which probably has bad effects. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-24 7:40 ` Sascha Hauer @ 2018-08-28 10:58 ` Abel Vesa 2018-08-28 19:11 ` Andrey Smirnov 0 siblings, 1 reply; 15+ messages in thread From: Abel Vesa @ 2018-08-28 10:58 UTC (permalink / raw) To: Sascha Hauer Cc: Lucas Stach, Sascha Hauer, A.s. Dong, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, devicetree, Stephen Boyd, Michael Turquette, linux-kernel, Abel Vesa, dl-linux-imx, Shawn Guo, linux-clk, Andrey Smirnov On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > +Cc Andrey Smirnov who made me aware of this issue. > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > > The driver currently misses the PLL lock check, as the preliminary > > documentation mentions lock configurations, but is quiet about where > > to find the actual lock status signal. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > --- > > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long parent_rate) > > +{ > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > + u32 val; > > + u32 divf; > > + > > + divf = rate / (parent_rate * 2); > > + > > + val = readl_relaxed(pll->base + PLL_CFG2); > > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > > + writel_relaxed(val, pll->base + PLL_CFG2); > > + > > + /* FIXME: PLL lock check */ > > Shouldn't be too hard to add, no? Added to the next version which I intend to send today. > > > + > > + return 0; > > +} > > + > > +static int clk_pll1_prepare(struct clk_hw *hw) > > +{ > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > + u32 val; > > + > > + val = readl_relaxed(pll->base); > > + val &= ~(1 << PLL_PD); > > + writel_relaxed(val, pll->base); > > pll->base + PLL_CFG0 please. Same as above. > > > +static const struct clk_ops clk_sccg_pll1_ops = { > > + .is_prepared = clk_pll1_is_prepared, > > + .recalc_rate = clk_pll1_recalc_rate, > > + .round_rate = clk_pll1_round_rate, > > + .set_rate = clk_pll1_set_rate, > > +}; > > + > > +static const struct clk_ops clk_sccg_pll2_ops = { > > + .prepare = clk_pll1_prepare, > > + .unprepare = clk_pll1_unprepare, > > + .recalc_rate = clk_pll2_recalc_rate, > > + .round_rate = clk_pll2_round_rate, > > + .set_rate = clk_pll2_set_rate, > > +}; > > So these are two PLLs that share the same enable register. Doing the > prepare/unprepare for only one PLL can lead to all kinds of trouble. > Finding a good abstraction the properly handles this case with the > clock framework is probably also not easy. > > I could imagine we'll need to track the enable state on both PLLs and > only if both are disabled we disable it in hardware. > > With the current code we disable the PLLs when all consumers are > reparented to pll1, which probably has bad effects. > So it took me a while to understand exactly why this needs to stay like it is. The PLL1 is never used by any device, instead it is used as a source for PLL2. But because the interlink between the two of them is too complicated, the PLLs 1 and 2 need to be separate clocks. As for the disabling, it's safe to disable just the second one because, as mentioned above, the first PLL is never used alone by a device. If there isn't anything else here to discuss, I would like to send the next version of this patchset with all the other comments taken care of. Abel > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&data=02%7C01%7Cabel.vesa%40nxp.com%7C5e9c7c6f9e464ed522f108d60994d471%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636706932168087639&sdata=XbfFq5z%2FRtkq6yGgwSyk6dNCZVuXOzY%2Fiygmwle3C2I%3D&reserved=0 | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-28 10:58 ` Abel Vesa @ 2018-08-28 19:11 ` Andrey Smirnov 2018-09-04 13:13 ` Abel Vesa 0 siblings, 1 reply; 15+ messages in thread From: Andrey Smirnov @ 2018-08-28 19:11 UTC (permalink / raw) To: Abel Vesa Cc: Sascha Hauer, Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, sboyd, Michael Turquette, linux-kernel, abelvesa, linux-imx, Shawn Guo, linux-clk On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > > +Cc Andrey Smirnov who made me aware of this issue. > > > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > > > From: Lucas Stach <l.stach@pengutronix.de> > > > > > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > > > The driver currently misses the PLL lock check, as the preliminary > > > documentation mentions lock configurations, but is quiet about where > > > to find the actual lock status signal. > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > --- > > > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > > > + unsigned long parent_rate) > > > +{ > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > + u32 val; > > > + u32 divf; > > > + > > > + divf = rate / (parent_rate * 2); > > > + > > > + val = readl_relaxed(pll->base + PLL_CFG2); > > > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > > > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > > > + writel_relaxed(val, pll->base + PLL_CFG2); > > > + > > > + /* FIXME: PLL lock check */ > > > > Shouldn't be too hard to add, no? > > Added to the next version which I intend to send today. > > > > > > + > > > + return 0; > > > +} > > > + > > > +static int clk_pll1_prepare(struct clk_hw *hw) > > > +{ > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > + u32 val; > > > + > > > + val = readl_relaxed(pll->base); > > > + val &= ~(1 << PLL_PD); > > > + writel_relaxed(val, pll->base); > > > > pll->base + PLL_CFG0 please. > > Same as above. > > > > > > +static const struct clk_ops clk_sccg_pll1_ops = { > > > + .is_prepared = clk_pll1_is_prepared, > > > + .recalc_rate = clk_pll1_recalc_rate, > > > + .round_rate = clk_pll1_round_rate, > > > + .set_rate = clk_pll1_set_rate, > > > +}; > > > + > > > +static const struct clk_ops clk_sccg_pll2_ops = { > > > + .prepare = clk_pll1_prepare, > > > + .unprepare = clk_pll1_unprepare, > > > + .recalc_rate = clk_pll2_recalc_rate, > > > + .round_rate = clk_pll2_round_rate, > > > + .set_rate = clk_pll2_set_rate, > > > +}; > > > > So these are two PLLs that share the same enable register. Doing the > > prepare/unprepare for only one PLL can lead to all kinds of trouble. > > Finding a good abstraction the properly handles this case with the > > clock framework is probably also not easy. > > > > I could imagine we'll need to track the enable state on both PLLs and > > only if both are disabled we disable it in hardware. > > > > With the current code we disable the PLLs when all consumers are > > reparented to pll1, which probably has bad effects. > > > > So it took me a while to understand exactly why this needs to stay like it is. > IMHO this means that, if nothing else, all of the below should be documented in code as a comment, otherwise simpletons like me are going to continue stumbling over it and wondering what's going on. > The PLL1 is never used by any device, instead it is used as a source for PLL2. > > But because the interlink between the two of them is too complicated, > the PLLs 1 and 2 need to be separate clocks. > Can you go a little bit more into detail as for why PLL1 needs to be exposed in the first place and can't just be dealt with behind the scenes as a part of PLL2 abstraction? Are there use-cases where the rates of the two are going to be adjusted individually in Linux? Thanks, Andrey Smirnov ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-28 19:11 ` Andrey Smirnov @ 2018-09-04 13:13 ` Abel Vesa 2018-09-04 19:30 ` Andrey Smirnov 0 siblings, 1 reply; 15+ messages in thread From: Abel Vesa @ 2018-09-04 13:13 UTC (permalink / raw) To: Andrey Smirnov Cc: Sascha Hauer, Lucas Stach, Sascha Hauer, A.s. Dong, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, sboyd, Michael Turquette, linux-kernel, abelvesa, dl-linux-imx, Shawn Guo, linux-clk On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote: > On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > > > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > > > +Cc Andrey Smirnov who made me aware of this issue. > > > > > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > > > > From: Lucas Stach <l.stach@pengutronix.de> > > > > > > > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > > > > The driver currently misses the PLL lock check, as the preliminary > > > > documentation mentions lock configurations, but is quiet about where > > > > to find the actual lock status signal. > > > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > > --- > > > > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > > > > + unsigned long parent_rate) > > > > +{ > > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > > + u32 val; > > > > + u32 divf; > > > > + > > > > + divf = rate / (parent_rate * 2); > > > > + > > > > + val = readl_relaxed(pll->base + PLL_CFG2); > > > > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > > > > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > > > > + writel_relaxed(val, pll->base + PLL_CFG2); > > > > + > > > > + /* FIXME: PLL lock check */ > > > > > > Shouldn't be too hard to add, no? > > > > Added to the next version which I intend to send today. > > > > > > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +static int clk_pll1_prepare(struct clk_hw *hw) > > > > +{ > > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > > + u32 val; > > > > + > > > > + val = readl_relaxed(pll->base); > > > > + val &= ~(1 << PLL_PD); > > > > + writel_relaxed(val, pll->base); > > > > > > pll->base + PLL_CFG0 please. > > > > Same as above. > > > > > > > > > +static const struct clk_ops clk_sccg_pll1_ops = { > > > > + .is_prepared = clk_pll1_is_prepared, > > > > + .recalc_rate = clk_pll1_recalc_rate, > > > > + .round_rate = clk_pll1_round_rate, > > > > + .set_rate = clk_pll1_set_rate, > > > > +}; > > > > + > > > > +static const struct clk_ops clk_sccg_pll2_ops = { > > > > + .prepare = clk_pll1_prepare, > > > > + .unprepare = clk_pll1_unprepare, > > > > + .recalc_rate = clk_pll2_recalc_rate, > > > > + .round_rate = clk_pll2_round_rate, > > > > + .set_rate = clk_pll2_set_rate, > > > > +}; > > > > > > So these are two PLLs that share the same enable register. Doing the > > > prepare/unprepare for only one PLL can lead to all kinds of trouble. > > > Finding a good abstraction the properly handles this case with the > > > clock framework is probably also not easy. > > > > > > I could imagine we'll need to track the enable state on both PLLs and > > > only if both are disabled we disable it in hardware. > > > > > > With the current code we disable the PLLs when all consumers are > > > reparented to pll1, which probably has bad effects. > > > > > > > So it took me a while to understand exactly why this needs to stay like it is. > > > > IMHO this means that, if nothing else, all of the below should be > documented in code as a comment, otherwise simpletons like me are > going to continue stumbling over it and wondering what's going on. Will try to add proper comment to explain what's happening. > > > The PLL1 is never used by any device, instead it is used as a source for PLL2. > > > > But because the interlink between the two of them is too complicated, > > the PLLs 1 and 2 need to be separate clocks. > > > > Can you go a little bit more into detail as for why PLL1 needs to be > exposed in the first place and can't just be dealt with behind the > scenes as a part of PLL2 abstraction? Are there use-cases where the > rates of the two are going to be adjusted individually in Linux? > Here is the SCCG PLL Block Diagram: https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 Now lets take the System PLL 2 for example. If you follow the hierarchy, when you reach the sys2_pll1_out you can see that one of its selectors is actually sys1_pll1_ref_sel. Same thing applies to sys3_pll2_out with sys2_pll1_ref_sel. This means there is an input reference clock interlinking between different System PLLs. > Thanks, > Andrey Smirnov -- ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-09-04 13:13 ` Abel Vesa @ 2018-09-04 19:30 ` Andrey Smirnov 0 siblings, 0 replies; 15+ messages in thread From: Andrey Smirnov @ 2018-09-04 19:30 UTC (permalink / raw) To: Abel Vesa Cc: Sascha Hauer, Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, sboyd, Michael Turquette, linux-kernel, abelvesa, linux-imx, Shawn Guo, linux-clk On Tue, Sep 4, 2018 at 6:13 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote: > > On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > > > > > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote: > > > > +Cc Andrey Smirnov who made me aware of this issue. > > > > > > > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, Abel Vesa wrote: > > > > > From: Lucas Stach <l.stach@pengutronix.de> > > > > > > > > > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > > > > > The driver currently misses the PLL lock check, as the preliminary > > > > > documentation mentions lock configurations, but is quiet about where > > > > > to find the actual lock status signal. > > > > > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > > > --- > > > > > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > > > > > + unsigned long parent_rate) > > > > > +{ > > > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > > > + u32 val; > > > > > + u32 divf; > > > > > + > > > > > + divf = rate / (parent_rate * 2); > > > > > + > > > > > + val = readl_relaxed(pll->base + PLL_CFG2); > > > > > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > > > > > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > > > > > + writel_relaxed(val, pll->base + PLL_CFG2); > > > > > + > > > > > + /* FIXME: PLL lock check */ > > > > > > > > Shouldn't be too hard to add, no? > > > > > > Added to the next version which I intend to send today. > > > > > > > > > > > > + > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static int clk_pll1_prepare(struct clk_hw *hw) > > > > > +{ > > > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > > > > > + u32 val; > > > > > + > > > > > + val = readl_relaxed(pll->base); > > > > > + val &= ~(1 << PLL_PD); > > > > > + writel_relaxed(val, pll->base); > > > > > > > > pll->base + PLL_CFG0 please. > > > > > > Same as above. > > > > > > > > > > > > +static const struct clk_ops clk_sccg_pll1_ops = { > > > > > + .is_prepared = clk_pll1_is_prepared, > > > > > + .recalc_rate = clk_pll1_recalc_rate, > > > > > + .round_rate = clk_pll1_round_rate, > > > > > + .set_rate = clk_pll1_set_rate, > > > > > +}; > > > > > + > > > > > +static const struct clk_ops clk_sccg_pll2_ops = { > > > > > + .prepare = clk_pll1_prepare, > > > > > + .unprepare = clk_pll1_unprepare, > > > > > + .recalc_rate = clk_pll2_recalc_rate, > > > > > + .round_rate = clk_pll2_round_rate, > > > > > + .set_rate = clk_pll2_set_rate, > > > > > +}; > > > > > > > > So these are two PLLs that share the same enable register. Doing the > > > > prepare/unprepare for only one PLL can lead to all kinds of trouble. > > > > Finding a good abstraction the properly handles this case with the > > > > clock framework is probably also not easy. > > > > > > > > I could imagine we'll need to track the enable state on both PLLs and > > > > only if both are disabled we disable it in hardware. > > > > > > > > With the current code we disable the PLLs when all consumers are > > > > reparented to pll1, which probably has bad effects. > > > > > > > > > > So it took me a while to understand exactly why this needs to stay like it is. > > > > > > > IMHO this means that, if nothing else, all of the below should be > > documented in code as a comment, otherwise simpletons like me are > > going to continue stumbling over it and wondering what's going on. > > Will try to add proper comment to explain what's happening. > > > > > > The PLL1 is never used by any device, instead it is used as a source for PLL2. > > > > > > But because the interlink between the two of them is too complicated, > > > the PLLs 1 and 2 need to be separate clocks. > > > > > > > Can you go a little bit more into detail as for why PLL1 needs to be > > exposed in the first place and can't just be dealt with behind the > > scenes as a part of PLL2 abstraction? Are there use-cases where the > > rates of the two are going to be adjusted individually in Linux? > > > > Here is the SCCG PLL Block Diagram: > > https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 > > Now lets take the System PLL 2 for example. If you follow the hierarchy, > when you reach the sys2_pll1_out you can see that one of its selectors is > actually sys1_pll1_ref_sel. Same thing applies to sys3_pll2_out with > sys2_pll1_ref_sel. This means there is an input reference clock interlinking > between different System PLLs. > Hmm, I am not sure I see how this would prevent you from treating a PLL pair as a black box, but OTOH, doing that probably wouldn't result cleaner or simpler code. IMHO, it's unfortunate that PD bit is shared between the two clocks, but if PLL1 could only be ever connected to corresponding PLL2, then my concerns were probably misguided and current implementation is good enough. Thanks, Andrey Smirnov ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 3/5] clk: imx: add SCCG PLL type 2018-08-22 13:48 ` [PATCH v6 3/5] clk: imx: add SCCG PLL type Abel Vesa 2018-08-24 7:40 ` Sascha Hauer @ 2018-08-28 18:47 ` Andrey Smirnov 1 sibling, 0 replies; 15+ messages in thread From: Andrey Smirnov @ 2018-08-28 18:47 UTC (permalink / raw) To: Abel Vesa Cc: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, linux-clk, linux-imx, Shawn Guo, Michael Turquette, sboyd, Rob Herring, Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, abelvesa On Wed, Aug 22, 2018 at 6:52 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > From: Lucas Stach <l.stach@pengutronix.de> > > The SCCG is a new PLL type introduced on i.MX8. Add support for this. > The driver currently misses the PLL lock check, as the preliminary > documentation mentions lock configurations, but is quiet about where > to find the actual lock status signal. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/Makefile | 3 +- > drivers/clk/imx/clk-sccg-pll.c | 231 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/imx/clk.h | 9 ++ > 3 files changed, 242 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/imx/clk-sccg-pll.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 4893c1f..b87513c 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -12,7 +12,8 @@ obj-y += \ > clk-pllv1.o \ > clk-pllv2.o \ > clk-pllv3.o \ > - clk-pfd.o > + clk-pfd.o \ > + clk-sccg-pll.o > > obj-$(CONFIG_SOC_IMX1) += clk-imx1.o > obj-$(CONFIG_SOC_IMX21) += clk-imx21.o > diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c > new file mode 100644 > index 0000000..886ae03 > --- /dev/null > +++ b/drivers/clk/imx/clk-sccg-pll.c > @@ -0,0 +1,231 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright 2018 NXP. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/slab.h> > + > +#include "clk.h" > + > +/* PLL CFGs */ > +#define PLL_CFG0 0x0 > +#define PLL_CFG1 0x4 > +#define PLL_CFG2 0x8 > + > +#define PLL_DIVF1_SHIFT 13 > +#define PLL_DIVF2_SHIFT 7 > +#define PLL_DIVF_MASK 0x3f > + > +#define PLL_DIVR1_SHIFT 25 > +#define PLL_DIVR2_SHIFT 19 > +#define PLL_DIVR1_MASK 0x3 > +#define PLL_DIVR2_MASK 0x3f > +#define PLL_REF_SHIFT 0 > +#define PLL_REF_MASK 0x3 > + > +#define PLL_LOCK 31 > +#define PLL_PD 7 > + > +#define OSC_25M 25000000 > +#define OSC_27M 27000000 > + > +struct clk_sccg_pll { > + struct clk_hw hw; > + void __iomem *base; > +}; > + > +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw) > + > +static int clk_pll1_is_prepared(struct clk_hw *hw) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + > + val = readl_relaxed(pll->base + PLL_CFG0); > + return (val & (1 << PLL_PD)) ? 0 : 1; > +} > + > +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val, divf; > + > + val = readl_relaxed(pll->base + PLL_CFG2); > + divf = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; > + > + return parent_rate * 2 * (divf + 1); > +} > + > +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *prate) > +{ > + unsigned long parent_rate = *prate; > + u32 div; > + > + div = rate / (parent_rate * 2); > + > + return parent_rate * div * 2; > +} > + > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + u32 divf; > + > + divf = rate / (parent_rate * 2); > + > + val = readl_relaxed(pll->base + PLL_CFG2); > + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); > + val |= (divf - 1) << PLL_DIVF1_SHIFT; > + writel_relaxed(val, pll->base + PLL_CFG2); > + > + /* FIXME: PLL lock check */ > + > + return 0; > +} > + > +static int clk_pll1_prepare(struct clk_hw *hw) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + > + val = readl_relaxed(pll->base); > + val &= ~(1 << PLL_PD); > + writel_relaxed(val, pll->base); > + > + /* FIXME: PLL lock check */ > + > + return 0; > +} > + > +static void clk_pll1_unprepare(struct clk_hw *hw) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val; > + > + val = readl_relaxed(pll->base); > + val |= (1 << PLL_PD); > + writel_relaxed(val, pll->base); > +} > + > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + u32 val, ref, divr1, divf1, divr2, divf2; > + u64 temp64; > + > + val = readl_relaxed(pll->base + PLL_CFG0); > + switch ((val >> PLL_REF_SHIFT) & PLL_REF_MASK) { > + case 0: > + ref = OSC_25M; > + break; > + case 1: > + ref = OSC_27M; > + break; > + default: > + ref = OSC_25M; > + break; > + } > + > + val = readl_relaxed(pll->base + PLL_CFG2); > + divr1 = (val >> PLL_DIVR1_SHIFT) & PLL_DIVR1_MASK; > + divr2 = (val >> PLL_DIVR2_SHIFT) & PLL_DIVR2_MASK; > + divf1 = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; > + divf2 = (val >> PLL_DIVF2_SHIFT) & PLL_DIVF_MASK; > + > + temp64 = ref * 2; > + temp64 *= (divf1 + 1) * (divf2 + 1); > + > + do_div(temp64, (divr1 + 1) * (divr2 + 1)); > + > + return (unsigned long)temp64; > +} > + > +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *prate) > +{ > + u32 div; > + unsigned long parent_rate = *prate; > + > + div = rate / (parent_rate); > + > + return parent_rate * div; > +} > + > +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + u32 val; > + u32 divf; > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); > + > + divf = rate / (parent_rate); > + > + val = readl_relaxed(pll->base + PLL_CFG2); > + val &= ~(PLL_DIVF_MASK << PLL_DIVF2_SHIFT); > + val |= (divf - 1) << PLL_DIVF2_SHIFT; > + writel_relaxed(val, pll->base + PLL_CFG2); > + > + /* FIXME: PLL lock check */ > + > + return 0; > +} > + > +static const struct clk_ops clk_sccg_pll1_ops = { > + .is_prepared = clk_pll1_is_prepared, > + .recalc_rate = clk_pll1_recalc_rate, > + .round_rate = clk_pll1_round_rate, > + .set_rate = clk_pll1_set_rate, > +}; > + > +static const struct clk_ops clk_sccg_pll2_ops = { > + .prepare = clk_pll1_prepare, > + .unprepare = clk_pll1_unprepare, > + .recalc_rate = clk_pll2_recalc_rate, > + .round_rate = clk_pll2_round_rate, > + .set_rate = clk_pll2_set_rate, > +}; > + > +struct clk *imx_clk_sccg_pll(const char *name, > + const char *parent_name, > + void __iomem *base, > + enum imx_sccg_pll_type pll_type) > +{ > + struct clk_sccg_pll *pll; > + struct clk *clk; > + struct clk_init_data init; > + > + pll = kzalloc(sizeof(*pll), GFP_KERNEL); > + if (!pll) > + return ERR_PTR(-ENOMEM); > + > + pll->base = base; > + init.name = name; > + switch (pll_type) { > + case SCCG_PLL1: > + init.ops = &clk_sccg_pll1_ops; > + break; > + case SCCG_PLL2: > + init.ops = &clk_sccg_pll2_ops; > + break; > + } Please add error checking in the switch above since it's pretty clear that a wrong kind of argument can be passed as a pll_type without it being noticeable. Thanks, Andrey Smirnov ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 4/5] clk: imx: add imx composite clock 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa ` (2 preceding siblings ...) 2018-08-22 13:48 ` [PATCH v6 3/5] clk: imx: add SCCG PLL type Abel Vesa @ 2018-08-22 13:48 ` Abel Vesa 2018-08-24 7:43 ` Sascha Hauer 2018-08-22 13:48 ` [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa 4 siblings, 1 reply; 15+ messages in thread From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw) To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa, Abel Vesa Since a lot of clocks on imx8 are formed by a mux, gate, predivider and divider, the idea here is to combine all of those into one composite clock, but we need to deal with both predivider and divider at the same time and therefore we add the imx_clk_composite_divider_ops and register the composite clock with those. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite.c | 157 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 +++ 3 files changed, 167 insertions(+) create mode 100644 drivers/clk/imx/clk-composite.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b87513c..4fabb0a 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -3,6 +3,7 @@ obj-y += \ clk.o \ clk-busy.o \ + clk-composite.o \ clk-cpu.o \ clk-fixup-div.o \ clk-fixup-mux.o \ diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c new file mode 100644 index 0000000..a5c0080 --- /dev/null +++ b/drivers/clk/imx/clk-composite.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + */ + +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/clk-provider.h> +#include <linux/clk.h> + +#include "clk.h" + +#define PCG_PREDIV_SHIFT 16 +#define PCG_PREDIV_WIDTH 3 + +#define PCG_DIV_SHIFT 0 +#define PCG_DIV_WIDTH 6 + +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +#define PCG_CGC_SHIFT 28 + +static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + unsigned int prediv_value; + unsigned int div_value; + + prediv_value = clk_readl(divider->reg) >> divider->shift; + prediv_value &= clk_div_mask(divider->width); + + prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value, + divider->table, divider->flags, + divider->width); + + div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT; + div_value &= clk_div_mask(PCG_DIV_WIDTH); + + return divider_recalc_rate(hw, prediv_rate, div_value, divider->table, + divider->flags, PCG_DIV_WIDTH); +} + +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + + prediv_rate = divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); + return divider_round_rate(hw, rate, &prediv_rate, divider->table, + PCG_DIV_WIDTH, divider->flags); +} + +static int imx_clk_composite_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + unsigned long flags = 0; + int prediv_value; + int div_value; + u32 val; + + prediv_value = divider_get_val(rate, parent_rate, NULL, + PCG_PREDIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); + if (prediv_value < 0) + return prediv_value; + + prediv_rate = DIV_ROUND_UP_ULL((u64)parent_rate, prediv_value + 1); + + div_value = divider_get_val(rate, prediv_rate, NULL, + PCG_DIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); + if (div_value < 0) + return div_value; + + spin_lock_irqsave(divider->lock, flags); + + val = clk_readl(divider->reg); + val &= ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + + val |= (u32)prediv_value << divider->shift; + val |= (u32)div_value << PCG_DIV_SHIFT; + clk_writel(val, divider->reg); + + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +static const struct clk_ops imx_clk_composite_divider_ops = { + .recalc_rate = imx_clk_composite_divider_recalc_rate, + .round_rate = imx_clk_composite_divider_round_rate, + .set_rate = imx_clk_composite_divider_set_rate, +}; + +struct clk *imx_clk_composite_flags(const char *name, + const char **parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + struct clk *clk; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + mux_hw = &mux->hw; + mux->reg = reg; + mux->shift = PCG_PCS_SHIFT; + mux->mask = PCG_PCS_MASK; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + kfree(mux); + return ERR_PTR(-ENOMEM); + } + div_hw = &div->hw; + div->reg = reg; + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + div->lock = &imx_ccm_lock; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(mux); + kfree(div); + return ERR_PTR(-ENOMEM); + } + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + + flags |= CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ops, div_hw, + &imx_clk_composite_divider_ops, gate_hw, + &clk_gate_ops, flags); + if (IS_ERR(clk)) { + kfree(mux); + kfree(div); + kfree(gate); + } + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 12b3fd6..9dbb680 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -232,4 +232,13 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +struct clk *imx_clk_composite_flags(const char *name, const char **parent_names, + int num_parents, void __iomem *reg, unsigned long flags); + +#define imx_clk_composite(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, 0) + +#define imx_clk_composite_critical(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, CLK_IS_CRITICAL) + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v6 4/5] clk: imx: add imx composite clock 2018-08-22 13:48 ` [PATCH v6 4/5] clk: imx: add imx composite clock Abel Vesa @ 2018-08-24 7:43 ` Sascha Hauer 0 siblings, 0 replies; 15+ messages in thread From: Sascha Hauer @ 2018-08-24 7:43 UTC (permalink / raw) To: Abel Vesa Cc: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, devicetree, Stephen Boyd, Michael Turquette, linux-kernel, Abel Vesa, linux-imx, Shawn Guo, linux-clk On Wed, Aug 22, 2018 at 04:48:22PM +0300, Abel Vesa wrote: > Since a lot of clocks on imx8 are formed by a mux, gate, predivider and > divider, the idea here is to combine all of those into one composite clock, > but we need to deal with both predivider and divider at the same time and > therefore we add the imx_clk_composite_divider_ops and register the composite > clock with those. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-composite.c | 157 ++++++++++++++++++++++++++++++++++++++++ > drivers/clk/imx/clk.h | 9 +++ > 3 files changed, 167 insertions(+) > create mode 100644 drivers/clk/imx/clk-composite.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index b87513c..4fabb0a 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -3,6 +3,7 @@ > obj-y += \ > clk.o \ > clk-busy.o \ > + clk-composite.o \ > clk-cpu.o \ > clk-fixup-div.o \ > clk-fixup-mux.o \ > diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c > new file mode 100644 > index 0000000..a5c0080 > --- /dev/null > +++ b/drivers/clk/imx/clk-composite.c > @@ -0,0 +1,157 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2018 NXP > + */ > + > +#include <linux/errno.h> > +#include <linux/slab.h> > +#include <linux/clk-provider.h> > +#include <linux/clk.h> > + > +#include "clk.h" > + > +#define PCG_PREDIV_SHIFT 16 > +#define PCG_PREDIV_WIDTH 3 > + > +#define PCG_DIV_SHIFT 0 > +#define PCG_DIV_WIDTH 6 > + > +#define PCG_PCS_SHIFT 24 > +#define PCG_PCS_MASK 0x7 > + > +#define PCG_CGC_SHIFT 28 > + > +static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct clk_divider *divider = to_clk_divider(hw); > + unsigned long prediv_rate; > + unsigned int prediv_value; > + unsigned int div_value; > + > + prediv_value = clk_readl(divider->reg) >> divider->shift; > + prediv_value &= clk_div_mask(divider->width); > + > + prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value, > + divider->table, divider->flags, > + divider->width); > + > + div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT; > + div_value &= clk_div_mask(PCG_DIV_WIDTH); > + > + return divider_recalc_rate(hw, prediv_rate, div_value, divider->table, > + divider->flags, PCG_DIV_WIDTH); This is no table based divider, so divider->table is NULL, right? It's clearer to just write NULL here instead. Otherwise this looks good for me now. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa ` (3 preceding siblings ...) 2018-08-22 13:48 ` [PATCH v6 4/5] clk: imx: add imx composite clock Abel Vesa @ 2018-08-22 13:48 ` Abel Vesa 2018-08-24 7:58 ` Sascha Hauer 2018-08-28 18:45 ` Andrey Smirnov 4 siblings, 2 replies; 15+ messages in thread From: Abel Vesa @ 2018-08-22 13:48 UTC (permalink / raw) To: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang Cc: linux-clk, linux-imx, Shawn Guo, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, devicetree, linux-kernel, Abel Vesa, Abel Vesa From: Lucas Stach <l.stach@pengutronix.de> Add driver for the Clock Control Module found on i.MX8MQ. This is largely based on the downstream driver from Anson Huang and Bai Ping at NXP, with only some small adaptions to mainline from me. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx8mq.c | 631 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 36 +++ 3 files changed, 668 insertions(+) create mode 100644 drivers/clk/imx/clk-imx8mq.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 4fabb0a..64e695c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o +obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c new file mode 100644 index 0000000..d3a9e31 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mq.c @@ -0,0 +1,631 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP. + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#include <dt-bindings/clock/imx8mq-clock.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/types.h> + +#include "clk.h" + +static u32 share_count_sai1; +static u32 share_count_sai2; +static u32 share_count_sai3; +static u32 share_count_sai4; +static u32 share_count_sai5; +static u32 share_count_sai6; +static u32 share_count_dcss; +static u32 share_count_nand; + +static struct clk *clks[IMX8MQ_CLK_END]; + +static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; + +static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", }; +static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", }; +static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", }; +static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", }; +static const char *video2_pll1_out_sels[] = {"video2_pll1", "video2_pll1_ref_sel", }; + +static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", }; +static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", }; +static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", }; +static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", }; +static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref_sel", }; + +/* CCM ROOT */ +static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", }; + +static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", }; + +static const char *imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",}; + +static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m", + "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", }; + +static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m", + "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", }; + +static const char *imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", }; + +static const char *imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", }; + +static const char *imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", + "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; + +static const char *imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m", + "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m", + "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m", + "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m", + "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"}; + +static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m", + "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", }; + +static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; + +static const char *imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; + +static const char *imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; + +static const char *imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; + +static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", }; + +static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out", + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; + +static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; + +static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; + +static const char *imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; + +static const char *imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; + +static const char *imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m", + "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; + +static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", "video_pll1_out", }; + +static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m", + "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", }; + +static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m", + "sys1_pll_80m", "audio_pll1_out", "clk_ext1", }; + +static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out", + "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", }; + +static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m", + "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", }; + +static const char *imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", }; + +static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", }; + +static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out", + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; + +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; + +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out", + "video_pll1_out", "ckil", }; + +static int const clks_init_on[] __initconst = { + IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG, + IMX8MQ_CLK_NOC, IMX8MQ_CLK_NOC_APB, + IMX8MQ_CLK_USB_BUS, IMX8MQ_CLK_NAND_USDHC_BUS, + IMX8MQ_CLK_MAIN_AXI, IMX8MQ_CLK_A53_CG, + IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT, + IMX8MQ_CLK_DRAM_APB, +}; + +static struct clk_onecell_data clk_data; + +static void __init imx8mq_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + void __iomem *base; + int i; + + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil"); + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m"); + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m"); + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6); + clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6); + clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6); + clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6); + clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6); + clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6); + clks[IMX8MQ_SYS1_PLL1_REF_DIV] = imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3); + clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3); + clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3); + clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3); + clks[IMX8MQ_VIDEO2_PLL1_REF_DIV] = imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, 25, 3); + + clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); + clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); + clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); + clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0); + clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8); + clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10); + clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1); + clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1); + clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1); + clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1); + clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", "video2_pll1_ref_div", base + 0x5c, 3); + + clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2); + clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2); + clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2); + clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2); + clks[IMX8MQ_VIDEO2_PLL2] = imx_clk_sccg_pll("video2_pll2", "video2_pll1_out_div", base + 0x54, SCCG_PLL2); + + /* PLL divs */ + clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6); + clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6); + clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6); + clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6); + clks[IMX8MQ_VIDEO2_PLL1_OUT_DIV] = imx_clk_divider("video2_pll1_out_div", "video2_pll1_out", base + 0x5c, 19, 6); + clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6); + clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6); + clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6); + clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6); + clks[IMX8MQ_VIDEO2_PLL2_DIV] = imx_clk_divider("video2_pll2_div", "video2_pll2", base + 0x5c, 1, 6); + + /* PLL bypass out */ + clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels)); + clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); + clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); + clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); + clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); + clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); + + clks[IMX8MQ_SYS1_PLL1_OUT] = imx_clk_mux("sys1_pll1_out", base + 0x30, 5, 1, sys1_pll1_out_sels, ARRAY_SIZE(sys1_pll1_out_sels)); + clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels)); + clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels)); + clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels)); + clks[IMX8MQ_VIDEO2_PLL1_OUT] = imx_clk_mux("video2_pll1_out", base + 0x54, 5, 1, video2_pll1_out_sels, ARRAY_SIZE(video2_pll1_out_sels)); + clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels)); + clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels)); + clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels)); + clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels)); + clks[IMX8MQ_VIDEO2_PLL2_OUT] = imx_clk_mux("video2_pll2_out", base + 0x54, 4, 1, video2_pll2_out_sels, ARRAY_SIZE(video2_pll2_out_sels)); + + /* unbypass all the plls */ + clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]); + clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]); + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]); + clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]); + clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]); + + /* PLL OUT GATE */ + clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); + clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); + clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21); + clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21); + clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21); + clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); + clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_gate("sys1_pll_out", "sys1_pll2_out", base + 0x30, 9); + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9); + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9); + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9); + clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_gate("video2_pll_out", "video2_pll2_out", base + 0x54, 9); + + /* SYS PLL fixed output */ + clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20); + clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10); + clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8); + clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6); + clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5); + clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4); + clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3); + clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2); + clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1); + + clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20); + clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10); + clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8); + clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6); + clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5); + clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4); + clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3); + clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2); + clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1); + + np = ccm_node; + base = of_iomap(np, 0); + WARN_ON(!base); + /* CORE */ + clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)); + clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels)); + clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels)); + clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels)); + clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL); + clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); + clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28); + clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28); + + clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); + clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); + clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); + clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); + + /* BUS */ + clks[IMX8MQ_CLK_MAIN_AXI] = imx_clk_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800); + clks[IMX8MQ_CLK_ENET_AXI] = imx_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880); + clks[IMX8MQ_CLK_NAND_USDHC_BUS] = imx_clk_composite_critical("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900); + clks[IMX8MQ_CLK_VPU_BUS] = imx_clk_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980); + clks[IMX8MQ_CLK_DISP_AXI] = imx_clk_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00); + clks[IMX8MQ_CLK_DISP_APB] = imx_clk_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80); + clks[IMX8MQ_CLK_DISP_RTRM] = imx_clk_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00); + clks[IMX8MQ_CLK_USB_BUS] = imx_clk_composite_critical("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80); + clks[IMX8MQ_CLK_GPU_AXI] = imx_clk_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00); + clks[IMX8MQ_CLK_GPU_AHB] = imx_clk_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80); + clks[IMX8MQ_CLK_NOC] = imx_clk_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00); + clks[IMX8MQ_CLK_NOC_APB] = imx_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80); + + /* AHB */ + clks[IMX8MQ_CLK_AHB_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, imx8mq_ahb_sels, ARRAY_SIZE(imx8mq_ahb_sels)); + clks[IMX8MQ_CLK_AUDIO_AHB_SRC] = imx_clk_mux2("audio_ahb_src", base + 0x9100, 24, 3, imx8mq_audio_ahb_sels, ARRAY_SIZE(imx8mq_audio_ahb_sels)); + clks[IMX8MQ_CLK_AHB_CG] = imx_clk_gate3_flags("ahb_cg", "ahb_src", base + 0x9000, 28, CLK_IS_CRITICAL); + clks[IMX8MQ_CLK_AUDIO_AHB_CG] = imx_clk_gate3("audio_ahb_cg", "audio_ahb_src", base + 0x9100, 28); + clks[IMX8MQ_CLK_AHB_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); + clks[IMX8MQ_CLK_AUDIO_AHB_PRE_DIV] = imx_clk_divider2("audio_ahb_pre_div", "audio_ahb_cg", base + 0x9100, 16, 3); + clks[IMX8MQ_CLK_AHB_DIV] = imx_clk_divider_flags("ahb_div", "ahb_pre_div", base + 0x9000, 0, 6, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_AUDIO_AHB_DIV] = imx_clk_divider2_flags("audio_ahb_div", "audio_ahb_pre_div", base + 0x9100, 0, 6, CLK_IS_CRITICAL); + + /* IPG */ + clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_div", base + 0x9080, 0, 1); + clks[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb_div", base + 0x9180, 0, 1); + + /* IP */ + clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); + + clks[IMX8MQ_CLK_DRAM_ALT] = imx_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000); + clks[IMX8MQ_CLK_DRAM_APB] = imx_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080); + clks[IMX8MQ_CLK_VPU_G1] = imx_clk_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100); + clks[IMX8MQ_CLK_VPU_G2] = imx_clk_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180); + clks[IMX8MQ_CLK_DISP_DTRC] = imx_clk_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200); + clks[IMX8MQ_CLK_DISP_DC8000] = imx_clk_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280); + clks[IMX8MQ_CLK_PCIE1_CTRL] = imx_clk_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300); + clks[IMX8MQ_CLK_PCIE1_PHY] = imx_clk_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380); + clks[IMX8MQ_CLK_PCIE1_AUX] = imx_clk_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400); + clks[IMX8MQ_CLK_DC_PIXEL] = imx_clk_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480); + clks[IMX8MQ_CLK_LCDIF_PIXEL] = imx_clk_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500); + clks[IMX8MQ_CLK_SAI1] = imx_clk_composite("sai1", imx8mq_sai1_sels, base + 0xa580); + clks[IMX8MQ_CLK_SAI2] = imx_clk_composite("sai2", imx8mq_sai2_sels, base + 0xa600); + clks[IMX8MQ_CLK_SAI3] = imx_clk_composite("sai3", imx8mq_sai3_sels, base + 0xa680); + clks[IMX8MQ_CLK_SAI4] = imx_clk_composite("sai4", imx8mq_sai4_sels, base + 0xa700); + clks[IMX8MQ_CLK_SAI5] = imx_clk_composite("sai5", imx8mq_sai5_sels, base + 0xa780); + clks[IMX8MQ_CLK_SAI6] = imx_clk_composite("sai6", imx8mq_sai6_sels, base + 0xa800); + clks[IMX8MQ_CLK_SPDIF1] = imx_clk_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880); + clks[IMX8MQ_CLK_SPDIF2] = imx_clk_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900); + clks[IMX8MQ_CLK_ENET_REF] = imx_clk_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980); + clks[IMX8MQ_CLK_ENET_TIMER] = imx_clk_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00); + clks[IMX8MQ_CLK_ENET_PHY_REF] = imx_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80); + clks[IMX8MQ_CLK_NAND] = imx_clk_composite("nand", imx8mq_nand_sels, base + 0xab00); + clks[IMX8MQ_CLK_QSPI] = imx_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80); + clks[IMX8MQ_CLK_USDHC1] = imx_clk_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00); + clks[IMX8MQ_CLK_USDHC2] = imx_clk_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80); + clks[IMX8MQ_CLK_I2C1] = imx_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00); + clks[IMX8MQ_CLK_I2C2] = imx_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80); + clks[IMX8MQ_CLK_I2C3] = imx_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00); + clks[IMX8MQ_CLK_I2C4] = imx_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80); + clks[IMX8MQ_CLK_UART1] = imx_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00); + clks[IMX8MQ_CLK_UART2] = imx_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80); + clks[IMX8MQ_CLK_UART3] = imx_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000); + clks[IMX8MQ_CLK_UART4] = imx_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080); + clks[IMX8MQ_CLK_USB_CORE_REF] = imx_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100); + clks[IMX8MQ_CLK_USB_PHY_REF] = imx_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180); + clks[IMX8MQ_CLK_ECSPI1] = imx_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280); + clks[IMX8MQ_CLK_ECSPI2] = imx_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300); + clks[IMX8MQ_CLK_PWM1] = imx_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380); + clks[IMX8MQ_CLK_PWM2] = imx_clk_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400); + clks[IMX8MQ_CLK_PWM3] = imx_clk_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480); + clks[IMX8MQ_CLK_PWM4] = imx_clk_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500); + clks[IMX8MQ_CLK_GPT1] = imx_clk_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580); + clks[IMX8MQ_CLK_WDOG] = imx_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900); + clks[IMX8MQ_CLK_WRCLK] = imx_clk_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980); + clks[IMX8MQ_CLK_CLKO2] = imx_clk_composite("clko2", imx8mq_clko2_sels, base + 0xba80); + clks[IMX8MQ_CLK_DSI_CORE] = imx_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00); + clks[IMX8MQ_CLK_DSI_PHY_REF] = imx_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80); + clks[IMX8MQ_CLK_DSI_DBI] = imx_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00); + clks[IMX8MQ_CLK_DSI_ESC] = imx_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80); + clks[IMX8MQ_CLK_DSI_AHB] = imx_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200); + clks[IMX8MQ_CLK_CSI1_CORE] = imx_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00); + clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80); + clks[IMX8MQ_CLK_CSI1_ESC] = imx_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00); + clks[IMX8MQ_CLK_CSI2_CORE] = imx_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80); + clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00); + clks[IMX8MQ_CLK_CSI2_ESC] = imx_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80); + clks[IMX8MQ_CLK_PCIE2_CTRL] = imx_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000); + clks[IMX8MQ_CLK_PCIE2_PHY] = imx_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080); + clks[IMX8MQ_CLK_PCIE2_AUX] = imx_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100); + clks[IMX8MQ_CLK_ECSPI3] = imx_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180); + + /*FIXME, the doc is not ready now */ + clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); + clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); + clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); + clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); + clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); + clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); + clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); + clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); + clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); + clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); + clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); + clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0); + clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0); + clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); + clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); + clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); + clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); + clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); + clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); + clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); + clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1); + clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1); + clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); + clks[IMX8MQ_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0, &share_count_sai2); + clks[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); + clks[IMX8MQ_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0, &share_count_sai3); + clks[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4); + clks[IMX8MQ_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4); + clks[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); + clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); + clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); + clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); + clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); + clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); + clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); + clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); + clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); + clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0); + clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0); + clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0); + clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); + clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); + clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); + clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); + clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); + clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0); + clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL); + clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); + clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0); + clks[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); + clks[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); + + clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8); + clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); + + for (i = 0; i < IMX8MQ_CLK_END; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX8mq clk %u register failed with %ld\n", + i, PTR_ERR(clks[i])); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_set_parent(clks[IMX8MQ_VIDEO2_PLL1_OUT], clks[IMX8MQ_VIDEO2_PLL1]); + clk_set_parent(clks[IMX8MQ_VIDEO2_PLL2_OUT], clks[IMX8MQ_VIDEO2_PLL2_DIV]); + + clk_set_parent(clks[IMX8MQ_CLK_AHB_SRC], clks[IMX8MQ_SYS1_PLL_133M]); + clk_set_parent(clks[IMX8MQ_CLK_NAND_USDHC_BUS], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_AUDIO_AHB_SRC], clks[IMX8MQ_SYS2_PLL_500M]); + + /* config video_pll1 clock */ + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]); + clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999); + + /* increase NOC clock to achieve best DDR access performance */ + clk_set_rate(clks[IMX8MQ_CLK_NOC], clk_get_rate(clks[IMX8MQ_SYS1_PLL_800M])); + + /* set pcie root's parent clk source */ + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]); + + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]); +} + +CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 9dbb680..e89c3a7 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -128,6 +128,15 @@ static inline struct clk *imx_clk_divider2(const char *name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_divider2_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 width, + unsigned long flags) +{ + return clk_register_divider(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -195,6 +204,15 @@ static inline struct clk *imx_clk_gate3(const char *name, const char *parent, reg, shift, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_gate3_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned long flags) +{ + return clk_register_gate(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate4(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -203,6 +221,15 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, reg, shift, 0x3, 0, &imx_ccm_lock, NULL); } +static inline struct clk *imx_clk_gate4_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned long flags) +{ + return clk_register_gate2(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0x3, 0, &imx_ccm_lock, NULL); +} + static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { @@ -228,6 +255,15 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk *imx_clk_mux2_flags(const char *name, + void __iomem *reg, u8 shift, u8 width, const char **parents, + int num_parents, unsigned long flags) +{ + return clk_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM 2018-08-22 13:48 ` [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa @ 2018-08-24 7:58 ` Sascha Hauer 2018-08-28 18:45 ` Andrey Smirnov 1 sibling, 0 replies; 15+ messages in thread From: Sascha Hauer @ 2018-08-24 7:58 UTC (permalink / raw) To: Abel Vesa Cc: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, Mark Rutland, Rob Herring, devicetree, Stephen Boyd, Michael Turquette, linux-kernel, Abel Vesa, linux-imx, Shawn Guo, linux-clk On Wed, Aug 22, 2018 at 04:48:23PM +0300, Abel Vesa wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > Add driver for the Clock Control Module found on i.MX8MQ. > > This is largely based on the downstream driver from Anson Huang and > Bai Ping at NXP, with only some small adaptions to mainline from me. It's time to rephrase the commit message. With the new composite clock the adaptions are no longer that small. > + > +static int const clks_init_on[] __initconst = { > + IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG, > + IMX8MQ_CLK_NOC, IMX8MQ_CLK_NOC_APB, > + IMX8MQ_CLK_USB_BUS, IMX8MQ_CLK_NAND_USDHC_BUS, > + IMX8MQ_CLK_MAIN_AXI, IMX8MQ_CLK_A53_CG, > + IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT, > + IMX8MQ_CLK_DRAM_APB, > +}; This is unused and you seem to have converted all these clocks to add the CLK_IS_CRITICAL flag. Are all these really needed? some clocks like IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_USB_BUS and IMX8MQ_CLK_NAND_USDHC_BUS look suspicious. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM 2018-08-22 13:48 ` [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa 2018-08-24 7:58 ` Sascha Hauer @ 2018-08-28 18:45 ` Andrey Smirnov 1 sibling, 0 replies; 15+ messages in thread From: Andrey Smirnov @ 2018-08-28 18:45 UTC (permalink / raw) To: Abel Vesa Cc: Lucas Stach, Sascha Hauer, Dong Aisheng, Fabio Estevam, Anson Huang, linux-clk, linux-imx, Shawn Guo, Michael Turquette, sboyd, Rob Herring, Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, abelvesa On Wed, Aug 22, 2018 at 7:05 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > From: Lucas Stach <l.stach@pengutronix.de> > > Add driver for the Clock Control Module found on i.MX8MQ. > > This is largely based on the downstream driver from Anson Huang and > Bai Ping at NXP, with only some small adaptions to mainline from me. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-imx8mq.c | 631 +++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/imx/clk.h | 36 +++ > 3 files changed, 668 insertions(+) > create mode 100644 drivers/clk/imx/clk-imx8mq.c > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 4fabb0a..64e695c 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o > obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o > obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o > obj-$(CONFIG_SOC_VF610) += clk-vf610.o > +obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > new file mode 100644 > index 0000000..d3a9e31 > --- /dev/null > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -0,0 +1,631 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2018 NXP. > + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> > + */ > + > +#include <dt-bindings/clock/imx8mq-clock.h> > +#include <linux/clk.h> > +#include <linux/clkdev.h> > +#include <linux/err.h> > +#include <linux/init.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/types.h> > + > +#include "clk.h" > + > +static u32 share_count_sai1; > +static u32 share_count_sai2; > +static u32 share_count_sai3; > +static u32 share_count_sai4; > +static u32 share_count_sai5; > +static u32 share_count_sai6; > +static u32 share_count_dcss; > +static u32 share_count_nand; > + > +static struct clk *clks[IMX8MQ_CLK_END]; > + > +static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; > +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; > +static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; > +static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; > +static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; > +static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; > +static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; > + > +static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", }; > +static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", }; > +static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", }; > +static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", }; > +static const char *video2_pll1_out_sels[] = {"video2_pll1", "video2_pll1_ref_sel", }; > + > +static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", }; > +static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", }; > +static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", }; > +static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", }; > +static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref_sel", }; > + > +/* CCM ROOT */ > +static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", > + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", }; > + > +static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", > + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", }; > + > +static const char *imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", > + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", > + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m", > + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",}; > + > +static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m", > + "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", }; > + > +static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m", > + "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", }; > + > +static const char *imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", }; > + > +static const char *imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", }; > + > +static const char *imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", > + "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; > + > +static const char *imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m", > + "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; > + > +static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m", > + "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; > + > +static const char *imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", > + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", > + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m", > + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m", > + "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", }; > + > +static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m", > + "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; > + > +static const char *imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m", > + "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; > + > +static const char *imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"}; > + > +static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m", > + "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", }; > + > +static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", > + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; > + > +static const char *imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; > + > +static const char *imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; > + > +static const char *imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; > + > +static const char *imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; > + > +static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", > + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", }; > + > +static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", > + "clk_ext3", "clk_ext4", }; > + > +static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out", > + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; > + > +static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; > + > +static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; > + > +static const char *imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; > + > +static const char *imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; > + > +static const char *imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; > + > +static const char *imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; > + > +static const char *imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; > + > +static const char *imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; > + > +static const char *imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; > + > +static const char *imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; > + > +static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m", > + "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; > + > +static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", > + "clk_ext3", "clk_ext4", "video_pll1_out", }; > + > +static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m", > + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; > + > +static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m", > + "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", }; > + > +static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", > + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; > + > +static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", > + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; > + > +static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", > + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; > + > +static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", > + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; > + > +static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", > + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; > + > +static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", > + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; > + > +static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", > + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; > + > +static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", > + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; > + > +static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", > + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", > + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; > + > +static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", > + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", > + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", > + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", > + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; > + > +static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", > + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; > + > +static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", > + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; > + > +static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", > + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; > + > +static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", > + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; > + > +static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", > + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; > + > +static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m", > + "sys1_pll_80m", "audio_pll1_out", "clk_ext1", }; > + > +static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out", > + "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", }; > + > +static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m", > + "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", }; > + > +static const char *imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", > + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", > + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", > + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; > + > +static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", > + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; > + > +static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", > + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", }; > + > +static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", > + "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", }; > + > +static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out", > + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; > + > +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", > + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; > +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; > + > +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out", > + "video_pll1_out", "ckil", }; > + > +static int const clks_init_on[] __initconst = { > + IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG, > + IMX8MQ_CLK_NOC, IMX8MQ_CLK_NOC_APB, > + IMX8MQ_CLK_USB_BUS, IMX8MQ_CLK_NAND_USDHC_BUS, > + IMX8MQ_CLK_MAIN_AXI, IMX8MQ_CLK_A53_CG, > + IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT, > + IMX8MQ_CLK_DRAM_APB, > +}; > + > +static struct clk_onecell_data clk_data; > + > +static void __init imx8mq_clocks_init(struct device_node *ccm_node) > +{ > + struct device_node *np; > + void __iomem *base; > + int i; > + > + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0); > + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil"); > + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m"); > + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m"); > + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); > + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); > + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); > + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); > + base = of_iomap(np, 0); > + WARN_ON(!base); > + > + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); > + > + clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6); > + clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6); > + clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6); > + clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6); > + clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6); > + clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6); > + clks[IMX8MQ_SYS1_PLL1_REF_DIV] = imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3); > + clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3); > + clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3); > + clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3); > + clks[IMX8MQ_VIDEO2_PLL1_REF_DIV] = imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, 25, 3); > + > + clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); > + clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); > + clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); > + clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0); > + clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8); > + clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10); > + clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1); > + clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1); > + clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1); > + clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1); > + clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", "video2_pll1_ref_div", base + 0x5c, 3); This is a bug which will result in a crash once IMX8MQ_VIDEO2_PLL1 is exercised (I know that from having to debug this issue when using this code in Barebox). Last argument should be SCCG_PLL1. Thanks, Andrey Smirnov ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-09-04 19:31 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-08-22 13:48 [PATCH v6 0/5] Add i.MX8MQ clock driver Abel Vesa 2018-08-22 13:48 ` [PATCH v6 1/5] dt-bindings: add binding for i.MX8MQ CCM Abel Vesa 2018-08-22 13:48 ` [PATCH v6 2/5] clk: imx: add fractional PLL output clock Abel Vesa 2018-08-22 13:48 ` [PATCH v6 3/5] clk: imx: add SCCG PLL type Abel Vesa 2018-08-24 7:40 ` Sascha Hauer 2018-08-28 10:58 ` Abel Vesa 2018-08-28 19:11 ` Andrey Smirnov 2018-09-04 13:13 ` Abel Vesa 2018-09-04 19:30 ` Andrey Smirnov 2018-08-28 18:47 ` Andrey Smirnov 2018-08-22 13:48 ` [PATCH v6 4/5] clk: imx: add imx composite clock Abel Vesa 2018-08-24 7:43 ` Sascha Hauer 2018-08-22 13:48 ` [PATCH v6 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa 2018-08-24 7:58 ` Sascha Hauer 2018-08-28 18:45 ` Andrey Smirnov
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