* [PATCH v3 0/2] clk: qcom: Quad SPI (qspi) clock support for sdm845 @ 2018-07-24 17:45 Douglas Anderson 2018-07-24 17:45 ` [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header Douglas Anderson 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson 0 siblings, 2 replies; 9+ messages in thread From: Douglas Anderson @ 2018-07-24 17:45 UTC (permalink / raw) To: sboyd, andy.gross Cc: tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Douglas Anderson, devicetree, Michael Turquette, linux-kernel, David Brown, Rob Herring, Mark Rutland This two-series patch adds the needed clock bits to use the Quad SPI (qspi) part on sdm845. It's expected that the bindings part of this patch could land in the clock tree with an immutable git hash and then be pulled into the Qualcomm tree so it could be used by dts files. From the reply to my v1, the clock plan for this clock is: - MinSVS@19.2 - LowSVS@75 - SVS@150 - Nominal@300 ...and intermediate frequencies can be used at frequences less than 300. I didn't see a need for 75 MHz and it was unclear from previous replies if this should come from MAIN or EVEN so I left it out. I have added 100 MHz here since it is useful (/ 4 = 25 MHz is a useful clock for SPI flash) OTHER NOTES: - From probing lines, it appears that the Quad SPI block has a divide by 4 somewhere inside it (probably so it can oversample the lines, or possibly so it can generate phase-offset clocks). Thus we need the core to go 4 times faster than we'd expect to run the SPI bus. - SPI devices usually specify the MAX frequency they should be clocked at, so it's important that we use the clk_rcg2_floor_ops here rather than the clk_rcg2_ops Changes in v3: - Removed gcc_parent_names_9 which I had left in (doh!). Changes in v2: - Only 19.2, 100, 150, and 300 MHz now. - All clocks come from MAIN rather than EVEN. - Use parent map 0 instead of new parent map 9. Douglas Anderson (2): clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header clk: qcom: Add qspi (Quad SPI) clocks for sdm845 drivers/clk/qcom/gcc-sdm845.c | 56 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 ++ 2 files changed, 59 insertions(+) -- 2.18.0.233.g985f88cf7e-goog ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header 2018-07-24 17:45 [PATCH v3 0/2] clk: qcom: Quad SPI (qspi) clock support for sdm845 Douglas Anderson @ 2018-07-24 17:45 ` Douglas Anderson 2018-07-25 16:01 ` Rob Herring 2018-08-28 22:58 ` Stephen Boyd 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson 1 sibling, 2 replies; 9+ messages in thread From: Douglas Anderson @ 2018-07-24 17:45 UTC (permalink / raw) To: sboyd, andy.gross Cc: tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Douglas Anderson, devicetree, linux-kernel, Rob Herring, Mark Rutland These clocks will need to be defined in the clock driver and referenced in device tree files. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v3: None Changes in v2: None include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h index f96fc2dbf60e..b8eae5a76503 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h @@ -194,6 +194,9 @@ #define GPLL4 184 #define GCC_CPUSS_DVM_BUS_CLK 185 #define GCC_CPUSS_GNOC_CLK 186 +#define GCC_QSPI_CORE_CLK_SRC 187 +#define GCC_QSPI_CORE_CLK 188 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 /* GCC Resets */ #define GCC_MMSS_BCR 0 -- 2.18.0.233.g985f88cf7e-goog ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header 2018-07-24 17:45 ` [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header Douglas Anderson @ 2018-07-25 16:01 ` Rob Herring 2018-08-10 8:08 ` Taniya Das 2018-08-28 22:58 ` Stephen Boyd 1 sibling, 1 reply; 9+ messages in thread From: Rob Herring @ 2018-07-25 16:01 UTC (permalink / raw) To: Douglas Anderson Cc: sboyd, andy.gross, tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, devicetree, linux-kernel, Mark Rutland On Tue, Jul 24, 2018 at 10:45:12AM -0700, Douglas Anderson wrote: > These clocks will need to be defined in the clock driver and > referenced in device tree files. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > Changes in v3: None > Changes in v2: None > > include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++ > 1 file changed, 3 insertions(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header 2018-07-25 16:01 ` Rob Herring @ 2018-08-10 8:08 ` Taniya Das 0 siblings, 0 replies; 9+ messages in thread From: Taniya Das @ 2018-08-10 8:08 UTC (permalink / raw) To: Rob Herring, Douglas Anderson Cc: sboyd, andy.gross, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, devicetree, linux-kernel, Mark Rutland On 7/25/2018 9:31 PM, Rob Herring wrote: > On Tue, Jul 24, 2018 at 10:45:12AM -0700, Douglas Anderson wrote: >> These clocks will need to be defined in the clock driver and >> referenced in device tree files. >> >> Signed-off-by: Douglas Anderson <dianders@chromium.org> >> --- >> >> Changes in v3: None >> Changes in v2: None >> >> include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++ >> 1 file changed, 3 insertions(+) > > Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Taniya Das <tdas@codeaurora.org> > -- > To unsubscribe from this list: send the line "unsubscribe linux-clk" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. -- ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header 2018-07-24 17:45 ` [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header Douglas Anderson 2018-07-25 16:01 ` Rob Herring @ 2018-08-28 22:58 ` Stephen Boyd 1 sibling, 0 replies; 9+ messages in thread From: Stephen Boyd @ 2018-08-28 22:58 UTC (permalink / raw) To: Douglas Anderson, andy.gross Cc: tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Douglas Anderson, devicetree, linux-kernel, Rob Herring, Mark Rutland Quoting Douglas Anderson (2018-07-24 10:45:12) > These clocks will need to be defined in the clock driver and > referenced in device tree files. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 2018-07-24 17:45 [PATCH v3 0/2] clk: qcom: Quad SPI (qspi) clock support for sdm845 Douglas Anderson 2018-07-24 17:45 ` [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header Douglas Anderson @ 2018-07-24 17:45 ` Douglas Anderson 2018-07-24 18:24 ` Doug Anderson ` (2 more replies) 1 sibling, 3 replies; 9+ messages in thread From: Douglas Anderson @ 2018-07-24 17:45 UTC (permalink / raw) To: sboyd, andy.gross Cc: tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Douglas Anderson, Michael Turquette, linux-kernel, David Brown Add both the interface and core clock. Signed-off-by: Douglas Anderson <dianders@chromium.org> (am from https://lore.kernel.org/patchwork/patch/966680/mbox) --- Changes in v3: - Removed gcc_parent_names_9 which I had left in (doh!). Changes in v2: - Only 19.2, 100, 150, and 300 MHz now. - All clocks come from MAIN rather than EVEN. - Use parent map 0 instead of new parent map 9. drivers/clk/qcom/gcc-sdm845.c | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 0f694ed4238a..fc1c6658ad82 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -358,6 +358,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qspi_core_clk_src = { + .cmd_rcgr = 0x4b008, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qspi_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_floor_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), @@ -1935,6 +1957,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = { }, }; +static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { + .halt_reg = 0x4b000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_cnoc_periph_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_core_clk = { + .halt_reg = 0x4b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_core_clk", + .parent_names = (const char *[]){ + "gcc_qspi_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .halt_reg = 0x17030, .halt_check = BRANCH_HALT_VOTED, @@ -3383,6 +3436,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { [GPLL4] = &gpll4.clkr, [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, + [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, + [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, }; static const struct qcom_reset_map gcc_sdm845_resets[] = { -- 2.18.0.233.g985f88cf7e-goog ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson @ 2018-07-24 18:24 ` Doug Anderson 2018-08-10 8:09 ` Taniya Das 2018-08-28 22:58 ` Stephen Boyd 2 siblings, 0 replies; 9+ messages in thread From: Doug Anderson @ 2018-07-24 18:24 UTC (permalink / raw) To: Stephen Boyd, Andy Gross Cc: Taniya Das, Girish Mahadevan, linux-arm-msm, Amit Nischal, Bjorn Andersson, grahamr, open list:ARM/QUALCOMM SUPPORT, linux-clk, Douglas Anderson, Michael Turquette, LKML, David Brown Hi, On Tue, Jul 24, 2018 at 10:45 AM, Douglas Anderson <dianders@chromium.org> wrote: > Add both the interface and core clock. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > (am from https://lore.kernel.org/patchwork/patch/966680/mbox) It's just the day for me being a screwup I guess. :( That line (obviously) doesn't belong. I'm assuming it's easy enough for Stephen to remove it when he applies so I won't plan to repost. Sorry for being so dumb. -Doug ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson 2018-07-24 18:24 ` Doug Anderson @ 2018-08-10 8:09 ` Taniya Das 2018-08-28 22:58 ` Stephen Boyd 2 siblings, 0 replies; 9+ messages in thread From: Taniya Das @ 2018-08-10 8:09 UTC (permalink / raw) To: Douglas Anderson, sboyd, andy.gross Cc: girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Michael Turquette, linux-kernel, David Brown On 7/24/2018 11:15 PM, Douglas Anderson wrote: > Add both the interface and core clock. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > (am from https://lore.kernel.org/patchwork/patch/966680/mbox) > > --- > > Changes in v3: > - Removed gcc_parent_names_9 which I had left in (doh!). > > Changes in v2: > - Only 19.2, 100, 150, and 300 MHz now. > - All clocks come from MAIN rather than EVEN. > - Use parent map 0 instead of new parent map 9. > > drivers/clk/qcom/gcc-sdm845.c | 56 +++++++++++++++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index 0f694ed4238a..fc1c6658ad82 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -358,6 +358,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { > }, > }; > > +static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), > + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), > + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_qspi_core_clk_src = { > + .cmd_rcgr = 0x4b008, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qspi_core_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_qspi_core_clk_src", > + .parent_names = gcc_parent_names_0, > + .num_parents = 4, > + .ops = &clk_rcg2_floor_ops, > + }, > +}; > + > static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { > F(9600000, P_BI_TCXO, 2, 0, 0), > F(19200000, P_BI_TCXO, 1, 0, 0), > @@ -1935,6 +1957,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = { > }, > }; > > +static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { > + .halt_reg = 0x4b000, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4b000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_qspi_cnoc_periph_ahb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_qspi_core_clk = { > + .halt_reg = 0x4b004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4b004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_qspi_core_clk", > + .parent_names = (const char *[]){ > + "gcc_qspi_core_clk_src", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_qupv3_wrap0_s0_clk = { > .halt_reg = 0x17030, > .halt_check = BRANCH_HALT_VOTED, > @@ -3383,6 +3436,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { > [GPLL4] = &gpll4.clkr, > [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, > [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, > + [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, > + [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, > + [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, > }; > > static const struct qcom_reset_map gcc_sdm845_resets[] = { > Reviewed-by: Taniya Das <tdas@codeaurora.org> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. -- ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson 2018-07-24 18:24 ` Doug Anderson 2018-08-10 8:09 ` Taniya Das @ 2018-08-28 22:58 ` Stephen Boyd 2 siblings, 0 replies; 9+ messages in thread From: Stephen Boyd @ 2018-08-28 22:58 UTC (permalink / raw) To: Douglas Anderson, andy.gross Cc: tdas, girishm, linux-arm-msm, anischal, bjorn.andersson, grahamr, linux-soc, linux-clk, Douglas Anderson, Michael Turquette, linux-kernel, David Brown Quoting Douglas Anderson (2018-07-24 10:45:13) > Add both the interface and core clock. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > (am from https://lore.kernel.org/patchwork/patch/966680/mbox) > > --- Applied to clk-next ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-08-28 22:58 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-07-24 17:45 [PATCH v3 0/2] clk: qcom: Quad SPI (qspi) clock support for sdm845 Douglas Anderson 2018-07-24 17:45 ` [PATCH v3 1/2] clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header Douglas Anderson 2018-07-25 16:01 ` Rob Herring 2018-08-10 8:08 ` Taniya Das 2018-08-28 22:58 ` Stephen Boyd 2018-07-24 17:45 ` [PATCH v3 2/2] clk: qcom: Add qspi (Quad SPI) clocks for sdm845 Douglas Anderson 2018-07-24 18:24 ` Doug Anderson 2018-08-10 8:09 ` Taniya Das 2018-08-28 22:58 ` Stephen Boyd
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