From: Atish Patra <atish.patra@wdc.com>
To: palmer@sifive.com, linux-riscv@lists.infradead.org
Cc: mark.rutland@arm.com, hch@infradead.org, anup@brainfault.org,
atish.patra@wdc.com, tglx@linutronix.de,
linux-kernel@vger.kernel.org, Damien.LeMoal@wdc.com,
marc.zyngier@arm.com, jeremy.linton@arm.com,
gregkh@linuxfoundation.org, jason@lakedaemon.net,
catalin.marinas@arm.com, dmitriy@oss-tech.org,
ard.biesheuvel@linaro.org
Subject: [PATCH v4 06/12] RISC-V: Provide a cleaner raw_smp_processor_id()
Date: Tue, 11 Sep 2018 13:05:33 -0700 [thread overview]
Message-ID: <1536696339-15204-7-git-send-email-atish.patra@wdc.com> (raw)
In-Reply-To: <1536696339-15204-1-git-send-email-atish.patra@wdc.com>
From: Palmer Dabbelt <palmer@sifive.com>
I'm not sure how I managed to miss this the first time, but this is much
better.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: code comment formatting and other fixes]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
---
arch/riscv/include/asm/smp.h | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 36016845..85d7619e 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -14,13 +14,9 @@
#ifndef _ASM_RISCV_SMP_H
#define _ASM_RISCV_SMP_H
-/* This both needs asm-offsets.h and is used when generating it. */
-#ifndef GENERATING_ASM_OFFSETS
-#include <asm/asm-offsets.h>
-#endif
-
#include <linux/cpumask.h>
#include <linux/irqreturn.h>
+#include <linux/thread_info.h>
#ifdef CONFIG_SMP
@@ -34,12 +30,10 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask);
void arch_send_call_function_single_ipi(int cpu);
/*
- * This is particularly ugly: it appears we can't actually get the definition
- * of task_struct here, but we need access to the CPU this task is running on.
- * Instead of using C we're using asm-offsets.h to get the current processor
- * ID.
+ * Obtains the hart ID of the currently executing task. This relies on
+ * THREAD_INFO_IN_TASK, but we define that unconditionally.
*/
-#define raw_smp_processor_id() (*((int*)((char*)get_current() + TASK_TI_CPU)))
+#define raw_smp_processor_id() (current_thread_info()->cpu)
#endif /* CONFIG_SMP */
--
2.7.4
next prev parent reply other threads:[~2018-09-11 20:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-11 20:05 [PATCH v4 00/12] SMP cleanup and new features Atish Patra
2018-09-11 20:05 ` [PATCH v4 01/12] RISC-V: No need to pass scause as arg to do_IRQ() Atish Patra
2018-09-11 20:05 ` [PATCH v4 02/12] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} Atish Patra
2018-09-11 20:05 ` [PATCH v4 03/12] RISC-V: Filter ISA and MMU values in cpuinfo Atish Patra
2018-09-11 20:05 ` [PATCH v4 04/12] RISC-V: Comment on the TLB flush in smp_callin() Atish Patra
2018-09-11 20:05 ` [PATCH v4 05/12] RISC-V: Disable preemption before enabling interrupts Atish Patra
2018-09-11 20:05 ` Atish Patra [this message]
2018-09-11 20:05 ` [PATCH v4 07/12] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid Atish Patra
2018-09-11 20:05 ` [PATCH v4 08/12] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu Atish Patra
2018-09-11 20:05 ` [PATCH v4 09/12] RISC-V: Use mmgrab() Atish Patra
2018-09-11 20:05 ` [PATCH v4 10/12] RISC-V: User WRITE_ONCE instead of direct access Atish Patra
2018-09-11 20:32 ` Andreas Schwab
2018-09-13 18:21 ` Atish Patra
2018-09-11 20:05 ` [PATCH v4 11/12] RISC-V: Add logical CPU indexing for RISC-V Atish Patra
2018-09-11 20:05 ` [PATCH v4 12/12] RISC-V: Use Linux logical cpu number instead of hartid Atish Patra
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