[RFC PATCH v2 0/4] Add support for SD Tap Delay setting for ZynqMP

[RFC PATCH v2 0/4] Add support for SD Tap Delay setting for ZynqMP

[Manish Narani]

This series of patches are created On top of the
below series of patches.
1. https://lkml.org/lkml/2018/8/3/687 
2. https://lkml.org/lkml/2018/9/18/1034

As the ZynqMP Firmware Driver is not yet merged, sending RFC to make
modifications before sending the final patches.

Changes in v2:
- s/_/-/ in the property name
- Changed order of the patches : DT binding change -> driver change -> DT change

Manish Narani (4):
  dt: bindings: Add SD tap value properties details for
    'xlnx,zynqmp-8.9a'
  firmware: xilinx: Add macros and API for SD tap delays
  sdhci: arasan: Add support to read and set tap delays from DT for
    ZynqMP
  arm64: zynqmp: Add 'xlnx,mio-bank' property in SDHCI node

 .../devicetree/bindings/mmc/arasan,sdhci.txt       |  19 ++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi             |   2 +
 drivers/firmware/xilinx/Makefile                   |   1 +
 drivers/firmware/xilinx/zynqmp-tap-delays.c        |  39 ++++
 drivers/mmc/host/sdhci-of-arasan.c                 | 215 +++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h               |  33 +++-
 6 files changed, 308 insertions(+), 1 deletion(-)
 create mode 100644 drivers/firmware/xilinx/zynqmp-tap-delays.c

-- 
2.1.1

[RFC PATCH v2 1/4] dt: bindings: Add SD tap value properties details for 'xlnx,zynqmp-8.9a'

[Manish Narani]

Add documentation for MIO bank required property and Tap Delays optional
properties in devicetree bindings.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.txt          | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 72769e0..6cc95fa 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -27,6 +27,7 @@ Required Properties for "arasan,sdhci-5.1":
 
 Required Properties for "xlnx,zynqmp-8.9a":
   - xlnx,device_id: SD controller device ID. Must be either <0> or <1>.
+  - xlnx,mio-bank: The value will be 0/1/2 depending on MIO bank selection.
 
 Optional Properties:
   - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
@@ -44,6 +45,24 @@ Optional Properties:
   - xlnx,int-clock-stable-broken: when present, the controller always reports
     that the internal clock is stable even when it is not.
 
+Optional Properties for "xlnx,zynqmp-8.9a":
+ - xlnx,itap-delay-sd-hsd: Input Tap Delay for SD HS.
+ - xlnx,itap-delay-sdr25: Input Tap Delay for SDR25.
+ - xlnx,itap-delay-sdr50: Input Tap Delay for SDR50.
+ - xlnx,itap-delay-sdr104: Input Tap Delay for SDR104.
+ - xlnx,itap-delay-sd-ddr50: Input Tap Delay for SD DDR50.
+ - xlnx,itap-delay-mmc-hsd: Input Tap Delay for MMC HS.
+ - xlnx,itap-delay-mmc-ddr52: Input Tap Delay for MMC DDR52.
+ - xlnx,itap-delay-mmc-hs200: Input Tap Delay for MMC HS200.
+ - xlnx,otap-delay-sd-hsd: Output Tap Delay for SD HS.
+ - xlnx,otap-delay-sdr25: Output Tap Delay for SDR25.
+ - xlnx,otap-delay-sdr50: Output Tap Delay for SDR50.
+ - xlnx,otap-delay-sdr104: Output Tap Delay for SDR104.
+ - xlnx,otap-delay-sd-ddr50: Output Tap Delay for DDR50.
+ - xlnx,otap-delay-mmc-hsd: Output Tap Delay for MMC HS.
+ - xlnx,otap-delay-mmc-ddr52: Output Tap Delay for MMC DDR52.
+ - xlnx,otap-delay-mmc-hs200: Output Tap Delay for MMC HS200.
+
 Example:
 	sdhci@e0100000 {
 		compatible = "arasan,sdhci-8.9a";
-- 
2.1.1

Re: [RFC PATCH v2 1/4] dt: bindings: Add SD tap value properties details for 'xlnx,zynqmp-8.9a'

[Rob Herring]

On Thu, Sep 20, 2018 at 03:00:42PM +0530, Manish Narani wrote:
> Add documentation for MIO bank required property and Tap Delays optional
> properties in devicetree bindings.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  .../devicetree/bindings/mmc/arasan,sdhci.txt          | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 72769e0..6cc95fa 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -27,6 +27,7 @@ Required Properties for "arasan,sdhci-5.1":
>  
>  Required Properties for "xlnx,zynqmp-8.9a":
>    - xlnx,device_id: SD controller device ID. Must be either <0> or <1>.
> +  - xlnx,mio-bank: The value will be 0/1/2 depending on MIO bank selection.
>  
>  Optional Properties:
>    - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
> @@ -44,6 +45,24 @@ Optional Properties:
>    - xlnx,int-clock-stable-broken: when present, the controller always reports
>      that the internal clock is stable even when it is not.
>  
> +Optional Properties for "xlnx,zynqmp-8.9a":
> + - xlnx,itap-delay-sd-hsd: Input Tap Delay for SD HS.
> + - xlnx,itap-delay-sdr25: Input Tap Delay for SDR25.
> + - xlnx,itap-delay-sdr50: Input Tap Delay for SDR50.
> + - xlnx,itap-delay-sdr104: Input Tap Delay for SDR104.
> + - xlnx,itap-delay-sd-ddr50: Input Tap Delay for SD DDR50.
> + - xlnx,itap-delay-mmc-hsd: Input Tap Delay for MMC HS.
> + - xlnx,itap-delay-mmc-ddr52: Input Tap Delay for MMC DDR52.
> + - xlnx,itap-delay-mmc-hs200: Input Tap Delay for MMC HS200.
> + - xlnx,otap-delay-sd-hsd: Output Tap Delay for SD HS.
> + - xlnx,otap-delay-sdr25: Output Tap Delay for SDR25.
> + - xlnx,otap-delay-sdr50: Output Tap Delay for SDR50.
> + - xlnx,otap-delay-sdr104: Output Tap Delay for SDR104.
> + - xlnx,otap-delay-sd-ddr50: Output Tap Delay for DDR50.
> + - xlnx,otap-delay-mmc-hsd: Output Tap Delay for MMC HS.
> + - xlnx,otap-delay-mmc-ddr52: Output Tap Delay for MMC DDR52.
> + - xlnx,otap-delay-mmc-hs200: Output Tap Delay for MMC HS200.

type, values, units for all of these?

Perhaps combine to pairs of values for input and output delays?

> +
>  Example:
>  	sdhci@e0100000 {
>  		compatible = "arasan,sdhci-8.9a";
> -- 
> 2.1.1
> 

[RFC PATCH v2 2/4] firmware: xilinx: Add macros and API for SD tap delays

[Manish Narani]

Add ZynqMP firmware SD tap delay macros and API for setting tap values.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 include/linux/firmware/xlnx-zynqmp.h | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 743687b..40feebc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -22,6 +22,27 @@
 #define ZYNQMP_TZ_VERSION_MAJOR	1
 #define ZYNQMP_TZ_VERSION_MINOR	0
 
+#define ZYNQMP_ITAPDLYSEL_SD_HSD	0x15
+#define ZYNQMP_ITAPDLYSEL_SDR25		0x15
+#define ZYNQMP_ITAPDLYSEL_SDR50		0x0
+#define ZYNQMP_ITAPDLYSEL_SDR104_B2	0x0
+#define ZYNQMP_ITAPDLYSEL_SDR104_B0	0x0
+#define ZYNQMP_ITAPDLYSEL_MMC_HSD	0x15
+#define ZYNQMP_ITAPDLYSEL_SD_DDR50	0x3D
+#define ZYNQMP_ITAPDLYSEL_MMC_DDR52	0x12
+#define ZYNQMP_ITAPDLYSEL_MMC_HS200_B2	0x0
+#define ZYNQMP_ITAPDLYSEL_MMC_HS200_B0	0x0
+#define ZYNQMP_OTAPDLYSEL_SD_HSD	0x05
+#define ZYNQMP_OTAPDLYSEL_SDR25		0x05
+#define ZYNQMP_OTAPDLYSEL_SDR50		0x03
+#define ZYNQMP_OTAPDLYSEL_SDR104_B0	0x03
+#define ZYNQMP_OTAPDLYSEL_SDR104_B2	0x02
+#define ZYNQMP_OTAPDLYSEL_MMC_HSD	0x06
+#define ZYNQMP_OTAPDLYSEL_SD_DDR50	0x04
+#define ZYNQMP_OTAPDLYSEL_MMC_DDR52	0x06
+#define ZYNQMP_OTAPDLYSEL_MMC_HS200_B0	0x03
+#define ZYNQMP_OTAPDLYSEL_MMC_HS200_B2	0x02
+
 #define ZYNQMP_TZ_VERSION	((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
 					ZYNQMP_TZ_VERSION_MINOR)
 
@@ -65,12 +86,18 @@ enum pm_node_id {
 
 enum pm_ioctl_id {
 	IOCTL_SD_DLL_RESET = 6,
-	IOCTL_SET_PLL_FRAC_MODE = 8,
+	IOCTL_SET_SD_TAPDELAY,
+	IOCTL_SET_PLL_FRAC_MODE,
 	IOCTL_GET_PLL_FRAC_MODE,
 	IOCTL_SET_PLL_FRAC_DATA,
 	IOCTL_GET_PLL_FRAC_DATA,
 };
 
+enum tap_delay_type {
+	PM_TAPDELAY_INPUT,
+	PM_TAPDELAY_OUTPUT,
+};
+
 enum dll_reset_type {
 	PM_DLL_RESET_ASSERT,
 	PM_DLL_RESET_RELEASE,
-- 
2.1.1

[RFC PATCH v2 3/4] sdhci: arasan: Add support to read and set tap delays from DT for ZynqMP

[Manish Narani]

Apart from taps set by auto tuning, ZynqMP platform has feature to set
the tap values manually. Add support to read tap delay values from
DT and set the same in HW via ZynqMP SoC framework. Reading Tap
Delays from DT is optional, if the property is not available in DT the
driver will use the pre-defined Tap Delay Values.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/firmware/xilinx/Makefile            |   1 +
 drivers/firmware/xilinx/zynqmp-tap-delays.c |  39 +++++
 drivers/mmc/host/sdhci-of-arasan.c          | 215 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h        |   4 +
 4 files changed, 259 insertions(+)
 create mode 100644 drivers/firmware/xilinx/zynqmp-tap-delays.c

diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
index 875a537..c32b2a3 100644
--- a/drivers/firmware/xilinx/Makefile
+++ b/drivers/firmware/xilinx/Makefile
@@ -2,4 +2,5 @@
 # Makefile for Xilinx firmwares
 
 obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
+obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp-tap-delays.o
 obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
diff --git a/drivers/firmware/xilinx/zynqmp-tap-delays.c b/drivers/firmware/xilinx/zynqmp-tap-delays.c
new file mode 100644
index 0000000..2e5cab3
--- /dev/null
+++ b/drivers/firmware/xilinx/zynqmp-tap-delays.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Zynq MPSoC Tap Delay Programming
+ *
+ *  Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ *  Manish Narani <mnarani@xilinx.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/**
+ * zynqmp_set_tap_delay - Program the tap delays.
+ * @deviceid:		Unique Id of device
+ * @itap_delay:		Input Tap Delay
+ * @oitap_delay:	Output Tap Delay
+ */
+void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, u8 otap_delay)
+{
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+	u32 node_id = (deviceid == 0) ? NODE_SD_0 : NODE_SD_1;
+
+	if (!eemi_ops || !eemi_ops->ioctl)
+		return;
+
+	/* Set the Input Tap Delay */
+	if (itap_delay)
+		eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
+				PM_TAPDELAY_INPUT, itap_delay, NULL);
+
+	/* Set the Output Tap Delay */
+	if (otap_delay)
+		eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
+				PM_TAPDELAY_OUTPUT, otap_delay, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_set_tap_delay);
+
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 1a8bbd2..57f89af 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -77,6 +77,18 @@ struct sdhci_arasan_soc_ctl_map {
 };
 
 /**
+ * struct sdhci_arasan_zynqmp_data
+ * @mio_bank		Memory IO Bank number
+ * @itapdly		Input Tap Delays array for different host timings
+ * @otapdly		Output Tap Delays array for different host timings
+ */
+struct sdhci_arasan_zynqmp_data {
+	u32 mio_bank;
+	u32 itapdly[MMC_TIMING_MMC_HS400 + 1];
+	u32 otapdly[MMC_TIMING_MMC_HS400 + 1];
+};
+
+/**
  * struct sdhci_arasan_data
  * @host:		Pointer to the main SDHCI host structure.
  * @clk_ahb:		Pointer to the AHB clock
@@ -99,6 +111,7 @@ struct sdhci_arasan_data {
 
 	struct regmap	*soc_ctl_base;
 	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
+	struct sdhci_arasan_zynqmp_data zynqmp_data;
 	unsigned int	device_id;
 	unsigned int	quirks; /* Arasan deviations from spec */
 
@@ -235,7 +248,11 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+	struct device *dev = mmc_dev(host->mmc);
+	unsigned int timing = host->timing;
 	bool ctrl_phy = false;
+	u8 itap_delay;
+	u8 otap_delay;
 
 	if (!IS_ERR(sdhci_arasan->phy)) {
 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
@@ -278,6 +295,17 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 
 	sdhci_set_clock(host, clock);
 
+	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
+		if ((host->version >= SDHCI_SPEC_300) &&
+		    (timing != MMC_TIMING_LEGACY) &&
+		    (timing != MMC_TIMING_UHS_SDR12)) {
+			itap_delay = sdhci_arasan->zynqmp_data.itapdly[timing];
+			otap_delay = sdhci_arasan->zynqmp_data.otapdly[timing];
+			zynqmp_set_tap_delay(sdhci_arasan->device_id,
+					     itap_delay, otap_delay);
+		}
+	}
+
 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
 		/*
 		 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
@@ -723,6 +751,182 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
 	of_clk_del_provider(dev->of_node);
 }
 
+/**
+ * arasan_zynqmp_dt_parse_tap_delays - Read Tap Delay values from DT
+ *
+ * Called at initialization to parse the values of Tap Delays.
+ *
+ * @dev:		Pointer to our struct device.
+ */
+static void arasan_zynqmp_dt_parse_tap_delays(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+	u32 mio_bank = sdhci_arasan->zynqmp_data.mio_bank;
+	u32 *itapdly = sdhci_arasan->zynqmp_data.itapdly;
+	u32 *otapdly = sdhci_arasan->zynqmp_data.otapdly;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	/*
+	 * Read Tap Delay values from DT, if the DT does not contain the
+	 * Tap Values then use the pre-defined values
+	 */
+	ret = of_property_read_u32(np, "xlnx,itap-delay-sd-hsd",
+				   &itapdly[MMC_TIMING_SD_HS]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_SD_HS\n");
+		itapdly[MMC_TIMING_SD_HS] = ZYNQMP_ITAPDLYSEL_SD_HSD;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-sd-hsd",
+				   &otapdly[MMC_TIMING_SD_HS]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_SD_HS\n");
+		otapdly[MMC_TIMING_SD_HS] = ZYNQMP_OTAPDLYSEL_SD_HSD;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-sdr25",
+				   &itapdly[MMC_TIMING_UHS_SDR25]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_UHS_SDR25\n");
+		itapdly[MMC_TIMING_UHS_SDR25] = ZYNQMP_ITAPDLYSEL_SDR25;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-sdr25",
+				   &otapdly[MMC_TIMING_UHS_SDR25]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_UHS_SDR25\n");
+		otapdly[MMC_TIMING_UHS_SDR25] = ZYNQMP_OTAPDLYSEL_SDR25;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-sdr50",
+				   &itapdly[MMC_TIMING_UHS_SDR50]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_UHS_SDR50\n");
+		itapdly[MMC_TIMING_UHS_SDR50] = ZYNQMP_ITAPDLYSEL_SDR50;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-sdr50",
+				   &otapdly[MMC_TIMING_UHS_SDR50]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_UHS_SDR50\n");
+		otapdly[MMC_TIMING_UHS_SDR50] = ZYNQMP_OTAPDLYSEL_SDR50;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-sd-ddr50",
+				   &itapdly[MMC_TIMING_UHS_DDR50]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_UHS_DDR50\n");
+		itapdly[MMC_TIMING_UHS_DDR50] = ZYNQMP_ITAPDLYSEL_SD_DDR50;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-sd-ddr50",
+				   &otapdly[MMC_TIMING_UHS_DDR50]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_UHS_DDR50\n");
+		otapdly[MMC_TIMING_UHS_DDR50] = ZYNQMP_OTAPDLYSEL_SD_DDR50;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-hsd",
+				   &itapdly[MMC_TIMING_MMC_HS]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_MMC_HS\n");
+		itapdly[MMC_TIMING_MMC_HS] = ZYNQMP_ITAPDLYSEL_MMC_HSD;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-hsd",
+				   &otapdly[MMC_TIMING_MMC_HS]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_MMC_HS\n");
+		otapdly[MMC_TIMING_MMC_HS] = ZYNQMP_OTAPDLYSEL_MMC_HSD;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-ddr52",
+				   &itapdly[MMC_TIMING_MMC_DDR52]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_MMC_DDR52\n");
+		itapdly[MMC_TIMING_MMC_DDR52] = ZYNQMP_ITAPDLYSEL_MMC_DDR52;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-ddr52",
+				   &otapdly[MMC_TIMING_MMC_DDR52]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_MMC_DDR52\n");
+		otapdly[MMC_TIMING_MMC_DDR52] = ZYNQMP_OTAPDLYSEL_MMC_DDR52;
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-sdr104",
+				   &itapdly[MMC_TIMING_UHS_SDR104]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_UHS_SDR104\n");
+		if (mio_bank == 2) {
+			itapdly[MMC_TIMING_UHS_SDR104] =
+				ZYNQMP_ITAPDLYSEL_SDR104_B2;
+		} else {
+			itapdly[MMC_TIMING_UHS_SDR104] =
+				ZYNQMP_ITAPDLYSEL_SDR104_B0;
+		}
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-sdr104",
+				   &otapdly[MMC_TIMING_UHS_SDR104]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_UHS_SDR104\n");
+		if (mio_bank == 2) {
+			otapdly[MMC_TIMING_UHS_SDR104] =
+				ZYNQMP_OTAPDLYSEL_SDR104_B2;
+		} else {
+			otapdly[MMC_TIMING_UHS_SDR104] =
+				ZYNQMP_OTAPDLYSEL_SDR104_B0;
+		}
+	}
+
+	ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-hs200",
+				   &itapdly[MMC_TIMING_MMC_HS200]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined itapdly for MMC_TIMING_MMC_HS200\n");
+		if (mio_bank == 2) {
+			itapdly[MMC_TIMING_MMC_HS200] =
+				ZYNQMP_ITAPDLYSEL_MMC_HS200_B2;
+		} else {
+			itapdly[MMC_TIMING_MMC_HS200] =
+				ZYNQMP_ITAPDLYSEL_MMC_HS200_B0;
+		}
+	}
+
+	ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-hs200",
+				   &otapdly[MMC_TIMING_MMC_HS200]);
+	if (ret) {
+		dev_dbg(dev,
+			"Using predefined otapdly for MMC_TIMING_MMC_HS200\n");
+		if (mio_bank == 2) {
+			otapdly[MMC_TIMING_MMC_HS200] =
+				ZYNQMP_OTAPDLYSEL_MMC_HS200_B2;
+		} else {
+			otapdly[MMC_TIMING_MMC_HS200] =
+				ZYNQMP_OTAPDLYSEL_MMC_HS200_B0;
+		}
+	}
+}
+
 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
 {
 	struct sdhci_host *host = sdhci_arasan->host;
@@ -863,6 +1067,15 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 
 	if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) {
 		ret = of_property_read_u32(pdev->dev.of_node,
+					   "xlnx,mio-bank",
+					   &sdhci_arasan->zynqmp_data.mio_bank);
+		if (ret < 0) {
+			dev_err(&pdev->dev,
+				"\"xlnx,mio-bank \" property is missing.\n");
+			goto unreg_clk;
+		}
+
+		ret = of_property_read_u32(pdev->dev.of_node,
 					   "xlnx,device_id",
 					   &sdhci_arasan->device_id);
 		if (ret < 0) {
@@ -871,6 +1084,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
 			goto unreg_clk;
 		}
 
+		arasan_zynqmp_dt_parse_tap_delays(&pdev->dev);
+
 		host->mmc_host_ops.execute_tuning =
 			arasan_zynqmp_execute_tuning;
 	}
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 40feebc..b00388f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -144,11 +144,15 @@ struct zynqmp_eemi_ops {
 
 #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
+/* API for programming the tap delays */
+void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, u8 otap_delay);
 #else
 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 {
 	return NULL;
 }
+inline void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay,
+					u8 otap_delay) {}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.1.1

Re: [RFC PATCH v2 3/4] sdhci: arasan: Add support to read and set tap delays from DT for ZynqMP

[Ulf Hansson]

On 20 September 2018 at 11:30, Manish Narani <manish.narani@xilinx.com> wrote:
> Apart from taps set by auto tuning, ZynqMP platform has feature to set
> the tap values manually. Add support to read tap delay values from
> DT and set the same in HW via ZynqMP SoC framework. Reading Tap
> Delays from DT is optional, if the property is not available in DT the
> driver will use the pre-defined Tap Delay Values.

As far as I understand the Tap Delay Values are properties of the clock signal.

Sounds like the backend part for changing the Tap delay values should
be implemented in the ZynqMP clock driver. Then the arasan mmc driver
should call clk_set|get_phase() to change the values.

Would that work?

Kind regards
Uffe

>
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  drivers/firmware/xilinx/Makefile            |   1 +
>  drivers/firmware/xilinx/zynqmp-tap-delays.c |  39 +++++
>  drivers/mmc/host/sdhci-of-arasan.c          | 215 ++++++++++++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h        |   4 +
>  4 files changed, 259 insertions(+)
>  create mode 100644 drivers/firmware/xilinx/zynqmp-tap-delays.c
>
> diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
> index 875a537..c32b2a3 100644
> --- a/drivers/firmware/xilinx/Makefile
> +++ b/drivers/firmware/xilinx/Makefile
> @@ -2,4 +2,5 @@
>  # Makefile for Xilinx firmwares
>
>  obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o
> +obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp-tap-delays.o
>  obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
> diff --git a/drivers/firmware/xilinx/zynqmp-tap-delays.c b/drivers/firmware/xilinx/zynqmp-tap-delays.c
> new file mode 100644
> index 0000000..2e5cab3
> --- /dev/null
> +++ b/drivers/firmware/xilinx/zynqmp-tap-delays.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx Zynq MPSoC Tap Delay Programming
> + *
> + *  Copyright (C) 2014-2018 Xilinx, Inc.
> + *
> + *  Manish Narani <mnarani@xilinx.com>
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/types.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +/**
> + * zynqmp_set_tap_delay - Program the tap delays.
> + * @deviceid:          Unique Id of device
> + * @itap_delay:                Input Tap Delay
> + * @oitap_delay:       Output Tap Delay
> + */
> +void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, u8 otap_delay)
> +{
> +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
> +       u32 node_id = (deviceid == 0) ? NODE_SD_0 : NODE_SD_1;
> +
> +       if (!eemi_ops || !eemi_ops->ioctl)
> +               return;
> +
> +       /* Set the Input Tap Delay */
> +       if (itap_delay)
> +               eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
> +                               PM_TAPDELAY_INPUT, itap_delay, NULL);
> +
> +       /* Set the Output Tap Delay */
> +       if (otap_delay)
> +               eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
> +                               PM_TAPDELAY_OUTPUT, otap_delay, NULL);
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_set_tap_delay);
> +
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 1a8bbd2..57f89af 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -77,6 +77,18 @@ struct sdhci_arasan_soc_ctl_map {
>  };
>
>  /**
> + * struct sdhci_arasan_zynqmp_data
> + * @mio_bank           Memory IO Bank number
> + * @itapdly            Input Tap Delays array for different host timings
> + * @otapdly            Output Tap Delays array for different host timings
> + */
> +struct sdhci_arasan_zynqmp_data {
> +       u32 mio_bank;
> +       u32 itapdly[MMC_TIMING_MMC_HS400 + 1];
> +       u32 otapdly[MMC_TIMING_MMC_HS400 + 1];
> +};
> +
> +/**
>   * struct sdhci_arasan_data
>   * @host:              Pointer to the main SDHCI host structure.
>   * @clk_ahb:           Pointer to the AHB clock
> @@ -99,6 +111,7 @@ struct sdhci_arasan_data {
>
>         struct regmap   *soc_ctl_base;
>         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
> +       struct sdhci_arasan_zynqmp_data zynqmp_data;
>         unsigned int    device_id;
>         unsigned int    quirks; /* Arasan deviations from spec */
>
> @@ -235,7 +248,11 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> +       struct device *dev = mmc_dev(host->mmc);
> +       unsigned int timing = host->timing;
>         bool ctrl_phy = false;
> +       u8 itap_delay;
> +       u8 otap_delay;
>
>         if (!IS_ERR(sdhci_arasan->phy)) {
>                 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
> @@ -278,6 +295,17 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
>
>         sdhci_set_clock(host, clock);
>
> +       if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
> +               if ((host->version >= SDHCI_SPEC_300) &&
> +                   (timing != MMC_TIMING_LEGACY) &&
> +                   (timing != MMC_TIMING_UHS_SDR12)) {
> +                       itap_delay = sdhci_arasan->zynqmp_data.itapdly[timing];
> +                       otap_delay = sdhci_arasan->zynqmp_data.otapdly[timing];
> +                       zynqmp_set_tap_delay(sdhci_arasan->device_id,
> +                                            itap_delay, otap_delay);
> +               }
> +       }
> +
>         if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
>                 /*
>                  * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
> @@ -723,6 +751,182 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
>         of_clk_del_provider(dev->of_node);
>  }
>
> +/**
> + * arasan_zynqmp_dt_parse_tap_delays - Read Tap Delay values from DT
> + *
> + * Called at initialization to parse the values of Tap Delays.
> + *
> + * @dev:               Pointer to our struct device.
> + */
> +static void arasan_zynqmp_dt_parse_tap_delays(struct device *dev)
> +{
> +       struct platform_device *pdev = to_platform_device(dev);
> +       struct sdhci_host *host = platform_get_drvdata(pdev);
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> +       u32 mio_bank = sdhci_arasan->zynqmp_data.mio_bank;
> +       u32 *itapdly = sdhci_arasan->zynqmp_data.itapdly;
> +       u32 *otapdly = sdhci_arasan->zynqmp_data.otapdly;
> +       struct device_node *np = dev->of_node;
> +       int ret;
> +
> +       /*
> +        * Read Tap Delay values from DT, if the DT does not contain the
> +        * Tap Values then use the pre-defined values
> +        */
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-sd-hsd",
> +                                  &itapdly[MMC_TIMING_SD_HS]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_SD_HS\n");
> +               itapdly[MMC_TIMING_SD_HS] = ZYNQMP_ITAPDLYSEL_SD_HSD;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-sd-hsd",
> +                                  &otapdly[MMC_TIMING_SD_HS]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_SD_HS\n");
> +               otapdly[MMC_TIMING_SD_HS] = ZYNQMP_OTAPDLYSEL_SD_HSD;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-sdr25",
> +                                  &itapdly[MMC_TIMING_UHS_SDR25]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_UHS_SDR25\n");
> +               itapdly[MMC_TIMING_UHS_SDR25] = ZYNQMP_ITAPDLYSEL_SDR25;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-sdr25",
> +                                  &otapdly[MMC_TIMING_UHS_SDR25]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_UHS_SDR25\n");
> +               otapdly[MMC_TIMING_UHS_SDR25] = ZYNQMP_OTAPDLYSEL_SDR25;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-sdr50",
> +                                  &itapdly[MMC_TIMING_UHS_SDR50]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_UHS_SDR50\n");
> +               itapdly[MMC_TIMING_UHS_SDR50] = ZYNQMP_ITAPDLYSEL_SDR50;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-sdr50",
> +                                  &otapdly[MMC_TIMING_UHS_SDR50]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_UHS_SDR50\n");
> +               otapdly[MMC_TIMING_UHS_SDR50] = ZYNQMP_OTAPDLYSEL_SDR50;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-sd-ddr50",
> +                                  &itapdly[MMC_TIMING_UHS_DDR50]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_UHS_DDR50\n");
> +               itapdly[MMC_TIMING_UHS_DDR50] = ZYNQMP_ITAPDLYSEL_SD_DDR50;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-sd-ddr50",
> +                                  &otapdly[MMC_TIMING_UHS_DDR50]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_UHS_DDR50\n");
> +               otapdly[MMC_TIMING_UHS_DDR50] = ZYNQMP_OTAPDLYSEL_SD_DDR50;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-hsd",
> +                                  &itapdly[MMC_TIMING_MMC_HS]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_MMC_HS\n");
> +               itapdly[MMC_TIMING_MMC_HS] = ZYNQMP_ITAPDLYSEL_MMC_HSD;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-hsd",
> +                                  &otapdly[MMC_TIMING_MMC_HS]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_MMC_HS\n");
> +               otapdly[MMC_TIMING_MMC_HS] = ZYNQMP_OTAPDLYSEL_MMC_HSD;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-ddr52",
> +                                  &itapdly[MMC_TIMING_MMC_DDR52]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_MMC_DDR52\n");
> +               itapdly[MMC_TIMING_MMC_DDR52] = ZYNQMP_ITAPDLYSEL_MMC_DDR52;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-ddr52",
> +                                  &otapdly[MMC_TIMING_MMC_DDR52]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_MMC_DDR52\n");
> +               otapdly[MMC_TIMING_MMC_DDR52] = ZYNQMP_OTAPDLYSEL_MMC_DDR52;
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-sdr104",
> +                                  &itapdly[MMC_TIMING_UHS_SDR104]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_UHS_SDR104\n");
> +               if (mio_bank == 2) {
> +                       itapdly[MMC_TIMING_UHS_SDR104] =
> +                               ZYNQMP_ITAPDLYSEL_SDR104_B2;
> +               } else {
> +                       itapdly[MMC_TIMING_UHS_SDR104] =
> +                               ZYNQMP_ITAPDLYSEL_SDR104_B0;
> +               }
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-sdr104",
> +                                  &otapdly[MMC_TIMING_UHS_SDR104]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_UHS_SDR104\n");
> +               if (mio_bank == 2) {
> +                       otapdly[MMC_TIMING_UHS_SDR104] =
> +                               ZYNQMP_OTAPDLYSEL_SDR104_B2;
> +               } else {
> +                       otapdly[MMC_TIMING_UHS_SDR104] =
> +                               ZYNQMP_OTAPDLYSEL_SDR104_B0;
> +               }
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,itap-delay-mmc-hs200",
> +                                  &itapdly[MMC_TIMING_MMC_HS200]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined itapdly for MMC_TIMING_MMC_HS200\n");
> +               if (mio_bank == 2) {
> +                       itapdly[MMC_TIMING_MMC_HS200] =
> +                               ZYNQMP_ITAPDLYSEL_MMC_HS200_B2;
> +               } else {
> +                       itapdly[MMC_TIMING_MMC_HS200] =
> +                               ZYNQMP_ITAPDLYSEL_MMC_HS200_B0;
> +               }
> +       }
> +
> +       ret = of_property_read_u32(np, "xlnx,otap-delay-mmc-hs200",
> +                                  &otapdly[MMC_TIMING_MMC_HS200]);
> +       if (ret) {
> +               dev_dbg(dev,
> +                       "Using predefined otapdly for MMC_TIMING_MMC_HS200\n");
> +               if (mio_bank == 2) {
> +                       otapdly[MMC_TIMING_MMC_HS200] =
> +                               ZYNQMP_OTAPDLYSEL_MMC_HS200_B2;
> +               } else {
> +                       otapdly[MMC_TIMING_MMC_HS200] =
> +                               ZYNQMP_OTAPDLYSEL_MMC_HS200_B0;
> +               }
> +       }
> +}
> +
>  static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
>  {
>         struct sdhci_host *host = sdhci_arasan->host;
> @@ -863,6 +1067,15 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>
>         if (of_device_is_compatible(pdev->dev.of_node, "xlnx,zynqmp-8.9a")) {
>                 ret = of_property_read_u32(pdev->dev.of_node,
> +                                          "xlnx,mio-bank",
> +                                          &sdhci_arasan->zynqmp_data.mio_bank);
> +               if (ret < 0) {
> +                       dev_err(&pdev->dev,
> +                               "\"xlnx,mio-bank \" property is missing.\n");
> +                       goto unreg_clk;
> +               }
> +
> +               ret = of_property_read_u32(pdev->dev.of_node,
>                                            "xlnx,device_id",
>                                            &sdhci_arasan->device_id);
>                 if (ret < 0) {
> @@ -871,6 +1084,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>                         goto unreg_clk;
>                 }
>
> +               arasan_zynqmp_dt_parse_tap_delays(&pdev->dev);
> +
>                 host->mmc_host_ops.execute_tuning =
>                         arasan_zynqmp_execute_tuning;
>         }
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 40feebc..b00388f 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -144,11 +144,15 @@ struct zynqmp_eemi_ops {
>
>  #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
>  const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
> +/* API for programming the tap delays */
> +void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, u8 otap_delay);
>  #else
>  static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
>  {
>         return NULL;
>  }
> +inline void zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay,
> +                                       u8 otap_delay) {}
>  #endif
>
>  #endif /* __FIRMWARE_ZYNQMP_H__ */
> --
> 2.1.1
>

[RFC PATCH v2 4/4] arm64: zynqmp: Add 'xlnx,mio-bank' property in SDHCI node

[Manish Narani]

Add a required property indicating the MIO Bank number for SDHCI
controller in ZynqMP.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 1def7e1..7ef002d 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -492,6 +492,7 @@
 			reg = <0x0 0xff160000 0x0 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
 			xlnx,device_id = <0>;
+			xlnx,mio-bank = <0>;
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -502,6 +503,7 @@
 			reg = <0x0 0xff170000 0x0 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
 			xlnx,device_id = <1>;
+			xlnx,mio-bank = <1>;
 		};
 
 		smmu: smmu@fd800000 {
-- 
2.1.1