* [PATCH 1/3] dt-bindings: display/msm: gpu: Allow multiple digits for patchid
2023-11-30 20:35 [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Luca Weiss
@ 2023-11-30 20:35 ` Luca Weiss
2023-12-01 8:18 ` Krzysztof Kozlowski
2023-11-30 20:35 ` [PATCH 2/3] drm/msm/adreno: Add A305B support Luca Weiss
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Luca Weiss @ 2023-11-30 20:35 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Luca Weiss
Some GPUs like the Adreno A305B has a patchid higher than 9, in this
case 18. Make sure the regexes can account for that.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index b019db954793..40b5c6bd11f8 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -23,7 +23,7 @@ properties:
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
items:
- - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
+ - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Imageon to
@@ -127,7 +127,7 @@ allOf:
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
then:
properties:
@@ -203,7 +203,7 @@ allOf:
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Allow multiple digits for patchid
2023-11-30 20:35 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Allow multiple digits for patchid Luca Weiss
@ 2023-12-01 8:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-01 8:18 UTC (permalink / raw)
To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Rob Clark,
Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 30/11/2023 21:35, Luca Weiss wrote:
> Some GPUs like the Adreno A305B has a patchid higher than 9, in this
> case 18. Make sure the regexes can account for that.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] drm/msm/adreno: Add A305B support
2023-11-30 20:35 [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Luca Weiss
2023-11-30 20:35 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Allow multiple digits for patchid Luca Weiss
@ 2023-11-30 20:35 ` Luca Weiss
2023-12-01 21:53 ` Konrad Dybcio
2023-12-25 21:12 ` Luca Weiss
2023-11-30 20:35 ` [PATCH 3/3] ARM: dts: qcom: msm8226: Add GPU Luca Weiss
2023-12-10 23:25 ` (subset) [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Bjorn Andersson
3 siblings, 2 replies; 8+ messages in thread
From: Luca Weiss @ 2023-11-30 20:35 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Luca Weiss
Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
Previously this was mistakenly claimed to be supported but using wrong
a configuration.
In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
should work with the same configuration but due to lack of hardware for
testing this is not added.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 15 ++++++++++++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++++++++----
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
3 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index c86b377f6f0d..5fc29801c4c7 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
/* Set up AOOO: */
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
+ } else if (adreno_is_a305b(adreno_gpu)) {
+ gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
+ gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);
+ gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);
+ gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
} else if (adreno_is_a306(adreno_gpu)) {
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
@@ -230,7 +237,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
/* Enable Clock gating: */
- if (adreno_is_a306(adreno_gpu))
+ if (adreno_is_a305b(adreno_gpu))
+ gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
+ else if (adreno_is_a306(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
@@ -333,7 +342,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
- } else if (adreno_is_a330(adreno_gpu)) {
+ } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
/* NOTE: this (value take from downstream android driver)
* includes some bits outside of the known bitfields. But
* A330 has this "MERCIU queue" thing too, which might
@@ -559,7 +568,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
goto fail;
/* if needed, allocate gmem: */
- if (adreno_is_a330(adreno_gpu)) {
+ if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
adreno_gpu, &a3xx_gpu->ocmem);
if (ret)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index f62ab5257e66..7028d5449956 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03000512,
- 0x03000520
- ),
+ .chip_ids = ADRENO_CHIP_IDS(0x03000512),
+ .family = ADRENO_3XX,
+ .fw = {
+ [ADRENO_FW_PM4] = "a330_pm4.fw",
+ [ADRENO_FW_PFP] = "a330_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000520),
.family = ADRENO_3XX,
.revn = 305,
.fw = {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 80b3f6312116..c654f21499bb 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -247,6 +247,11 @@ static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
return adreno_is_revn(gpu, 305);
}
+static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x03000512;
+}
+
static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
{
/* yes, 307, because a305c is 306 */
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] drm/msm/adreno: Add A305B support
2023-11-30 20:35 ` [PATCH 2/3] drm/msm/adreno: Add A305B support Luca Weiss
@ 2023-12-01 21:53 ` Konrad Dybcio
2023-12-25 21:12 ` Luca Weiss
1 sibling, 0 replies; 8+ messages in thread
From: Konrad Dybcio @ 2023-12-01 21:53 UTC (permalink / raw)
To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Rob Clark,
Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 30.11.2023 21:35, Luca Weiss wrote:
> Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
> Previously this was mistakenly claimed to be supported but using wrong
> a configuration.
>
> In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
> should work with the same configuration but due to lack of hardware for
> testing this is not added.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 15 ++++++++++++---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++++++++----
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> 3 files changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index c86b377f6f0d..5fc29801c4c7 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> /* Set up AOOO: */
> gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
> + } else if (adreno_is_a305b(adreno_gpu)) {
> + gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
> + gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);
> + gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);
> + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> } else if (adreno_is_a306(adreno_gpu)) {
> gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
> @@ -230,7 +237,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
>
> /* Enable Clock gating: */
> - if (adreno_is_a306(adreno_gpu))
> + if (adreno_is_a305b(adreno_gpu))
> + gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
> + else if (adreno_is_a306(adreno_gpu))
> gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
||?
[...]
Otherwise looks in line with msm-3.10
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] drm/msm/adreno: Add A305B support
2023-11-30 20:35 ` [PATCH 2/3] drm/msm/adreno: Add A305B support Luca Weiss
2023-12-01 21:53 ` Konrad Dybcio
@ 2023-12-25 21:12 ` Luca Weiss
1 sibling, 0 replies; 8+ messages in thread
From: Luca Weiss @ 2023-12-25 21:12 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On Donnerstag, 30. November 2023 21:35:19 CET Luca Weiss wrote:
> Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
> Previously this was mistakenly claimed to be supported but using wrong
> a configuration.
>
> In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
> should work with the same configuration but due to lack of hardware for
> testing this is not added.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Hi all,
Any chance this can be picked up for v6.8? The dts patch has already been
picked up :)
Regards
Luca
> ---
> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 15 ++++++++++++---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++++++++----
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> 3 files changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index c86b377f6f0d..5fc29801c4c7
> 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> /* Set up AOOO: */
> gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
> + } else if (adreno_is_a305b(adreno_gpu)) {
> + gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
> + gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0,
0x00000018);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0,
0x00000018);
> + gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST,
0x00000303);
> + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> } else if (adreno_is_a306(adreno_gpu)) {
> gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0,
0x0000000a);
> @@ -230,7 +237,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
>
> /* Enable Clock gating: */
> - if (adreno_is_a306(adreno_gpu))
> + if (adreno_is_a305b(adreno_gpu))
> + gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
> + else if (adreno_is_a306(adreno_gpu))
> gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
> else if (adreno_is_a320(adreno_gpu))
> gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
> @@ -333,7 +342,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
>
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
>
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
>
AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
> - } else if (adreno_is_a330(adreno_gpu)) {
> + } else if (adreno_is_a330(adreno_gpu) ||
adreno_is_a305b(adreno_gpu)) {
> /* NOTE: this (value take from downstream android driver)
> * includes some bits outside of the known bitfields. But
> * A330 has this "MERCIU queue" thing too, which might
> @@ -559,7 +568,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
> goto fail;
>
> /* if needed, allocate gmem: */
> - if (adreno_is_a330(adreno_gpu)) {
> + if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
> ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
> adreno_gpu, &a3xx_gpu-
>ocmem);
> if (ret)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c index
> f62ab5257e66..7028d5449956 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a2xx_gpu_init,
> }, {
> - .chip_ids = ADRENO_CHIP_IDS(
> - 0x03000512,
> - 0x03000520
> - ),
> + .chip_ids = ADRENO_CHIP_IDS(0x03000512),
> + .family = ADRENO_3XX,
> + .fw = {
> + [ADRENO_FW_PM4] = "a330_pm4.fw",
> + [ADRENO_FW_PFP] = "a330_pfp.fw",
> + },
> + .gmem = SZ_128K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a3xx_gpu_init,
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x03000520),
> .family = ADRENO_3XX,
> .revn = 305,
> .fw = {
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 80b3f6312116..c654f21499bb
> 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -247,6 +247,11 @@ static inline bool adreno_is_a305(const struct
> adreno_gpu *gpu) return adreno_is_revn(gpu, 305);
> }
>
> +static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
> +{
> + return gpu->info->chip_ids[0] == 0x03000512;
> +}
> +
> static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
> {
> /* yes, 307, because a305c is 306 */
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] ARM: dts: qcom: msm8226: Add GPU
2023-11-30 20:35 [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Luca Weiss
2023-11-30 20:35 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Allow multiple digits for patchid Luca Weiss
2023-11-30 20:35 ` [PATCH 2/3] drm/msm/adreno: Add A305B support Luca Weiss
@ 2023-11-30 20:35 ` Luca Weiss
2023-12-10 23:25 ` (subset) [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Luca Weiss @ 2023-11-30 20:35 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Luca Weiss
The msm8226 SoC contains an Adreno 305B. Add a node to configure it.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
index 5cd03ea7b084..9b43766df8f8 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
@@ -1006,6 +1006,46 @@ mdss_dsi0_phy: phy@fd922a00 {
"ref";
};
};
+
+ gpu: adreno@fdb00000 {
+ compatible = "qcom,adreno-305.18", "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ clock-names = "core", "iface", "mem_iface";
+
+ sram = <&gmu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-19000000 {
+ opp-hz = /bits/ 64 <19000000>;
+ };
+ };
+ };
};
thermal-zones {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: (subset) [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B)
2023-11-30 20:35 [PATCH 0/3] Add GPU support for MSM8226 (Adreno A305B) Luca Weiss
` (2 preceding siblings ...)
2023-11-30 20:35 ` [PATCH 3/3] ARM: dts: qcom: msm8226: Add GPU Luca Weiss
@ 2023-12-10 23:25 ` Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2023-12-10 23:25 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Daniel Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Konrad Dybcio, Luca Weiss
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On Thu, 30 Nov 2023 21:35:17 +0100, Luca Weiss wrote:
> Add the necessary bits to bring up the GPU on msm8226.
>
> Tested on apq8026-lg-lenok.
>
>
Applied, thanks!
[3/3] ARM: dts: qcom: msm8226: Add GPU
commit: fc209f869310776c437daba478246df64d82c38b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread