From: Wei Wang <wei.w.wang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
pbonzini@redhat.com, ak@linux.intel.com, peterz@infradead.org
Cc: mingo@redhat.com, rkrcmar@redhat.com, like.xu@intel.com,
wei.w.wang@intel.com
Subject: [PATCH v1 2/8] perf/x86/intel: add pmi callback support
Date: Thu, 1 Nov 2018 18:04:02 +0800 [thread overview]
Message-ID: <1541066648-40690-3-git-send-email-wei.w.wang@intel.com> (raw)
In-Reply-To: <1541066648-40690-1-git-send-email-wei.w.wang@intel.com>
This patch adds the pmi callback support for the counters reserved by
components outside the perf core. For example, a hypervisor may register
such a callback to get the guest notified about the receiving of the
pmi.
The host PMI handling requires the active_events to be non-zero, so we
need active_events to be at least 1 in x86_perf_mask_perf_counters when
there are counters used by the guest.
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/events/core.c | 10 ++++++++++
arch/x86/events/intel/core.c | 27 +++++++++++++++++++++++++++
arch/x86/events/perf_event.h | 4 ++++
arch/x86/include/asm/perf_event.h | 5 +++++
4 files changed, 46 insertions(+)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index e73135a..504d102 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2408,6 +2408,16 @@ void x86_perf_mask_perf_counters(u64 mask)
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
/*
+ * Increment active_events by 1 if there are counters reserved for
+ * the guest to use, and no need to do more increments if there are
+ * already counters taken by the guest.
+ */
+ if (!cpuc->intel_ctrl_guest_mask && mask)
+ atomic_inc(&active_events);
+ else if (cpuc->intel_ctrl_guest_mask && !mask)
+ atomic_dec(&active_events);
+
+ /*
* If the counter happens to be used by a host event, take it back
* first, and then restart the pmu after mask that counter as being
* reserved.
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 0fb8659..f5e5191 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2283,6 +2283,13 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
*/
status |= cpuc->intel_cp_status;
+ if (status & cpuc->intel_ctrl_guest_mask) {
+ cpuc->pmi_callback(cpuc->pmi_opaque,
+ status & cpuc->intel_ctrl_guest_mask);
+ status &= ~cpuc->intel_ctrl_guest_mask;
+ handled++;
+ }
+
for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
struct perf_event *event = cpuc->events[bit];
@@ -3162,6 +3169,26 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
}
EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
+void x86_perf_register_pmi_callback(pmi_callback_t callback, void *opaque)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+
+ cpuc->pmi_callback = callback;
+ cpuc->pmi_opaque = opaque;
+
+ apic_write(APIC_LVTPC, APIC_DM_NMI);
+}
+EXPORT_SYMBOL_GPL(x86_perf_register_pmi_callback);
+
+void x86_perf_unregister_pmi_callback(void)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+
+ cpuc->pmi_callback = NULL;
+ cpuc->pmi_opaque = NULL;
+}
+EXPORT_SYMBOL_GPL(x86_perf_unregister_pmi_callback);
+
static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index adae087..06404eb 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -197,6 +197,10 @@ struct cpu_hw_events {
unsigned int txn_flags;
int is_fake;
+ /* PMI related fields */
+ pmi_callback_t pmi_callback;
+ void *pmi_opaque;
+
/*
* Intel DebugStore bits
*/
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 5b4463e..fd33688 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -275,6 +275,8 @@ struct perf_guest_switch_msr {
u64 host, guest;
};
+typedef void (*pmi_callback_t)(void *opaque, u64 status);
+
extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
extern void perf_check_microcode(void);
@@ -298,6 +300,9 @@ static inline void perf_check_microcode(void) { }
#ifdef CONFIG_CPU_SUP_INTEL
extern void intel_pt_handle_vmx(int on);
extern void x86_perf_mask_perf_counters(u64 mask);
+extern void x86_perf_register_pmi_callback(pmi_callback_t callback,
+ void *opaque);
+extern void x86_perf_unregister_pmi_callback(void);
#endif
#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
--
2.7.4
next prev parent reply other threads:[~2018-11-01 10:36 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 10:04 [PATCH v1 0/8] Intel Virtual PMU Optimization Wei Wang
2018-11-01 10:04 ` [PATCH v1 1/8] perf/x86: add support to mask counters from host Wei Wang
2018-11-01 14:52 ` Peter Zijlstra
2018-11-02 9:08 ` Wei Wang
2018-11-05 9:34 ` Peter Zijlstra
2018-11-05 11:19 ` Wei Wang
2018-11-05 12:14 ` Peter Zijlstra
2018-11-05 15:37 ` Wang, Wei W
2018-11-05 16:56 ` Peter Zijlstra
2018-11-05 18:20 ` Andi Kleen
2018-11-01 10:04 ` Wei Wang [this message]
2018-11-01 10:04 ` [PATCH v1 3/8] KVM/x86/vPMU: optimize intel vPMU Wei Wang
2018-11-01 10:04 ` [PATCH v1 4/8] KVM/x86/vPMU: support msr switch on vmx transitions Wei Wang
2018-11-01 10:04 ` [PATCH v1 5/8] KVM/x86/vPMU: intel_pmu_read_pmc Wei Wang
2018-11-01 10:04 ` [PATCH v1 6/8] KVM/x86/vPMU: remove some unused functions Wei Wang
2018-11-01 10:04 ` [PATCH v1 7/8] KVM/x86/vPMU: save/restore guest perf counters on vCPU switching Wei Wang
2018-11-01 10:04 ` [PATCH v1 8/8] KVM/x86/vPMU: return the counters to host if guest is torn down Wei Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1541066648-40690-3-git-send-email-wei.w.wang@intel.com \
--to=wei.w.wang@intel.com \
--cc=ak@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=like.xu@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=rkrcmar@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).