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From: Wei Wang <wei.w.wang@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	pbonzini@redhat.com, ak@linux.intel.com, mingo@redhat.com,
	rkrcmar@redhat.com, like.xu@intel.com
Subject: Re: [PATCH v1 1/8] perf/x86: add support to mask counters from host
Date: Fri, 02 Nov 2018 17:08:31 +0800	[thread overview]
Message-ID: <5BDC140F.6060303@intel.com> (raw)
In-Reply-To: <20181101145257.GD3178@hirez.programming.kicks-ass.net>

On 11/01/2018 10:52 PM, Peter Zijlstra wrote:
> On Thu, Nov 01, 2018 at 06:04:01PM +0800, Wei Wang wrote:
>> Add x86_perf_mask_perf_counters to reserve counters from the host perf
>> subsystem. The masked counters will not be assigned to any host perf
>> events. This can be used by the hypervisor to reserve perf counters for
>> a guest to use.
>>
>> This function is currently supported on Intel CPUs only, but put in x86
>> perf core because the counter assignment is implemented here and we need
>> to re-enable the pmu which is defined in the x86 perf core in the case
>> that a counter to be masked happens to be used by the host.
>>
>> Signed-off-by: Wei Wang <wei.w.wang@intel.com>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Andi Kleen <ak@linux.intel.com>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>>   arch/x86/events/core.c            | 37 +++++++++++++++++++++++++++++++++++++
>>   arch/x86/include/asm/perf_event.h |  1 +
>>   2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
>> index 106911b..e73135a 100644
>> --- a/arch/x86/events/core.c
>> +++ b/arch/x86/events/core.c
>> @@ -716,6 +716,7 @@ struct perf_sched {
>>   static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
>>   			    int num, int wmin, int wmax, int gpmax)
>>   {
>> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>>   	int idx;
>>   
>>   	memset(sched, 0, sizeof(*sched));
>> @@ -723,6 +724,9 @@ static void perf_sched_init(struct perf_sched *sched, struct event_constraint **
>>   	sched->max_weight	= wmax;
>>   	sched->max_gp		= gpmax;
>>   	sched->constraints	= constraints;
>> +#ifdef CONFIG_CPU_SUP_INTEL
>> +	sched->state.used[0]	= cpuc->intel_ctrl_guest_mask;
>> +#endif
> NAK.  This completely undermines the whole purpose of event scheduling.
>

Hi Peter,

Could you share more details how it would affect the host side event 
scheduling?

We wanted to partition out the perf counters that the guest needs and
dedicated them to guest usages for that period (i.e. guest occupation 
period).
The remaining counters are still schedulable for the host events (there 
won't be
many other perf events when the guest runs, watchdog_hld seems to be the one
that would).

Would you have any suggestions? Thanks.

Best,
Wei







  reply	other threads:[~2018-11-02  9:03 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01 10:04 [PATCH v1 0/8] Intel Virtual PMU Optimization Wei Wang
2018-11-01 10:04 ` [PATCH v1 1/8] perf/x86: add support to mask counters from host Wei Wang
2018-11-01 14:52   ` Peter Zijlstra
2018-11-02  9:08     ` Wei Wang [this message]
2018-11-05  9:34       ` Peter Zijlstra
2018-11-05 11:19         ` Wei Wang
2018-11-05 12:14           ` Peter Zijlstra
2018-11-05 15:37             ` Wang, Wei W
2018-11-05 16:56               ` Peter Zijlstra
2018-11-05 18:20               ` Andi Kleen
2018-11-01 10:04 ` [PATCH v1 2/8] perf/x86/intel: add pmi callback support Wei Wang
2018-11-01 10:04 ` [PATCH v1 3/8] KVM/x86/vPMU: optimize intel vPMU Wei Wang
2018-11-01 10:04 ` [PATCH v1 4/8] KVM/x86/vPMU: support msr switch on vmx transitions Wei Wang
2018-11-01 10:04 ` [PATCH v1 5/8] KVM/x86/vPMU: intel_pmu_read_pmc Wei Wang
2018-11-01 10:04 ` [PATCH v1 6/8] KVM/x86/vPMU: remove some unused functions Wei Wang
2018-11-01 10:04 ` [PATCH v1 7/8] KVM/x86/vPMU: save/restore guest perf counters on vCPU switching Wei Wang
2018-11-01 10:04 ` [PATCH v1 8/8] KVM/x86/vPMU: return the counters to host if guest is torn down Wei Wang

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